The MAX2838 direct-conversion, zero-IF, RF transceiver is designed specifically for 3.3GHz to 3.9GHz wireless broadband systems. The MAX2838 completely
integrates all circuitry required to implement the RF
transceiver function, providing RF-to-baseband receive
path, baseband-to-RF transmit path, VCO, frequency
synthesizer, and baseband/control interface. The
device includes a fast-settling sigma-delta RF synthesizer with smaller than 29Hz frequency steps. The
MAX2838 supports 2Tx, 2Rx MIMO applications with a
master device providing coherent LO to the slave
device. The transceiver IC also integrates circuits for
on-chip DC-offset cancellation, I/Q error, and carrierleakage detection circuits. Only an RF bandpass filter
(BPF), TCXO, RF switch, PA, and a small number of
passive components are needed to form a complete
wireless broadband RF radio solution.
The MAX2838 completely eliminates the need for an
external SAW filter by implementing on-chip monolithic
filters for both the receiver and transmitter. The baseband filters along with the Rx and Tx signal paths are
optimized to meet the stringent noise figure and linearity specifications. The device supports up to 2048-FFT
OFDM and implements programmable channel filters
for 1.5MHz to 28MHz RF channel bandwidths. The
transceiver requires only 2µs Tx-Rx switching time. The
IC is available in a small 48-pin thin QFN package measuring only 6mm x 6mm x 0.8mm.
Applications
802.16-2004/802.16d Fixed WiMAX™
802.16e MIMO Mobile WiMAX
WiMAX Pico and Femto Basestations
NLOS Wireless Broadband Systems
Features
♦ 3.3GHz to 3.9GHz Wide-Band Operation
♦ Master-Slave Modes with Coherent LO for MIMO
♦ Complete RF Transceiver, and PA Driver
0dBm Linear OFDM Transmit Power
-70dBr Tx Spectral Emission Mask
2.8dB Rx Noise Figure
Tx/Rx I/Q Error and LO Leakage Detection and
Adjustment
Automatic Rx DC Offset Correction
Monolithic Low-Noise VCO with -39dBc Integrated
Phase Noise
Programmable Rx I/Q Lowpass Channel Filters
Programmable Tx I/Q Lowpass Anti-Aliasing Filter
Sigma-Delta Fractional-N PLL with 29Hz Step Size
60dB Tx Gain Control Range with 1dB Step Size,
Digitally Controlled
94dB Rx Gain Control Range with 2dB Step Size,
Digitally Controlled
60dB Analog RSSI Instantaneous Dynamic Range
4-Wire SPI™ Digital Interface
I/Q Analog Baseband Interface
Digital Tx/Rx/Shutdown Mode Control
Low-Power CLOCKOUT Mode
On-Chip Digital Temperature Sensor Readout
♦ +2.7V to +3.6V Transceiver Supply
♦ Low-Power Shutdown Mode
♦ Small 48-Pin Thin QFN Package (6mm x 6mm x 0.8mm)
(MAX2838 Evaluation Kit, VCC_ = 2.7V to 3.6V, TA= -40°C to +85°C, ENABLE and RXTX set according to operating mode, CS =
high, SCLK = DIN = low, transmitter and receiver in maximum gain, no input signal at RF inputs, all RF inputs and outputs terminated
into 50Ω, receiver baseband outputs are open. 90mV
RMS
differential I and Q signals (1MHz) applied to I and Q baseband inputs of
transmitter in transmit mode, all registers set to recommended settings and corresponding test mode, unless otherwise noted.
Typical values are at V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC_
Pins to GND..................................................-0.3V to +3.6V
RF Inputs: RXRF+, RXRF-, EXTVCO+,
EXTVCO- to GND ................................................-0.3V to +3.6V
RF Outputs: TXRF+, TXRF-, EXTVCO+,
EXTVCO- to GND ................................................-0.3V to +3.6V
Analog Inputs: TXBBI+, TXBBI-, TXBBQ+,
TXBBQ-, REFCLK to GND ...................................-0.3V to +3.6V
Analog Outputs: RXBBI+, RXBBI-, RXBBQ+,
RXBBQ-, RSSI, VCOBYP, CPOUT+, CPOUT-,
PABIAS to GND ...................................................-0.3V to +3.6V
Digital Inputs: ENABLE, RXTX, CS, SCLK,
DIN, RXHP B1–B7 to GND ..................................-0.3V to +3.6V
Digital Outputs: DOUT, CLKOUT to GND .............-0.3V to +3.6V
= 40MHz, CS = ENABLE = RXTX = high, SCLK = DIN = low, channel bandwidth BW = 7MHz, with power matching for the RF inputs
using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted.
Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless
otherwise indicated. Rx I/Q differential output load impedance = 10kΩ || 8pF.) (Note 1)
DC ELECTRICAL CHARACTERISTICS (continued)
(MAX2838 Evaluation Kit, VCC_ = 2.7V to 3.6V, TA= -40°C to +85°C, ENABLE and RXTX set according to operating mode, CS =
high, SCLK = DIN = low, transmitter and receiver in maximum gain, no input signal at RF inputs, all RF inputs and outputs terminated
into 50Ω, receiver baseband outputs are open. 90mV
RMS
differential I and Q signals (1MHz) applied to I and Q baseband inputs of
transmitter in transmit mode, all registers set to recommended settings and corresponding test mode, unless otherwise noted.
Typical values are at V
= 40MHz, CS = ENABLE = RXTX = high, SCLK = DIN = low, channel bandwidth BW = 7MHz, with power matching for the RF inputs
using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted.
Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless
otherwise indicated. Rx I/Q differential output load impedance = 10kΩ || 8pF.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
DSB Noise Figure
In-Band Input P-1dB
Maximum Output Signal Level
Out-of-Band Input IP3 (Note 2)
I/Q Phase Error1MHz baseband output; 1 σ variation, TA = +25°C0.15D eg r ees
I/Q Gain Imbalance1MHz baseband output; 1 σ variation, TA = +25°C0.05dB
I/Q Output DC Droop
I/Q Static DC Offset
Loopback Gain (for Receiver I/Q
Calibration)
RECEIVER BASEBAND FILTERS
Baseband Highpass Filter Corner
Frequency
Voltage gain ≥ 65dB with max RF gain (B7:B6 = 00)2.9
V ol tag e g ai n = 50d B w i th m ax RF g ai n - 8d B ( B7:B6 = 01) 7.9
V ol tag e g ai n = 45d B w i th m ax RF g ai n - 16d B ( B7:B6 = 10) 13.7
V ol tag e g ai n = 15d B w i th m ax RF g ai n - 32d B ( B7:B6 = 11) 31.4
Max RF gain (B7:B6 = 00)-35
Max RF gain - 8dB (B7:B6 = 01)-27
Max RF gain - 16dB (B7:B6 = 10)-19
Max RF gain - 32dB (B7:B6 = 11)-3
Over passband frequency range; at any gain setting;
1dB compression point, differential output
Max RF gain (B7:B6 = 00), AGC set for -65dBm wanted
signal
Max RF gain - 8dB (B7:B6 = 01), AGC set for -55dBm
wanted signal
Max RF gain - 16dB (B7:B6 = 10), AGC set for -40dBm
wanted signal
Max RF gain - 32dB (B7:B6 = 11), AGC set for -30dBm
wanted signal
After completion of default power-on on-chip DC
cancellation, 1 σ variation
N o RF i np ut si g nal ; B7:B1 = 0000000, after com p l eti on of
d efaul t p ow er - on on- chi p D C cancel l ati on, 1 σ var i ati on
Tr ansm itter I/Q i nput to r ecei ver I/Q outp ut; tr ansm i tter B6:B1 =
000011, r ecei ver B5:B1 = 10011 p r og r am m ed thr oug h S P I
= 40MHz, CS = ENABLE = RXTX = high, SCLK = DIN = low, channel bandwidth BW = 7MHz, with power matching for the RF inputs
using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted.
Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless
otherwise indicated. Rx I/Q differential output load impedance = 10kΩ || 8pF.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
A4:A0 = 00010 serial bits D7:D4 = 00001.5
A4:A0 = 00010 serial bits D7:D4 = 00011.75
A4:A0 = 00010 serial bits D7:D4 = 00103.5
A4:A0 = 00010 serial bits D7:D4 = 00115.0
A4:A0 = 00010 serial bits D7:D4 = 01005.5
A4:A0 = 00010 serial bits D7:D4 = 01016.0
A4:A0 = 00010 serial bits D7:D4 = 01107.0
RF Channel BW Supported by
Baseband Filter
Baseband Gain Ripple0 to 3.2MHz for BW = 7MHz1dB
Baseband Group Delay Ripple0 to 3.2MHz for BW = 7MHz65ns
Baseband Filter Rejection for
7MHz RF Channel BW
RSSI
RSSI Minimum Output VoltageR
RSSI Maximum Output VoltageR
RSSI Slope30mV/dB
RSSI Output Settling Time
A4:A0 = 00010 serial bits D7:D4 = 01118.0
A4:A0 = 00010 serial bits D7:D4 = 10009.0
A4:A0 = 00010 serial bits D7:D4 = 100110.0
A4:A0 = 00010 serial bits D7:D4 = 101012.0
A4:A0 = 00010 serial bits D7:D4 = 101114.0
A4:A0 = 00010 serial bits D7:D4 = 110015.0
A4:A0 = 00010 serial bits D7:D4 = 110120.0
A4:A0 = 00010 serial bits D7:D4 = 111024.0
A4:A0 = 00010 serial bits D7:D4 = 111128.0
At 4.67MHz7
At > 10.5MHz53
At > 14MHz75
At > 29.4MHz75
≥ 10kΩ0.65V
LOAD
≥ 10kΩ2.4V
LOAD
To within 3dB of steady
state
+32dB signal step200
-32dB signal step800
MHz
dB
ns
P-P
P-P
MAX2838
3.3GHz to 3.9GHz
Wireless Broadband RF Transceiver
= SCLK = DIN = low, with power matching for the differential RF pins using the
Typical Operating Circuit
. Lowpass filter is set to
7MHz RF channel BW, 90mV
RMS
sine and cosine signal (or 90mV
RMS
64QAM 1024-FFT OFDMA FUSC I/Q signals wherever OFDM
is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommended settings and
corresponding test mode, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS—FREQUENCY SYNTHESIS
(MAX2838 Evaluation Kit, VCC= 2.8V, TA= +25°C, fLO= 3.6GHz, f
REF
= 40MHz, CS = high, SCLK = DIN = low, PLL loop bandwidth
= 180kHz, charge-pump comparison frequency = 40MHz, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS
RF Output Frequency Range3.33.9GHz
Peak-to-Peak Gain Variation over
RF Band
Total Voltage GainMaximum gain; at unbalanced 50Ω matched output8dB
Maximum Output Power over
Frequency
RF Output Return LossAll gain settings7dB
RF Gain Control Range60dB
RF Gain Control Binary Weights
Unwanted Sideband Suppression
Carrier LeakageRel ati ve to 0d Bm outp ut p ow er ; w i thout cal i b r ati on b y m od em -40dBc
Tx I/Q Input Impedance (R || C)
Baseband Frequency Response
for 7MHz RF Channel BW
Baseband Group Delay Ripple0 to 4.9MHz (BW = 7MHz)15ns
O FD M si g nal confor m i ng to sp ectr al em i ssi on m ask and
- 36d B EV M after I/Q i m bal ance cal i br ation by m od em ( N ote 3)
B11
B22
B34
B48
B516
B632
Without calibration by modem, and excludes modem I/Q
imbalance; P
Minimum differential resistance60kΩ
Maximum differential capacitance0.5pF
0 to 4.67MHz-8
At > 13.23MHz-45
OUT
= 0dBm
2.6dB
0dBm
-40dBc
dB
dB
P-P
PARAMETERCONDITIONSMINTYPMAXUNITS
FREQUENCY SYNTHESIZER
RF Channel Center Frequency3.33.9GHz
Channel Center Frequency
Programming Minimum Step Size
Charge-Pump Comparison
Frequency
Reference Frequency Range114080MHz
Refer ence Fr eq uency Inp ut Level sAC-coupled to REFCLK pin800mV
1VCCRXLNALNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
2GNDRXLNA LNA Ground
3B5Receiver and Transmitter Gain-Control Logic Input Bit 5
4RXRF+
5RXRF-
6B4Receiver and Transmitter Gain-Control Logic Input Bit 4
7VCCTXPAD Supply Voltage for Power-Amplifier Driver. Bypass with a capacitor as close as possible to the pin.
8B3Receiver and Transmitter Gain-Control Logic Input Bit 3
9B2Receiver and Transmitter Gain-Control Logic Input Bit 2
10TXRF+
11TXRF-
12B1Receiver and Transmitter Gain-Control Logic Input Bit 1
13PABIASTransmit PA Bias DAC Output
14VCCTXMXTransmitter Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
15CSChip-Select Logic Input of 4-Wire Serial Interface (See Figure 1)
16SCLKSerial-Clock Logic Input of 4-Wire Serial Interface (See Figure 1)
17CLKOUTReference Clock Divided Output
18VCCDIGDigital Circuit Supply Voltage. Bypass with a capacitor as close as possible to the pin.
19REFCLKReference Clock Input
20VCCCPPLL Charge-Pump Supply Voltage. Bypass with a capacitor as close as possible to the pin.
21GNDCPCharge-Pump Circuit Ground
22CPOUT+
23CPOUT-
24GNDVCOVCO Ground
25VCOBYP
26VCCVCOVCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.
27VCCLOLO Generation Supply Voltage. Bypass with a capacitor as close as possible to the pin.
28EXTVCO-
29EXTVCO+
30DOUTData Logic Output of 4-Wire Serial Interface (See Figure 1)
31DINData Logic Input of 4-Wire Serial Interface (See Figure 1)
32RSSIRSSI or Temperature Sensor Multiplexed Analog Output
33B7Receiver Gain-Control Logic Input Bit 7
34B6Receiver and Transmitter Gain-Control Logic Input Bit 6
35RXBBQ-
36RXBBQ+
37RXBBI-
38RXBBI+
39VCCRXVGA Receiver VGA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
LNA Differential Inputs. Inputs are internally DC-coupled. Two external series capacitors and one
shunt inductor match the inputs to 100Ω differential.
Power-Amplifier Driver Differential Output. Outputs are internally DC-coupled. Two external series
capacitors and one shunt inductor match the outputs to 100Ω differential.
Differential Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT+
and CPOUT- (see the Typical Operating Circuit).
On-Chip VCO Regulator Output Bypass. Bypass with a 1µF capacitor to GND. Do not connect other
circuitry to this point.
External VCO Differential Input or Output. Input for slave configuration and output for master
configuration. Leave unconnected for single configuration.
Receiver Baseband Q-Channel Differential Outputs. In Tx calibration mode, these pins are the LO
leakage and sideband detector outputs.
Receiver Baseband I-Channel Differential Outputs. In Tx calibration mode, these pins are the LO
leakage and sideband detector outputs.
MAX2838
3.3GHz to 3.9GHz
Wireless Broadband RF Transceiver
Table 1. Operating Mode for MIMO Master and Single Configuration (Note 5)
Note 5: Set SPI Reg 24 D1:D0 = “00” for single-transceiver mode of operation. Set SPI Reg 16 D4:D3 = “11,” Reg 24 D8 = “1,” Reg
24 D1:D0 = “01” for MIMO master configuration.
Note 6: Unused states of SPI Reg 16, D1:D0 above are not tested, and therefore, should not be used.
Note 7: Parts of transceiver may be selectively enabled.
Note 8: PA bias DAC may be kept active in these non-transmit mode(s) by SPI programming.
Note 9: Set SPI Reg 5 D5 = “1” to mux AM detector output to RXBB pins.
Note 10: Set SPI Reg 26 D3 = “1.”
Note 11: CLKOUT signal is active independent of the states of SPI Reg 16, D1:D0, and is only dependent on the states of ENABLE
and RXTX pins. However, to ensure that the rest of the chip is off when the CLKOUT is active in the clock-out mode, set SPI
Reg 16, D1:D0 to “00” as shown above.
PINNAMEFUNCTION
40RXHP
41VCCRXFLReceiver Baseband Filter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
42TXBBI-
43TXBBI+
44TXBBQ+
45TXBBQ-
46VCCRXMXReceiver Downconverters Supply Voltage. Bypass with a capacitor as close as possible to the pin.
47RXTXMode Control Logic Input. See Table 1 for operating modes.
48ENABLEMode Control Logic Input. See Table 1 for operating modes.
—EP
MODE
SHUTDOWNxx00OffOffOffOffNone
STANDBY (Note 7)0101OffOffOnOnNone
CLOCK OUT00 (Note 11)01OffOffOffOnNone
Rx0111OnOff ( N ote 8) OnOnNone
Tx0110OffOnOnOnNone
Tx CALIBRATION
(Note 9)
Rx CALIBRATION
(Note 10)
Receiver Baseband AC-Coupling Highpass Corner Frequency Control Logic Input. Connect to
ground if not being used.
Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat
dissipation. Do not share with any other pin grounds and bypass capacitors’ ground.
The MAX2838 can be configured in a) single mode, for
non-MIMO or SISO applications, b) MIMO master
mode, and c) MIMO slave mode. Options b) and c) are
for MIMO applications where a coherent LO is required
for all transmitters and all receivers.
Modes of Operation
The modes of operation for the MAX2838 are clock-out,
shutdown, standby, Tx, Rx, Tx calibration, and Rx calibration. See Table 1 for a summary of the modes of
operation. The logic input pins—RXTX (pin 47) and
ENABLE (pin 48)—control the various modes.
Shutdown Mode (Complete IC Power-Down)
All circuit blocks are powered down, except the 4-wire
serial bus and its internal programmable registers.
Current drain is the minimum possible with the supply
voltages applied. If the digital supply voltage is applied
at the VCCDIG pin, the registers can be loaded.
Standby Mode
PLL, VCO, and LO generation blocks are ON, so that
Tx or Rx modes can be quickly enabled from this
mode. These and other blocks may be selectively
enabled in this mode.
Rx Mode
All Rx circuit blocks are powered on and active.
Antenna signal is applied; RF is downconverted, filtered, and buffered at Rx BB I & Q outputs.
Tx Mode
All Tx circuit blocks are powered on. The external PA is
powered on after a programmable delay.
Clock-Out Only
Only the clock-out signal is active on the CLKOUT pin.
The clock output divider is also functional. The rest of
the transceiver is powered down.
Rx Calibration
Part of the Rx and Tx circuit blocks except the LNA and
PA driver are powered on and active. The transmitter
IQ input signal is upconverted to RF and at the output
of the Tx gain control (VGA). It is fed to the receiver at
the input of the downconverter. Either or both of the two
receiver channels can be connected to the transmitter
and powered on. The I/Q lowpass filters are not present
in the transmitter signal path (they are bypassed).
Tx Calibration
All Tx circuit blocks except the PA driver and external
PA are powered on and active. The AM detector and
receiver I/Q channel buffers are also on, along with
multiplexers in receiver side to route this AM detector’s
signal to each I and Q differential lines.
Table 2. Operating Mode for MIMO Slave Configuration (Note 12)
Note 12: Set SPI Reg 16 D4:3 = “00,” Reg 24 D8 = “0,” Reg 24 D1:0 = “10” to select the MIMO slave configuration.
MODE CONTROL LOGIC INPUTSCIRCUIT BLOCK STATES
C A L I-
MODE
SHUTDOWNxx00OffOffOffOffNone
STANDBY (Note 7)0101OffOffOffOnNone
CLOCK OUT00 (Note 11)01OffOffOffOnNone
Rx0111OnOff ( N ote 8) OffOnNone
Tx0110OffOnOffOnNone
Tx CALIBRATION
(Note 9)
Rx CALIBRATION
(Note 10)
SPI REG 16,
D1:D0 (Note 4)
1110Off
1111
ENABLE
PIN
RXTX PINRx PATHTx PATHPLL, VCO
On
On
(except
LNA)
(except PA
driver)
On
(except PA
driver)
OffOn
OffOnLoop-back
CLOCK
OUT
B R A T I O N
SEC T I O N S
AM d etector
+ RX I,Q
b uffer s
O N
MAX2838
3.3GHz to 3.9GHz
Wireless Broadband RF Transceiver
The MAX2838 includes 32 programmable 16-bit registers. The most significant bit (MSB) is the read/write
selection bit. The next 5 bits are register addresses.
The 10 least significant bits (LSBs) are register data.
Register data is loaded through the 4-wire
SPI/MICROWIRE™-compatible serial interface. Data at
the DIN pin is shifted in MSB first and is framed by CS.
When CS is low, the clock is active, and input data is
shifted at the rising edge of the clock. During the read
mode, register data selected by address bits is shifted
out to the DOUT pin at the falling edges of the clock. At
CS rising edge, the 10-bit data bits are latched into the
register selected by address bits. See Figure 1.
MICROWIRE is a trademark of National Semiconductor Corp.
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.
48 TQFN-EPT4866+2
21-0141
MAX2838
3.3GHz to 3.9GHz
Wireless Broadband RF Transceiver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
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