General Description
The MAX2769 is the industry’s first global navigation
satellite system (GNSS) receiver covering GPS,
GLONASS, and Galileo navigation satellite systems on a
single chip. This single-conversion, low-IF GNSS receiver
is designed to provide high performance for a wide range
of consumer applications, including mobile handsets.
Designed on Maxim’s advanced, low-power SiGe
BiCMOS process technology, the MAX2769 offers the
highest performance and integration at a low cost.
Incorporated on the chip is the complete receiver
chain, including a dual-input LNA and mixer, followed
by the image-rejected filter, PGA, VCO, fractional-N
frequency synthesizer, crystal oscillator, and a multibit
ADC. The total cascaded noise figure of this receiver is
as low as 1.4dB.
The MAX2769 completely eliminates the need for external
IF filters by implementing on-chip monolithic filters and
requires only a few external components to form a complete low-cost GPS receiver solution.
The MAX2769 is the most flexible receiver on the
market. The integrated delta-sigma fractional-N frequency
synthesizer allows programming of the IF frequency
within a ±40Hz accuracy while operating with any reference or crystal frequencies that are available in the
host system. The integrated ADC outputs 1 or 2 quantized bits for both I and Q channels, or up to 3 quantized bits for the I channel. Output data is available
either at the CMOS logic or at the limited differential
logic levels.
The MAX2769 is packaged in a compact 5mm x 5mm,
28-pin thin QFN package with an exposed paddle. The
part is also available in die form. Contact the factory for
further information.
Applications
Location-Enabled Mobile Handsets
PNDs (Personal Navigation Devices)
PMPs (Personal Media Players)
PDAs (Personal Digital Assistants)
In-Vehicle Navigation Systems
Telematics (Asset Tracking, Inventory
Management)
Recreational/Marine Navigation/Avionics
Software GPS
Laptops and Ultra-Mobile PCs
Digital Still Cameras and Camcorders
Features
o GPS/GLONASS/Galileo Receivers
o No External IF SAW or Discrete Filters Required
o Programmable IF Frequency
o Fractional-N Synthesizer with Integrated VCO
Supports Wide Range of Reference Frequencies
o Dual-Input Uncommitted LNA for Separate
Passive and Active Antenna Inputs
o 1.4dB Cascade Noise Figure
o Integrated Crystal Oscillator
o Integrated Active Antenna Sensor
o 10mA Supply Current in Low-Power Mode
o 2.7V to 3.3V Supply Voltage
o Small, 28-Pin, RoHS-Compliant, Thin QFN Lead-
Free Package (5mm x 5mm)
MAX2769
Universal GPS Receiver
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration/Block Diagram
Ordering Information
19-0791; Rev 2; 6/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed paddle.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX2769ETI+ -40°C to +85°C 28 Thin QFN-EP*
MAX2769E/W -40°C to +85°C Dice (In Wafer Form)
N.C.
VCCIF
IDLE
LNA2
PGM
LNA1
TSENS
I0
20
21
22
+
1
ADC
LNA2
LNA1
ANTFLAG
MAX2769
FILTER
2
LNAOUT
23
24
25
26
27
28
Q0
VCCADC
19 17 16
3 5
ANTBIAS
Q1I1CLKOUT
18
ADC
PLL
900
4 6
MIXIN
VCCRF
VCO
3-WIRE
INTERFACE
LD
XTAL
15
14
VCCD
VCCCP
13
CPOUT
12
VCCVCO
11
CS
10
9
SCLK
8
SDATA
7
SHDN
MAX2769
Universal GPS Receiver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. Typical
values are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.2V
Other Pins to GND ..................-0.3V to +(Operating V
CC
+ 0.3V)
Maximum RF Input Power ..............................................+15dBm
Continuous Power Dissipation (T
A
= +70°C)
28-Pin Thin QFN (derates 27mW/°C above +70°C)...2500mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (TQFN only, soldering, 10s) ..............+300°C
Soldering Temperature (reflow) .......................................+260°C
Idle Mode is a trademark of Maxim Integrated Products, Inc.
CAUTION! ESD SENSITIVE DEVICE
Supply Voltage 2.7 2.85 3.3 V
Supply Current
Voltage Drop at ANTBIAS from
VCCRF
S hor t- C i r cui t P r otecti on C ur r ent
at AN TBIAS
Acti ve Antenna D etecti on C ur r ent To asser t l og i c- hi g h at AN TFLAG 1.1 mA
DIGITAL INPUT AND OUTPUT
Digital Input Logic-High Measure at the SHDN pin 1.5 V
Digital Input Logic-Low Measure at the SHDN pin 0.4 V
PARAMETER CONDITIONS MIN TYP MAX UNITS
Default mode, LNA1 is active (Note 2) 15 18 22
Default mode, LNA2 is active (Note 2) 12 15 19
Idle Mode™, IDLE = low 1.5
Shutdown mode, SHDN = low 20 μA
Sourcing 20mA at ANTBIAS 0.2 V
AN TBIAS i s shor ted to g r ound 57 mA
mA
MAX2769
Universal GPS Receiver
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.) (Note 1)
CASCADED RF PERFORMANCE
RF Frequency L1 band
Out-of-Band 3rd-Order Input
Intercept Point
In-Band Mixer Input Referred
1dB Compression Point
Mixer Input Return Loss 10 dB
Image Rejection 25 dB
Spurs at LNA1 Input
Maximum Voltage Gain Measured from the mixer to the baseband analog output 91 96 103 dB
Variable Gain Range 55 59 dB
FILTER RESPONSE
Passband Center Frequency 4 MHz
Lowpass 3dB Bandwidth FBW = 11 9 MHz
Stopband Attenuation
LNA
LNA1 INPUT
Power Gain 19 dB
Noise Figure 0.83 dB
Input IP3 (Note 5) -1.1 dBm
Output Return Loss 10 dB
Intput Return Loss 8dB
LNA2 INPUT
Power Gain 13 dB
Noise Figure 1.14 dB
Input IP3 (Note 5) 1 dBm
Output Return Loss 19 dB
Input Return Loss 11 dB
PARAMETER CONDITIONS MIN TYP MAX UNITS
1575.42
LNA1 input active, default mode (Note 3) 1.4
LNA2 input active, default mode (Note 3) 2.7Noise Figure
Measured at the mixer input 10.3
Measured at the mixer input (Note 4) -7 dBm
Measured at the mixer input -85 dBm
LO leakage -101
Reference harmonics leakage -103
FBW = 00 2.5
FBW = 10 4.2Passband 3dB Bandwidth
FBW = 01 8
3r d- or der fi l ter , band wi d th = 2.5M Hz, measur ed at 4M H z offset 30
5th- or der fi l ter , band wi d th = 2.5M Hz, measur ed at 4M H z offset 41 49.5
MHz
dB
dBm
MHz
dB
MAX2769
Universal GPS Receiver
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.) (Note 1)
Note 1: MAX2769 is production tested at TA = +25°C. All min/max specifications are guaranteed by design and characterization
from -40°C to +85°C, unless otherwise noted. Default register settings are not production tested or guaranteed. User must
program the registers upon power-up.
Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an
active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically
disabled and LNA2 becomes active. PLL is in an integer-N mode with f
COMP
= f
TCXO
/ 16 = 1.023MHz and ICP= 0.5mA. The
complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz. Output
data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.
Note 3: The LNA output connects to the mixer input without a SAW filter between them.
Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz
at -60dBm/tone. Passive pole at the mixer output is programmed to be 13MHz.
Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the
GPS center frequency of 1575.42MHz at -60dBm per tone.
FREQUENCY SYNTHESIZER
LO Frequency Range 0.4V < V
LO Tuning Gain 57 MHz/V
Reference Input Frequency 8 44 MHz
Main Divider Ratio 36 32,767 —
Reference Divider Ratio 1 1023 —
Charge-Pump Current
TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER
Reference Input Level Sine wave 0.4 V
Clock Output Multiply/Divide
Range
ADC
ADC Differential Nonlinearity AGC enabled, 3-bit output ±0.1 LSB
ADC Integral Nonlinearity AGC enabled, 3-bit output ±0.1 LSB
PARAMETER CONDITIONS MIN TYP MAX UNITS
< 2.4V 1550 1610 MHz
TUNE
ICP = 0 0.5
ICP = 1 1
÷4 x2 —
mA
P-P
MAX2769
Universal GPS Receiver
_______________________________________________________________________________________
5
Typical Operating Characteristics
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.)
CASCADED RECEIVER GAIN (dB)
CASCADED RECEIVER GAIN
vs. PGA GAIN CODE
120
100
80
60
40
065
TA = -40°C
TA = +25°C
TA = +85°C
PGA GAIN CODE (DECIMAL FORMAT)
MAX2769 toc01
60555045403530252015105
CASCADED GAIN AND NOISE FIGURE
vs. TEMPERATURE
2.0
1.5
AGC GAIN
1.0
NOISE FIGURE (dB)
0.5
0
-40 85
TEMPERATURE (°C)
LNA1 GAIN AND NOISE FIGURE
vs. LNA1 BIAS DIGITAL CODE
1.6
1.4
1.2
1.0
0.8
0.6
NOISE FIGURE (dB)
0.4
0.2
0
115
GAIN
NOISE FIGURE
LNA BIAS DIGITAL CODE (DECIMAL)
MAX2769 toc04
14132 3 4 6 7 8 9 10 115 12
25
20
15
10
5
0
LNA1 GAIN (dB)
NOISE FIGURE
MAX2769 toc02
603510-15
120
115
110
105
100
95
90
40
30
20
10
0
-10
CASCADED GAIN
-20
LNA1 |S21| AND |S12| (dB)
-30
-40
-50
0.50 2.50
LNA1 GAIN AND NOISE FIGURE
vs. TEMPERATURE
1.4
LNA BIAS = 1000
1.2
1.0
0.8
0.6
NOISE FIGURE (dB)
0.4
NOISE FIGURE
0.2
0
-40 85
TEMPERATURE (°C)
GAIN
LNA1 |S21| AND |S12|
vs. FREQUENCY
|S21|
|S12|
FREQUENCY (GHz)
MAX2769 toc05
19.6
19.4
19.2
19.0
18.8
18.6
LNA1 GAIN (dB)
18.4
18.2
18.0
603510-15
17.8
2.252.001.50 1.751.00 1.250.75
MAX2769 toc03
MAX2769
Universal GPS Receiver
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.)
-10.0
-12.5
LNA1 INPUT 1dB COMPRESSION POINT (dBm)
-15.0
LNA1 INPUT 1dB COMPRESSION POINT
vs. LNA1 BIAS DIGITAL CODE
5.0
2.5
0
-2.5
-5.0
-7.5
115
LNA BIAS DIGITAL CODE (DECIMAL)
14132 3 4 6 7 8 9 10 115 12
30
20
MAX2769 toc06
10
0
-10
-20
LNA2 |S21| AND |S12| (dB)
-30
-40
-50
0.50 2.50
LNA2 |S21| AND |S12|
vs. FREQUENCY
FREQUENCY (GHz)
|S21|
|S12|
LNA2 GAIN AND NOISE FIGURE
vs. TEMPERATURE
2.0
LNA BIAS = 10
1.8
MAX2769 toc07
1.6
1.4
1.2
1.0
0.8
NOISE FIGURE (dB)
2.252.000.75 1.00 1.25 1.50 1.75
NOISE FIGURE
0.6
0.4
0.2
0
-40 85
GAIN
TEMPERATURE (°C)
MAX2769 toc08
603510-15
13.6
13.4
13.2
13.0
12.8
12.6
12.4
12.2
LNA2 GAIN (dB)
LNA INPUT RETURN LOSS
vs. FREQUENCY
0
LNA1
-10
-20
-30
LNA INPUT RETURN LOSS (dB)
-40
-50
1.0 2.2
LNA2
FREQUENCY (GHz)
LNA OUTPUT RETURN LOSS
vs. FREQUENCY
0
MAX2769 toc09
-5
LNA1
-10
-15
LNA OUTPUT RETURN LOSS (dB)
2.12.01.91.81.71.61.51.41.31.21.1
-20
LNA2
1.0 2.2
FREQUENCY (GHz)
MAX2769 toc10
MIXER INPUT REFERRED IP1dB (dB)
2.12.01.91.81.71.61.51.41.31.21.1
MIXER INPUT REFERRED IP1dB
vs. OFFSET FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
PGA GAIN = 32dB
PGA GAIN = 51dB
PRF = -100dBm
0 300
OFFSET FREQUENCY (MHz)
MAX2769 toc11
25020015010050
MAX2769
Universal GPS Receiver
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.)
5TH-ORDER POLYPHASE FILTER MAGNITUDE
RESPONSE vs. BASEBAND FREQUENCY
MAX2769 toc15
BASEBAND FREQUENCY (MHz)
MAGNITUDE (dB)
98765432
-60
-50
-40
-30
-20
-10
0
10
-70
110
MIXER INPUT REFERRED GAIN
vs. PGA GAIN CODE
MAX2769 toc16
PGA GAIN CODE (DECIMAL FORMAT)
MIXER INPUT REFERRED GAIN (dB)
60555045403530252015105
40
60
80
100
20
065
TA = +25°C
TA = -40°C
TA = +85°C
JAMMER POWER (dBm)
1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY
0
-5
-10
-15
-20
800 950
MAX2769 toc12a
925900875850825
JAMMER FREQUENCY (MHz)
3RD-ORDER POLYPHASE FILTER MAGNITUDE
RESPONSE vs. BASEBAND FREQUENCY
10
MAX2769 toc12b
205020001950190018501800 2100
MIXER INPUT REFERRED NOISE FIGURE
vs. PGA GAIN
16
14
12
10
8
MIXER INPUT REFERRED NOISE FIGURE (dB)
6
565
PGA GAIN (dB)
5545352515
MAX2769 toc13
0
-10
-20
-30
MAGNITUDE (dB)
-40
-50
-60
110
BASEBAND FREQUENCY (MHz)
MAX2769 toc14
98765432
MAX2769
Universal GPS Receiver
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
CC
= 2.85V and TA= +25°C, unless otherwise noted.)
2-BIT ADC TRANSFER CURVE
3.5
3.0
2.5
2.0
1.5
1.0
CODE (DECIMAL VALUE)
0.5
0
-0.5
-1.0 1.0
DIFFERENTIAL VOLTAGE (V)
0.80.6-0.8 -0.6 -0.4 0 0.2-0.2 0.4
MAX2769 toc17a
3-BIT ADC TRANSFER CURVE
7
6
5
4
3
2
CODE (DECIMAL VALUE)
1
0
-1.0 1.0
DIFFERENTIAL VOLTAGE (V)
MAX2769 toc17b
0.80.6-0.8 -0.6 -0.4 0 0.2-0.2 0.4
DIGITAL OUTPUT CMOS LOGIC
20ns/div
CRYSTAL OSCILLATOR FREQUENCY
vs. DIGITAL TUNING CODE
16,368.10
16,368.05
16,368.00
16,367.95
16,367.90
CRYSTAL OSCILLATOR FREQUENCY (kHz)
16,367.85
032
DIGITAL TUNING CODE (DECIMAL)
TA = -40°C
TA = +85°C
TA = +25°C
MAX2760 toc18
282420161284
CLK
2V/div
SIGN DATA
2V/div
MAGNITUDE
DATA
2V/div
MAX2769 toc20
DIGITAL OUTPUT DIFFERENTIAL LOGIC
40ns/div
MAX2760 toc19
CRYSTAL OSCILLATOR FREQUENCY
VARIATION vs. TEMPERATURE
10
8
6
4
2
0
-2
-4
-6
-8
-10
CRYSTAL OSCILLATOR FREQUENCY VARIATION (ppm)
-40 85
TEMPERATURE (°C)
603510-15
CLK
1V/div
SIGN+
1V/div
SIGN1V/div
MAX2769 toc21
MAX2769
Universal GPS Receiver
_______________________________________________________________________________________ 9
Typical Application Circuit
Table 1. Component List
BASEBAND
OUTPUT
BASEBAND
CLOCK
REFERENCE
INPUT
C11
PLL
C10
VCO
3-WIRE
INTERFACE
LD
XTAL
15
7
SHDN
14
13
12
11
10
9
8
VCCD
VCCCP
CPOUT
VCCVCO
CS
SCLK
SDATA
SERIAL
INPUT
C6
C5
C1
C4
C2
TOP VIEW
I0
20
21
N.C.
VCCIF
IDLE
LNA2
PGM
LNA1
N.C.
22
+
1
ANTFLAG
ADC
LNA2
LNA1
2
LNAOUT
23
24
25
26
27
28
C8
C0
C7
Q0
VCCADC
19 17 16
18
ADC
MAX2769
FILTER
900
3 5
4 6
VCCRF
ANTBIAS
C3 C13
Q1I1CLKOUT
MIXIN
ACTIVE
ANTENNA BIAS
C12
DESIGNATION QUANTITY DESCRIPTION
C0 1 0.47nF AC-coupling capacitor
C1 1 27pF PLL loop filter capacitor
C2 1 0.47nF PLL loop filter capacitor
C3–C8 6 0.1μF supply voltage bypass capacitor
C10, C11 2 10nF AC-coupling capacitor
C12 1 0.47nF AC-coupling capacitor
C13 1 0.1nF supply voltage bypass capacitor
R1 1 20kΩ PLL loop filter resistor
MAX2769
Universal GPS Receiver
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 ANTFLAG
2 LNAOUT LNA Output. The LNA output is internally matched to 50Ω.
3 ANTBIAS Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.
4 VCCRF
5 MIXIN Mixer Input. The mixer input is internally matched to 50Ω.
6 LD Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked.
7 SHDN Operation Control Logic Input. A logic-low shuts off the entire device.
8 SDATA Data Digital Input of 3-Wire Serial Interface
9 SCLK
10 CS
11 VCCVCO VCO Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
12 CPOUT
13 VCCCP
14 VCCD Digital Circuitry Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
15 XTAL XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used.
16 CLKOUT Reference Clock Output
17 Q1
18 Q0
19 VCCADC ADC Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
20 I0
21 I1
22 N.C. No Connection. Leave this pin unconnected.
23 VCCIF IF Section Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
24 IDLE
25 LNA2 LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50Ω.
26 PGM
27 LNA1
28 N.C. No connection. Leave this pin open.
—EP
Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the
ANTBIAS pin.
RF Section Supply Voltage. Bypass to GND with 100nF and 100pF capacitors in parallel as close as
possible to the pin.
Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising
edge of the SCLK.
Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high
when the loading action is completed.
Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and
C (see the Typical Application Circuit).
PLL Charge-Pump Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the
pin.
Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.
I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.
Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active,
and all other blocks are off.
Logic Input. Connect to GND to use the serial interface. A logic-high allows programming to 8 hardcoded by device states connecting SDATA, CS, and SCLK to supply or ground according to Table 3.
LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50Ω (see the
Typical Application Circuit).
Exposed Paddle. Ultra-low-inductance connection to ground. Place several vias to the PCB ground
plane.
MAX2769
Universal GPS Receiver
______________________________________________________________________________________ 11
Detailed Description
Integrated Active Antenna Sensor
The MAX2769 includes a low-dropout switch to bias an
external active antenna. To activate the antenna switch
output, set ANTEN in the Configuration 1 register to
logic 1. This closes the switch that connects the antenna bias pin to VCCRF to achieve a low 200mV dropout
for a 20mA load current. A logic-low in ANTEN disables
the antenna bias. The active antenna circuit also features short-circuit protection to prevent the output from
being shorted to ground.
Low-Noise Amplifier (LNA)
The MAX2769 integrates two low-noise amplifiers. LNA1
is typically used with a passive antenna. This LNA
requires an AC-coupling capacitor. In the default mode,
the bias current is set to 4mA, the typical noise figure and
IIP3 are approximately 0.8dB and -1.1dBm, respectively.
LNA1 current can be programmed through ILNA in
Configuration 1 register. In the low-current mode of 1mA,
the typical noise figure is degraded to 1.2dB and the IIP3
is lowered to -15dBm. LNA2 is typically used with an
active antenna. The LNA2 is internally matched to 50Ω
and requires a DC-blocking capacitor. Bits LNAMODE in
the Configuration 1 register control the modes of the two
LNAs. See Table 6 for the LNA mode settings and current
selections.
Mixer
The MAX2769 includes a quadrature mixer to output lowIF or zero IF I and Q signals. The quadrature mixer is
internally matched to 50Ω and requires a low-side LO
injection. The output of the LNA and the input of the mixer
are brought off-chip to facilitate the use of a SAW filter.
Programmable Gain Amplifier (PGA)
The MAX2769 integrates a baseband programmable
gain amplifier that provides 59dB of gain control range.
The PGA gain can be programmed through the serial
interface by setting bits GAININ in the Configuration 3
register. Set bits 12 and 11 (AGCMODE) in the
Configuration 2 register to 10 to control the gain of the
PGA directly from the 3-wire interface.
Automatic Gain Control (AGC)
The MAX2769 provides a control loop that automatically
programs PGA gain to provide the ADC with an input
power that optimally fills the converter and establishes
a desired magnitude bit density at its output. An algorithm operates by counting the number of magnitude
bits over 512 ADC clock cycles and comparing the
magnitude bit count to the reference value provided
through a control word (GAINREF). The desired magnitude bit density is expressed as a value of GAINREF in
a decimal format divided by the counter length of 512.
For example, to achieve the magnitude bit density of
33%, which is optimal for a 2-bit converter, program the
GAINREF to 170, so that 170 / 512 = 33%.
Baseband Filter
The baseband filter of the receiver can be programmed to
be a lowpass filter or a complex bandpass filter. The lowpass filter can be configured as a 3rd-order Butterworth
filter for a reduced group delay by setting bit F3OR5 in the
Configuration 1 register to be 1 or a 5th-order Butterworth
filter for a steeper out-of-band rejection by setting the
same bit to be 0. The two-sided 3dB corner bandwidth
can be selected to be 2.5MHz, 4.2MHz, 8MHz, or 18MHz
(only to be used as a lowpass filter) by programming bits
FBW in the Configuration 1 register. When the complex
filter is enabled by changing bit FCENX in the
Configuration 1 register to 1, the lowpass filter becomes a
bandpass filter and the center frequency can be
programmed by bits FCEN in the Configuration 1 register.
Synthesizer
The MAX2769 integrates a 20-bit sigma-delta fractional-N
synthesizer allowing the device to tune to a required
VCO frequency with an accuracy of approximately
±40Hz. The synthesizer includes a 10-bit reference
divider with a divisor range programmable from 1 to
1023, a 15-bit integer portion main divider with a divisor
range programmable from 36 to 32767, and also a 20-bit
fractional portion main divider. The reference divider is
programmable by bits RDIV in the PLL integer division
ratio register (see Table 10), and can accommodate reference frequencies from 8MHz to 44MHz. The reference
divider needs to be set so the comparison frequency
falls between 0.05MHz to 32MHz.
Figure 1. Schematic of the Crystal Oscillator in the MAX2679
EV Kit
BASEBAND
CLKOUT
16
MAX2769
XTAL
15
CLOCK
10nF
23pF
MAX2769
Universal GPS Receiver
12 ______________________________________________________________________________________
The PLL loop filter is the only external block of the synthesizer. A typical PLL filter is a classic C-R-C network
at the charge-pump output. The charge-pump output
sink and source current is 0.5mA by default, and the
LO tuning gain is 57MHz/V. As an example, see the
Typical Application Circuit
for the recommended loop-
filter component values for f
COMP
= 1.023MHz and loop
bandwidth = 50kHz.
The desired integer and fractional divider ratios can be
calculated by dividing the LO frequency (fLO) by
f
COMP
. f
COMP
can be calculated by dividing the TCXO
frequency (f
TCXO
) by the reference division ratio
(RDIV). For example, let the TCXO frequency be
20MHz, RDIV be 1, and the nominal LO frequency be
1575.42MHz. The following method can be used when
calculating divider ratios supporting various reference
and comparison frequencies:
Integer Divider = 78(d) = 000 000 0100 1110
(binary)
Fractional Divider = 0.771 x 220= 808452
(decimal) = 1100 0101 0110 0000 0100
In the fractional mode, the synthesizer should not be
operated with integer division ratios greater than 251.
Crystal Oscillator
The MAX2769 includes an on-chip crystal oscillator. A
parallel mode crystal is required when the crystal oscillator is being used. It is recommended that an AC-coupling capacitor be used in series with the crystal and
the XTAL pin to optimize the desired load capacitance
and to center the crystal-oscillator frequency. Take the
parasitic loss of interconnect traces on the PCB into
account when optimizing the load capacitance. For
example, the MAX2769 EV kit utilizes a 16.368MHz
crystal that is designed for a 12pF load capacitance. A
series capacitor of 23pF is used to center the crystal
oscillator frequency, see Figure 1. In addition, the 5-bit
serial-interface word, XTALCAP in the PLL Configuration
register, can be used to vary the crystal-oscillator
frequency electronically. The range of the electronic
adjustment depends on how much the chosen crystal
frequency can be pulled by the varying capacitor. The
frequency of the crystal oscillator used on the MAX2769
EV kit has a range of approximately 200Hz.
The MAX2769 provides a reference clock output. The
frequency of the clock can be adjusted to crystal-oscillator frequency, a quarter of the oscillator frequency, a
half of the oscillator frequency, or twice the oscillator
frequency, by programming bits REFDIV in the PLL
Configuration register.
ADC
The MAX2769 features an on-chip ADC to digitize the
downconverted GPS signal. The maximum sampling
rate of the ADC is approximately 50Msps. The sampled
output is provided in a 2-bit format (1-bit magnitude
and 1-bit sign) by default and also can be configured
as a 1-bit, 1.5-bit, or 2-bit in both I and Q channels, or
1-bit, 1.5-bit, 2-bit, 2.5-bit, or 3-bit in the I channel only.
The ADC supports the digital outputs in three different
formats: the unsigned binary, the sign and magnitude,
or the two’s complement format by setting bits FORMAT
in Configuration register 2. MSB bits are output at I1 or
Q1 pins and LSB bits are output at I0 or Q0 pins, for I or
Q channel, respectively. In the case of 2.5-bit or 3-bit,
output data format is selected in the I channel only, the
ComparisonFrequency
RDIV
MHz
MHz
TCXO
=
ƒ
==
20
1
20
LLO Frequency Divider
MHz
LO
COMP
.
=
ƒ
ƒ
=
1575 42
20
MMHz
= 78 771.
Table 2. Output Data Format
INTEGER
VALUE
7 0 01 01 011 011 1 10 11 101 111 0 01 01 101 011
5 0 01 01 001 010 1 10 11 100 110 0 01 01 100 010
3 0 01 00 001 001 1 10 10 100 101 0 01 00 100 001
1 0 00 00 000 000 1 11 10 011 110 0 00 00 011 000
-1 1 00 10 000 100 0 11 01 011 011 1 00 11 011 111
-3 1 10 10 101 101 0 01 01 001 010 1 11 11 111 110
-5 1 10 11 101 110 0 01 00 001 001 1 11 10 111 101
-7 1 10 11 111 111 0 01 00 000 000 1 11 10 110 100
SIGN/MAGNITUDE UNSIGNED BINARY TWO’S COMPLEMENT BINARY
1b 1.5b 2b 2.5b 3b 1b 1.5b 2b 2.5b 3b 1b 1.5b 2b 2.5b 3b
MAX2769
Universal GPS Receiver
______________________________________________________________________________________ 13
MSB is output at I1, the second bit is at I0, and the LSB
is at Q1.
Figure 2 illustrates the ADC quantization levels for 2and 3-bit cases and also describes the sign/magnitude
data mapping. The variable T = 1 designates the location of the magnitude threshold for the 2-bit case.
Fractional Clock Divider
A 12-bit fractional clock divider is located in the clock
path prior to the ADC and can be used to generate the
ADC clock that is a fraction of the reference input
clock. In a fractional divider mode, the instantaneous
division ratio alternates between integer division ratios
to achieve the required fraction. For example, if the
fractional output clock is 4.5 times slower than the input
clock, an average division ratio of 4.5 is achieved
through an equal series of alternating divide-by-4 and
divide-by-5 periods. The fractional division ratio is
given by:
f
OUT
/ fIN= L
COUNT
/ (4096 - M
COUNT
+ L
COUNT
)
where L
COUNT
and M
COUNT
are the 12-bit counter val-
ues programmed through the serial interface.
DSP Interface
GPS data is output from the ADC as the four logic signals (bit0, bit1, bit2, and bit3) that represent sign/magnitude, unsigned binary, or two’s complement binary data
in the I (bit0and bit1) and Q (bit2and bit3) channels. The
resolution of the ADC can be set up to 3 bits per channel. For example, the 2-bit I and Q data in sign/magnitude format is mapped as follows: bit0= I
SIGN
, bit1=
I
MAG
, bit2= Q
SIGN
, and bit3= Q
MAG
. The data can be
serialized in 16-bit segments of bit0, followed by bit1,
bit2, and bit3. The number of bits to be serialized is controlled by the bits STRMBITS in the Configuration 3 regis-
Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases
011
01
010
001
00
000
-6-7
-3-4-5
-1-2
101
110
11
111
10
100
12
345
T = 1
67
MAX2769
Universal GPS Receiver
14 ______________________________________________________________________________________
ter. This selects between bit0; bit0and bit1; bit0and bit2;
and bit0, bit1, bit2, and bit3cases. If only bit0is serialized, the data stream consists of bit0data only. If a serialization of bit0and bit1(or bit2) is selected, the stream
data pattern consists of 16 bits of bit0data followed by
16 bits of bit1(or bit2) data, which, in turn, is followed by
16 bits of bit0data, and so on. In this case, the serial
clock must be at least twice as fast as the ADC clock. If a
4-bit serialization of bit
0
, bit1, bit2, and bit3is chosen, the
serial clock must be at least four times faster than the
ADC clock.
The ADC data is loaded in parallel into four holding registers that correspond to four ADC outputs. Holding registers are 16 bits long and are clocked by the ADC clock.
At the end of the 16-bit ADC cycle, the data is transferred into four shift registers and shifted serially to the
output during the next 16-bit ADC cycle. Shift registers
are clocked by a serial clock that must be chosen fast
enough so that all data is shifted out before the next set
of data is loaded from the ADC. An all-zero pattern follows the data after all valid ADC data are streamed to the
output. A DATASYNC signal is used to signal the beginning of each valid 16-bit data slice. In addition, there is a
TIME_SYNC signal that is output every 128 to 16,384
cycles of the ADC clock.
Figure 3. DSP Interface Top-Level Connectivity and Control Signals
I
ADC
Q
CONTROL
SIGNALS
FROM 3-WIRE
INTERFACE
STRM_EN
DATA_OUT
BIT 0
BIT 1
CLK_SER
BIT 2
DATA_SYNC
BIT 3
TIME_SYNC
STRM_EN
STRM_START
STRM_STOP
STRM_COUNT<2:0>
DIEID<1:0>
STRM_BITS<1:0>
FRM_COUNT<27:0>
STAMP_EN
DAT_SYNCEN
TIME_SYNCEN
STRM_RST
CLK_ADC CLK_SER
STRM_EN
OUTPUT
DRIVER
PIN 21
PIN 20
PIN 17
PIN 18
L_CNT<11:0>
M_CNT<11:0>
CLK_IN CLK_OUT
REF/XTAL
PIN 15
THROUGH
/2
/4
x2
REFDIV<1:0>
ADCCLK_SEL
SERCLK_SEL
FRCLK_SEL
MAX2769
Universal GPS Receiver
______________________________________________________________________________________ 15
Preconfigured Device States
When a serial interface is not available, the device can
be used in preconfigured states that don’t require programming through the serial interface. Connecting the
PGM pin to logic-high and SCLK, SDATA, and CS pins
to either logic-high or low sets the device in one of the
preconfigured states according to Table 3.
Serial Interface, Address,
and Bit Assignments
A serial interface is used to program the MAX2769 for
configuring the different operating modes.
The serial interface is controlled by three signals: SCLK
(serial clock), CS (chip select), and SDATA (serial data).
The control of the PLL, AGC, test, and block selection is
performed through the serial-interface bus from the baseband controller. A 32-bit word, with the MSB (D27) being
sent first, is clocked into a serial shift register when the
chip-select signal is asserted low. The timing of the interface signals is shown in Figure 4 and Table 4 along with
typical values for setup and hold time requirements.
Table 3. Preconfigured Device States
*
If the IF center frequency is programmed to 1.023MHz, the filter passband extends from 0.1MHz to 2.6MHz.
Figure 4. 3-Wire Timing Diagram
DEVICE ELECTRICAL CHARACTERISTICS 3-WIRE CONTROL PINS
(MHz)
DEVICE STATE
0 16.368 16 1536 I 1 Differential 4.092 5th 0 0 0
1 16.368 16 1536 I 1 Differential 4.092 3rd 0 0 1
2 16.368 16 1536 I 2 CMOS 4.092 5th 0 1 0
3 32.736 32 1536 I 2 CMOS 4.092 5th 0 1 1
4 19.2 96 7857 I 2 CMOS 4.092 5th 1 0 0
5 18.414 18 1539 I 2 CMOS 1.023* 5th 1 0 1
6 13 65 7857 I 2 CMOS 4.092 5th 1 1 0
7 16.368 16 1536 I 1 CMOS 4.092 5th 1 1 1
REFERENCE
FREQUENCY
DIVISION
REFERENCE
RATIO
MAIN
DIVISION
RATIO
ONLY
I AND Q OR I
NUMBER OF
I Q BITS
LOGIC
LEVEL
I AND Q
(MHz)
IF CENTER
FREQUENCY
ORDER
IF FILTER
SCLK
DATA
CS
CS
t
CSH
t
CSS
SCLK
t
DH t
DATA
LSB
ADDR
MSB
CH
ADDR
LSB
SDATA
DATA
MSB
t
DS
t
CSW
t
CL
MAX2769
Universal GPS Receiver
16 ______________________________________________________________________________________
Table 4. Serial-Interface Timing Requirements
Table 5. Default Register Setting
SYMBOL PARAMETER TYP VALUE UNITS
t
CSS
t
DS
t
DH
t
CH
t
CL
t
CSH
t
CSW
Falling edge of CS to rising edge of the first SCLK time. 10 ns
Data to serial-clock setup time. 10 ns
Data to clock hold time. 10 ns
Serial clock pulse-width high. 25 ns
Clock pulse-width low. 25 ns
Last SCLK rising edge to rising edge of CS.10ns
CS high pulse width. 1 clock
REGISTER
NAME
CONF1 0000 Configures RX and IF sections, bias settings for individual blocks. A2919A3
CONF2 0001 Configures AGC and output sections. 0550288
CONF3 0010 Configures support and test functions for IF filter and AGC. EAFF1DC
PLLCONF 0011 PLL, VCO, and CLK settings. 9EC0008
DIV 0100 PLL main and reference division ratios, other controls. 0C00080
FDIV 0101 PLL fractional division ratio, other controls. 8000070
STRM 0110 DSP interface number of frames to stream. 8000000
CLK 0111 Fractional clock-divider values. 10061B2
TEST1 1000 Reserved for test mode. 1E0F401
TEST2 1001 Reserved for test mode. 14C0402
ADDRESS
(A3:A0)
DATA
DEFAULT
(D27:D0)
MAX2769
Universal GPS Receiver
______________________________________________________________________________________ 17
Table 6. Configuration 1 (Address: 0000)
Detailed Register Definitions
DATA BIT LOCATION
CHIPEN 27 1
IDLE 26 0 Idle enable. Set 1 to put the chip in the idle mode and 0 for operating mode.
ILNA1 25:22 1000 LNA1 current programming.
ILNA2 21:20 10 LNA2 current programming.
ILO 19:18 10 LO buffer current programming.
IMIX 17:16 01 Mixer current programming.
MIXPOLE 15 0
LNAMODE 14:13 00
MIXEN 12 1 Mixer enable. Set 1 to enable the mixer and 0 to shut down the mixer.
ANTEN 11 1 Antenna b i as enab l e. S et 1 to enab l e the antenna b i as and 0 to shut d ow n the antenna b i as.
FCEN 10:5 001101 IF center frequency programming. Default for f
FBW 4:3 00
F3OR5 2 0
FCENX 1 1
FGAIN 0 1 IF filter gain setting. Set 0 to reduce the filter gain by 6dB.
DEFAULT
VALUE
DESCRIPTION
Chip enable. Set 1 to enable the device and 0 to disable the entire device except the
serial bus.
Mixer pole selection. Set 1 to program the passive filter pole at mixer output at 36MHz, or
set 0 to program the pole at 13MHz.
LN A m od e sel ecti on, D 14:D 13 = 00: LN A sel ecti on g ated b y the antenna b i as ci r cui t, 01:
LN A2 i s acti ve; 10: LN A1 i s acti ve; 11: b oth LN A1 and LN A2 a r e off.
= 4MHz, BW = 2.5MHz.
CENTER
IF filter center bandwidth selection. D4:D3 = 00: 2.5MHz; 10: 4.2MHz; 01: 8MHz;
11: 18MHz (only used as a lowpass filter).
Filter order selection. Set 0 to select the 5th-order Butterworth filter. Set 1 to select the
3rd-order Butterworth filter.
Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 0 to select
lowpass filter mode.
MAX2769
Universal GPS Receiver
18 ______________________________________________________________________________________
Table 7. Configuration 2 (Address: 0001)
DATA BIT LOCATION
IQEN 27 0
GAINREF 26:15 170d
— 14:13 00 Reserved.
AGCMODE 12:11 00
DEFAULT
VALUE
I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I
channel only.
AGC gain reference value expressed by the number of MSB counts (magnitude bit
density).
AGC mode control. Set D12:D11 = 00: independent I and Q; 01: I and Q gains are
locked to each other; 10: gain is set directly from the serial interface by GAININ;
11: disallowed state.
DESCRIPTION
FORMAT 10:9 01
BITS 8:6 010
DRVCFG 5:4 00
LOEN 3 1 LO buffer enable. Set 1 to enable LO buffer or 0 to disable the buffer.
RESERVED 2 0 Reserved.
DIEID 1:0 00 Identifies a version of the IC.
Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X:
two’s complement binary.
Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: 1.5 bits; 010: 2 bits;
011: 2.5 bits, 100: 3 bits.
O utp ut d r i ve r confi g ur ati on. S et D 5:D 4 = 00: C M O S l og i c, 01: l i m i ted d i ffer enti al l og i c; 1X:
analog outputs.
MAX2769
Universal GPS Receiver
______________________________________________________________________________________ 19
Table 8. Configuration 3 (Address: 0010)
DATA BIT LOCATION
GAININ 27:22 111010 PGA gain value programming from the serial interface in step s of dB per LSB.
FSLOWEN 21 1 Low value of the ADC ful l-scale enable. Set 1 to enable or 0 to disable.
HILOADEN 20 0 Set 1 to enable the output driver to drive high loads.
ADCEN 19 1 ADC enable. Set 1 to enable ADC or 0 to di sable.
DRVEN 18 1 Output driver enable. Set 1 to enable the dri ver or 0 to disable.
FOFSTEN 17 1
FILTEN 16 1 IF filter enab le. Set 1 to enable the filter or 0 to disable.
FHIPEN 15 1
— 14 1 Reserved.
PGAIEN 13 1 I-channel PGA enable. Set 1 to enable PGA in the I channel or 0 to disable.
PGAQEN 12 0 Q-channel PGA enable. Set 1 to enab le PGA in the Q channel or 0 to disable .
STRMEN 11 0
STRMSTART 10 0
STRMSTOP 9 0
STRMCOUNT 8:6 111 Sets the length of the data counter from 128 (000) to 16,394 (111) bits per frame.
STRMBITS 5:4 01
STAMPEN 3 1
TIMESYNCEN 2 1
DATSYNCEN 1 0
STRMRST 0 0
DEFAULT
VALUE
Filter DC offset cancellation circuitry enable. Set 1 to enable the circuitry or 0 to
Highpass coupling enable. Set 1 to enable the highpass coupling between the filter
and PGA, or 0 to disable the coupling.
DSP interface for serial streaming of data enable. This bit configures the IC such
that the DSP interface is inserted in the s ignal path. Set 1 to enable the interface
or 0 to disable the interface.
The pos it ive edge of th is command enables data streaming to the output. It also
enables c lock, data sync, and frame sync outputs.
The pos it ive edge of th is command disables data streaming to the output. It also
disables clock, data sync, and frame sync outputs.
Number of bits streamed. D5:D4 = 00: I MSB; 01: I MSB, I LSB; 10: I MSB, Q MSB;
11: I MSB, I LS B, Q MSB, Q LSB.
The signal enables the insertion of the frame number at the beginning of each
frame. If disabled, only the ADC data is streamed to the output.
This signal enables the output of the time sync pulse s at all time s when streaming
is enabled by the STRMEN command. Otherwise, the time sync pulses are
available only when data streaming is active at the output, for example, in the time
intervals bound by the STRMSTART and STRMSTOP commands.
This control signal enables the sync pulses at the DATASYNC output. Each pulse
is co incident with the beginn ing of the 16-bit data word that corresponds to a
given output bit.
This command resets all the counters irrespective of the timing within the
stream cycle.
DESCRIPTION
MAX2769
Universal GPS Receiver
20 ______________________________________________________________________________________
Table 9. PLL Configuration (Address: 0011)
DATA BIT LOCATION
VCOEN 27 1 VCO enable. Set 1 to enable the VCO or 0 to disable VCO.
IVCO 26 0
— 25 0 Reserved.
REFOUTEN 24 1 C l ock b uffer enab l e. S et 1 to enab l e the cl ock b uffer or 0 to d i sab l e the cl ock b uffer .
—231Reser ved .
REFDIV 22:21 11
IXTAL 20:19 01
XTALCAP 18:14 10000 Digital XTAL load cap programming.
LDMUX 13:10 0000 LD pin output selection. Set D13:D10 = 0000: PLL lock-detect signal.
ICP 9 0 Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA.
PFDEN 8 0 Set 0 for normal operation or 1 to disable the PLL phase frequency detector.
— 7 0 Reserved.
CPTEST 6:4 000
INT_PLL 3 1 P LL m od e contr ol . S et 1 to enab l e the i nteg er - N P LL or 0 to enab l e the fr acti onal - N P LL.
PWRSAV 2 0 PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable.
— 1 0 Reserved.
— 0 0 Reserved.
DEFAULT
VALUE
VCO current-mode selection. Set 1 to program the VCO in the low-current mode or
0 to program in the normal mode.
C l ock outp ut d i vi d er r ati o. S et D 22:D 21 = 00: cl ock fr eq uency = X TAL fr eq uency x 2; 01:
cl ock fr eq uency = X TAL fr eq uency / 4; 10: cl ock fr eq uency = X TAL fr eq uency / 2; 11:
cl ock fr eq uency = X TAL.
Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: oscillator normal
current; 01: buffer normal current; 10: oscillator medium current; 11: oscillator high
current.
Charge-pump test. Set D6:D4 = 000: normal operation; X10: pump up; X01 = pump
down; 100 = high impedance; 111: both up and down on.
DESCRIPTION
MAX2769
Universal GPS Receiver
______________________________________________________________________________________ 21
Table 10. PLL Integer Division Ratio (Address 0100)
Table 11. PLL Division Ratio (Address 0101)
Table 12. DSP Interface (Address 0110)
Table 13. Clock Fractional Division Ratio (Address 0111)
Table 14. Test Mode 1 (Address 1000)
Table 15. Test Mode 2 (Address 1001)
DATA BIT LOCATION
NDIV 27:13 1536d PLL integer division ratio.
RDIV 12:3 16d PLL reference division ratio.
— 2:0 000 Reserved.
DEFAULT
VALUE
DESCRIPTION
DATA BIT LOCATION
FDIV 27:8 80000h PLL fractional divider ratio.
— 7:0 01110000 Reserved.
DEFAULT
VALUE
DATA BIT LOCATION
FRAMECOUNT 27:0 8000000h
DEFAULT
VALUE
This word defines the frame number at which to start streaming. This mode is active
when streaming mode is enabled by a command STRMEN, but a command
STRMSTART is not received. In this case, the frame counter is reset upon the assertion
of STRMEN, and it begins its count. When the frame number reaches the value defined
by FRMCOUNT, the streaming begins.
DATA BIT LOCATION
L_CNT 27:16 256d Sets the value for the L counter.
M_CNT 15:4 1563d Sets the value for the M counter.
FCLKIN 3 0
ADCCLK 2 0
SERCLK 1 1
MODE 0 0 DSP interface mode selection.
DEFAULT
VALUE
Fractional clock divider. Set 1 to select the ADC clock to come from the fractional
clock divider, or 0 to bypass the ADC clock from the fractional clock divider.
ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come
from the reference divider/multiplier.
Serializer clock selection. Set 0 to select the serializer clock output to come from the
reference divider/multiplier.
DESCRIPTION
DESCRIPTION
DESCRIPTION
DATA BIT LOCATION
— 27:0 1E0F401 Reserved.
DEFAULT
VALUE
DESCRIPTION
DATA BIT LOCATION
— 27:0 14C0402 Reserved.
DEFAULT
VALUE
DESCRIPTION
MAX2769
Universal GPS Receiver
22 ______________________________________________________________________________________
Applications Information
The LNA and mixer inputs require careful consideration
in matching to 50Ω lines. Proper supply bypassing,
grounding, and layout are required for reliable performance from any RF circuit.
Low-Power Operation
The MAX2769 can be operated in a low-power mode
by programming the bias current values of individual
blocks to their minimum recommended values. The list
below summarizes the recommended changes to serial
interface registers from their default states to achieve a
low-power operation:
ILNA1 = 0010
ILNA2 = 00
ILO = 00
IMIX = 00
F3OR5 = 1
ANTEN = 0
BITS = 000
IVCO = 0
REFOUTEN = 0
PLLPWRSAV = 1
In this mode, LNA, mixer, LO, and VCO currents are
reduced to their minimum recommended values. The IF
filter is configured as a 3rd-order filter. The output data
is in a 1-bit CMOS mode in the I channel only. PLL is in
an integer-N power-saving mode, which can be used if
the main division ratio is divisible by 32. The antenna
bias circuitry is disabled.
In the low-power mode, the total current consumption
reduces to 10mA, while the total cascaded noise figure
increases to 3.8dB.
Operation in Wideband Galileo and
GLONASS Applications
The use of the wideband receiver options is recommended for Galileo and GLONASS applications. The
frequency synthesizer is used to tune LO to a desired
frequency, which, in turn, determines the choice of the
IF center frequency. Either a fractional-N or an integerN mode of the frequency synthesizer can be used
depending on the choice of the reference frequency.
For Galileo reception, set the IF filter bandwidth to
4.2MHz (FBW = 10) and adjust the IF center frequency
through a control word FCEN to the middle of the downconverted signal band. Alternatively, use wideband settings of 8MHz and 18MHz when the receiver is in a
zero-IF mode.
For GLONASS as well as GPS P-code reception, a
zero-IF receiver configuration is used in which the IF filter is used in a lowpass filter mode (FCENX = 1) with a
two-sided bandwidth of 18MHz.
It is recommended that an active antenna LNA be used
in wide-bandwidth applications such that the PGA is
operated at lower gain levels for a maximum bandwidth. If a PGA gain is programmed directly from a serial interface, GAININ values between 32 and 38 are
recommended. Set the filter pole at the mixer output to
36MHz through MIXPOLE = 1.
Layout Issues
The MAX2769 EV kit can be used as a starting point for
layout. For best performance, take into consideration
grounding and routing of RF, baseband, and powersupply PCB proper line. Make connections from vias to
the ground plane as short as possible. On the highimpedance ports, keep traces short to minimize shunt
capacitance. EV kit Gerber files can be requested at
www.maxim-ic.com.
Power-Supply Layout
To minimize coupling between different sections of the
IC, a star power-supply routing configuration with a large
decoupling capacitor at a central VCCnode is recommended. The VCCtraces branch out from this node, each
going to a separate VCCnode in the circuit. Place a
bypass capacitor as close as possible to each supply
pin This arrangement provides local decoupling at each
VCCpin. Use at least one via per bypass capacitor for a
low-inductance ground connection. Do not share the
capacitor ground vias with any other branch.
Chip Information
PROCESS: SiGe BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP T2855+3
21-0140
WAFER WDICE8 —
MAX2769
Universal GPS Receiver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
23
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 6/07 Initial release —
1 1/09 Added MAX2769E/W, updated specifications 1, 4, 12, 16, 22
2 6/10
REVISION
DATE
DESCRIPTION
Removed references to temperature sensor function, changed four
specifications for SPF, and added soldering temperature
PAGES
CHANGED
1–4, 8, 9, 10,
14–18, 22
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