MAXIM MAX2306, MAX2308, MAX2309 User Manual

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX2306/MAX2308/MAX2309 are IF receivers
designed for dual-band, dual-mode, and single-mode
N-CDMA and W-CDMA cellular phone systems. The
signal path consists of a variable-gain amplifier (VGA)
and I/Q demodulator. The devices feature guaranteed
+2.7V operation, a gain control range of over 110dB,
and high input IP3 (-31dBm at 35dB gain, 3.4dBm at

-35dB gain).
Unlike similar devices, the MAX2306 family of receivers

includes dual oscillators and synthesizers to form a
self-contained IF subsystem. The synthesizer’s refer­ence and RF dividers are fully programmable through a
3-wire serial bus, enabling dual-band system architec­tures using any common reference and IF frequency.
The differential baseband outputs have enough band­width to suit both N-CDMA and W-CDMA systems, and
offer saturated output levels of 2.7Vp-p at a low +2.75V
supply voltage. Including the low-noise voltage-con­trolled oscillator (VCO) and synthesizer, the MAX2306
draws only 26mA from a +2.75V supply in CDMA (dif­ferential IF) mode.

The MAX2306/MAX2308/MAX2309 are available in 28­pin Thin QFN and QFN packages.

Applications

Single/Dual/Triple-Mode CDMA Handsets
Globalstar Dual-Mode Handsets
Wireless Data Links
W-CDMA Handsets
Wireless Local Loop (WLL)

Features

♦ Complete IF Subsystem Includes VCO and

Synthesizer

♦ Supports Dual-Band, Triple-Mode Operation
♦ VGA with >110dB Gain Control
♦ Quadrature Demodulator
♦ High Output Level (2.7V)
♦ Programmable Charge-Pump Current
♦ Supports Any IF Frequency Between 40MHz and

300MHz

♦ 3-Wire Programmable Interface
♦ Low Supply Voltage (+2.7V)

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

________________________________________________________________ Maxim Integrated Products 1

19-2014; Rev 3; 8/04

EVALUATION KIT AVAILABLE

Pin Configurations appear at end of data sheet.
Block Diagram appears at end of data sheet.

Ordering Information

Selector Guide

*Exposed paddle

PART

TEMP RANGE

PIN-PACKAGE

MAX2306EGI

28 QFN-EP*

MAX2306ETI

28 TQFN-EP*

MAX2308EGI

28 QFN-EP*

MAX2308ETI

28 TQFN-EP*

MAX2309EGI

28 QFN-EP*

MAX2309ETI

28 TQFN-EP*

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

PART MODE DESCRIPTION INPUT RANGE

AMPS,

MAX2306

MAX2308

MAX2309

Cellular CDMA,

PCS CDMA

AMPS,

Cellular CDMA,

PCS CDMA

External AMPS,
Cellular CDMA,

PCS CDMA

Dual Band, Triple Mode with Two

IF VCOs

Dual Band, Triple Mode with Common

IF VCO

Dual Band, Triple Mode (Drives External

AMPS Discriminator)

40MHz to 300MHz

70MHz to 300MHz

70MHz to 300MHz

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +2.7V to +3.6V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10kΩ, TA= -40°C to +85°C,

registers set to default power-up settings. Typical values are at V

CC

= +2.75V and TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto GND...........................................................-0.3V to +6.0V

SHDN to GND.............................................-0.3V to (V

CC

+ 0.3V)

STBY, BUFEN, MODE, EN, DATA,

CLK, DIVSEL ...........................................-0.3V to (V

CC

+ 0.3V)

VGC to GND...............-0.3V, the lesser of +4.2V or (V

CC

+ 0.3V)

AC Signals TANKH ±, TANKL ±,

REF, FM ±, CDMA ± .................................................1.0V peak

Digital Input Current SHDN, MODE, DIVSEL,

BUFEN, DATA, CLK, EN, STBY .....................................±10mA

Continuous Power Dissipation (T

A

= +70°C)

28-Pin QFN (derate 28.5mW/°C above T

A

= +70°C)...........2W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +160°C

Lead Temperature (soldering, 10s).................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TA = +25°C

CDMA mode

TA = +25°C

FM_IQ mode

TA = +25°C

FM_I mode

TA = +25°C

TA = +25°C

Supply Current
(Note 1)

I

CC

Addition for LO out (BUFEN = low) 3.5

mA

Shutdown Current I

CC

SHDN = low 1.5 10 µA

Register Shutdown Current I

CC

4 5.8 mA
Logic High 2.0 V
Logic Low 0.5 V
Logic High Input Current I

IH

2µA

Logic Low Input Current I

IL

2µA

VGC Control Input Current 0.5V < V

VGC

< 2.3V -5 5 µA

VGC Control Input Current
During Shutdown

SHDN = low 1 µA

Lock Indicator High (locked) 47kΩ load 2.0 V
Lock Indicator Low (unlocked) 47kΩ load 0.5 V
DC Offset Voltage I+ to I- and Q+ to Q-, PLL locked -20

mV

Common-Mode Output Voltage VCC = +2.75V

V

STANDBY (VCO_H)

STANDBY (VCO_L)

TA = -40°C to +85°C 41.5

TA = -40°C to +85°C 40.6

TA = -40°C to +85°C 39.5

T

= -40°C to +85°C 20.7

A

T

= -40°C to +85°C 20.3

A

25.9 37.5

25.4 36.7

24.7 35.7

12.3 18.8

11.4 18.4

±1.5 +20

VCC - 1.4

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(MAX2306/MAX2308/MAX2309 EV kit, VCC= +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16,
f

IN

= 183.7MHz, f

REF

= 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for

+35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T

A

= +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Frequency f

IN

(Note 2) 40 300

MHz

Reference Frequency f

REF

39

MHz

Frequency Reference Signal
Level

V

REF

0.2

Vp-p

SIGNAL PATH, CDMA MODE

Gain = -35dB, (Note 3) 3.4

Input 3rd-Order Intercept IIP3

Gain = +35dB, T

A

= -40°C to +85°C

(Notes 4, 5)

-38

dBm

Gain = -35dB -9

Input 1dB Compression P

1dB

Gain = +35dB -44

dBm

Gain = -35dB

Input 0.25dB Desensitization (Note 6)

Gain = +35dB -49

dBm

Minimum Voltage Gain A

V

V

VGC

= 0.5V (Note 5) -56 -51 dB

Maximum Voltage Gain A

V

V

VGC

= 2.3V (Note 5) 57 61 dB

Gain = -35dB

DSB Noise Figure NF

Gain = +35dB

dBm

SIGNAL PATH, FM_IQ MODE

Gain = -35dB, (Note 7)

Input 3rd-Order Intercept IIP3

Gain = +35dB, T

A

= -40°C to +85°C

(Notes 5, 8)

-32

dBm

Gain = -35dB -20

Input 1dB Compression P

1dB

Gain = +35dB -44

dBm

Minimum Voltage Gain A

V

V

VGC

= 0.5V (Note 5)

-52 dB

Maximum Voltage Gain A

V

V

VGC

= 2.3V (Note 5) 56

dB

SIGNAL PATH, CDMA AND FM_IQ MODE

Gain Variation Over Temperature

Normalized to +25°C

dB

Baseband 0.5dB Bandwidth 4.2

MHz

Quadrature Suppression TA = -40°C to +85°C (Note 5) 28 40 dB
LO to Baseband Leakage 1

mVp-p

Saturated Output Level V

SAT

Differential 2.7

Vp-p

PHASE-LOCKED LOOP

(Note 2) 80 300

VCO Tune Range

(Note 2)

600

MHz

LO_OUT Output Power P

LO

RL = 50Ω, BUFEN = low

dBm

VCO Minimum Divide Ratio

256
VCO Maximum Divide Ratio
REF Minimum Divide Ratio

2

F

VCO_L

F

VCO_H

M1, M2
M1, M2 16383

R1, R2

-31.0

-40.2

135

-14.8

62.9

6.36

-6.5

-56.7

59.5

±2.5

-13.7

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(MAX2306/MAX2308/MAX2309 EV kit, VCC= +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16,
f

IN

= 183.7MHz, f

REF

= 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for

+35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T

A

= +25°C, unless otherwise noted.)

Note 1: FM_IQ and FM_I modes are not available on MAX2309.
Note 2: Recommended operating frequency range. Contact factory for operating frequency outside this range.
Note 3: f

1

= 183.7MHz, f2= 183.71MHz, Pf1= P

f2

= -15dBm.

Note 4: f

1

= 183.7MHz, f2= 183.71MHz, Pf1= P

f2

= -50dBm.

Note 5: Guaranteed by design.
Note 6: Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at

1.25MHz below the LO frequency is applied at the specified level.

Note 7: f

1

= 183.7MHz, f2= 183.71MHz, Pf1= P

f2

= -23dBm.

Note 8: f

1

= 183.7MHz, f2= 183.71MHz, Pf1= P

f2

= -55dBm.

PARAMETER

CONDITIONS

UNITS

REF Maximum Divide Ratio
Minimum Phase Detector

Comparison Frequency

(Note 5) 20 kHz

Maximum Phase Detector
Comparison Frequency

(Note 5)

kHz

1kHz offset, TA = -40°C to +85°C

12.5kHz offset, TA = -40°C to +85°C
30kHz offset, TA = -40°C to +85°C
120kHz offset, TA = -40°C to +85°C

Phase Noise

900kHz offset, T

A

= -40°C to +85°C

dBc/Hz

TURBO LOCK

Acquisition, CPX = XX, TC =1
Locked, CPX = 00

150

Locked, CPX = 01

210

Locked, CPX = 10

300

Charge-Pump Source/Sink
Current

Locked, CPX = 11

425

µA

Charge-Pump Source/Sink
Matching

Locked, all values of CPX,

0.5V < V

CP

< VCC - 0.5V

0.2 10 %

SYMBOL

R1, R2 2047

MIN TYP MAX

1500

-79.6

-94.6

-105

-115.3

-125

1480 2100 2650

105
150
210
300

190
265
380
530

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________ 5

20.00

25.00

22.50

30.00

27.50

32.50

35.00

2.5 3.5 4.03.0 4.5 5.0 5.5

RECEIVE SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX2306/8/9 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

TA = +85°C

TA = +25°C

TA = -40°C

0

0.004

0.002

0.008

0.006

0.012

0.010

0.014

2.0 3.0 3.52.5 4.0 4.5 5.0 5.5

RECEIVE SHUTDOWN CURRENT vs.

SUPPLY VOLTAGE

MAX2306/8/9 toc02

SUPPLY VOLTAGE (V)

SHUTDOWN CURRENT (mA)

TA = -40°C

TA = +25°C

TA = +85°C

-80

-60

-40

-20

0

20

40

60

80

0.5 1.0 1.5 2.0 2.5 3.0

GAIN vs. V

GC

MAX2306/8/9 toc03

VGC (V)

GAIN (dB)

TA = +25°C

TA = -40°C

TA = +85°C

15

25
20

35
30

40

45

55
50

60

0 100 200 300 400 500

GAIN vs. INPUT FREQUENCY

MAX2306/8/9 toc04

FREQUENCY (MHz)

GAIN (dB)

VGC = 2.5V

56.0

57.0

56.5

57.5

59.0

59.5

58.5

58.0

60.0

0 468102 1214161820

GAIN vs. BASEBAND FREQUENCY

MAX2306/8/9 toc05

FREQUENCY (MHz)

RELATIVE GAIN (dB)

-60

-40

-50

-20

-30

0

-10

10

-60 -20 0-40 20406080

THIRD-ORDER INPUT
INTERCEPT vs. GAIN

MAX2306/8/9 toc06

GAIN (dB)

IIP3 (dBm)

TA = -40°C

TA = +85°C

TA = +25°C

0

60

20

10

30

40

50

70

-40 -20 -10 0-30 10 20 5040 6030 70

NOISE FIGURE vs. GAIN

MAX2306/8/9 toc07

GAIN (dB)

NF (dB)

6.0

6.4

6.2

6.8

6.6

7.2

7.0

7.4

-40 0 20-20 406080100

NOISE FIGURE vs. TEMPERATURE

MAX2306/8/9 toc08

TEMPERATURE (°C)

NF (dB)

GAIN = 50dB

LOCK

VCO
VOLTAGE

VCO VOLTAGE vs. TIME

MAX2306/8/9 toc09

500µs/div

SHDN

LOCK TIME

1.83ms

1V/div

Typical Operating Characteristics

(MAX2306/MAX2308/MAX2309 EV kits, VCC= +2.75V, registers set to default power-up states, fIN= 183.7MHz, f

REF

= 19.2MHz,
synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load
= 10kΩ, all power levels referred to 50Ω, T

A

= +25°C, unless otherwise noted.)

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

6 _______________________________________________________________________________________

500

1100

900
700

1300

1500

1700

1900

2100

2300

2500

0 200100 300 400 500 600

IF PORT PARALLEL RESISTANCE

vs. FREQUENCY

MAX2306/8/9 toc10

FREQUENCY (MHz)

EQUIVALENT PARELLEL RESISTANCE (Ω)

MEASURED DIFFERENTIALLY

CDMA PORT

FM PORT

MAX2306/8/9 toc12

-400

-380

-340

-360

-280

-260

-300

-320

-240

EQUIVALENT PARELLEL RESISTANCE (Ω)

80 240 320160 400 480 560

FREQUENCY (MHz)

TANK PORT PARALLEL RESISTANCE

vs. FREQUENCY

TANKH

TANKL

MEASURED DIFFERENTIALLY

0

0.2

0.1

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

MAX2306/8/9 toc13

FREQUENCY (MHz)

EQUIVALENT PARELLEL CAPACITANCE (pF)

80 160 240 320 400 400 560

TANK PORT PARALLEL CAPACITANCE

vs. FREQUENCY

TANK

TANKL

MEASURED DIFFERENTIALLY

Typical Operating Characteristics (continued)

(MAX2306/MAX2308/MAX2309 EV kits, VCC= +2.75V, registers set to default power-up states, fIN= 183.7MHz, f

REF

= 19.2MHz,
synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load
= 10kΩ, all power levels referred to 50Ω, T

A

= +25°C, unless otherwise noted.)

LOOUT PORT

S11 vs. FREQUENCY

MAX2310 toc14

START: 10MHz
STOP: 600MHz

0.5

0.7

0.6

0.9

0.8

1.1

1.0

1.2

0 200 300100 400 500 600

MAX2306/8/9 toc11

FREQUENCY (MHz)

EQUIVALENT PARELLEL CAPACITANCE (pF)

IF PORT PARALLEL CAPACITANCE

vs. FREQUENCY

CDMA PORT

FM PORT

MEASURED DIFFERENTIALLY

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________ 7

Pin Description

PIN

MAX2306

NAME FUNCTION

1, 28 — —

TANKL-

Differential Tank Input for Low-Frequency Oscillator

— 1, 4 — N.C. No Connection. Must be left open-circuit.

2, 3 2, 3 1, 2

TANKH-

Differential Tank Input for High-Frequency Oscillator

—— 3BUFEN LO Buffer Amplifier—active low

4 — — MODE Mode Select. High selects CDMA mode; low selects FM mode.

— — 4 LOOUT

Internal VCO Output. Depending on setting of BD bit, LOOUT is
either the VCO frequency (twice the IF frequency) or one-half the
VCO frequency (equal to the IF frequency).

555VCC+2.7V to +5.5V Supply
6 6 6 GND Ground
7 7 7 REF Reference Frequency Input

888SHDN

Shutdown Input—active low. Low powers down entire device,
including registers and serial interface.

9, 10 9, 10 9, 10

IOUT+,

IOUT-

Differential In-Phase Baseband Output, or FM signal output if FM_I
mode is selected.

11 11 11 LOCK

Lock Output—open-collector pin. Logic high indicates phase-locked
condition.

12, 13 12, 13 12, 13

QOUT-,
QOUT+

Differential Quadrature-Phase Baseband Output. Disabled if FM_I
mode is selected.

14 14 14 CLK Clock input of the 3-wire serial bus
15 15 15 EN Enable Input. When low, input shift register is enabled.
16 16 16 DATA Data input of the 3-wire serial bus.
17 17 17 V

CC

+2.7V to +5.5V Supply

18 18 18 VGC VGA Gain Control Input. Control voltage range is 0.5V to 2.3V.

19, 20 19, 20 19, 20

CDMA-,
CDMA+

Differential CDMA Input. Active in CDMA mode.
21 21 — FM+ Differential Positive Input. Active in FM mode.
22 22 — FM-

Differential Negative Input for FM signal. Bypass to GND for

single-ended operation.

——22STBY

Standby Input—active low. Low powers down VGA and demodulator

while keeping VCO, PLL, and serial bus on.

23, 24 23, 24 23, 24 BYP Bypass Node. Must be capacitively decoupled (bypassed) to pin 17.

MAX2308 MAX2309

TANKL+,

TANKH+,

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

8 _______________________________________________________________________________________

_______________Detailed Description

MAX2306

The MAX2306 is intended for dual-band (PCS and cel­lular) and dual-mode code division multiple access
(CDMA) and FM applications (Figure 1). The device
includes an IF variable-gain amplifier, quadrature
demodulator, dual VCOs, and dual-frequency synthe­sizers (Functional Diagram). Dual VCOs are provided
for applications using different IF frequencies for each
mode or band of operation. The analog FM output sig­nal can be configured for conversion to the I channel,
or it may be converted in quadrature to both the I and
Q channels. The MAX2306’s operation modes are
described in Table 1. These modes are set by pro­gramming the control register and setting logic levels
on control pins. If MODE is left floating, the internal reg­ister controls the operation. If driven high or low, mode
will override certain register bits, as shown in Table 1.

MAX2308

The MAX2308 supports dual-band, triple mode with
common IF VCO. As with the MAX2306, the FM mode
can be configured for conversion to the I port or quad­rature conversion to both the I and Q ports (Figure 2).
The MAX2308’s operational modes are described in
Table 2. These modes are set by programming the con­trol register.

MAX2309

The MAX2309 quadrature demodulators are simplified
versions of the MAX2306 that can be used in single­mode CDMA or triple mode using an external FM dis­criminator (Figure 3). The MAX2309 VCO is optimized
for the 67MHz to 300MHz IF frequency range.

The MAX2309 includes a buffered output for the VCO.
The buffered VCO output can be used to support sys-

tems implementing traditional limiting IF stages for FM
demodulation in dual-mode phones as well as for the
transmit LO in TDD systems. This buffered output can
be configured for the VCO frequency (twice the IF fre­quency) or one-half the VCO frequency (IF frequency).
The BUFEN pin enables this feature. A standby mode,
in which only the VCO and synthesizer are operational,
can be selected through the serial interface or the
STBY pin. The MAX2309’s operational modes are
described in Table 3. These modes are set by pro­gramming the control register and/or setting logic levels
on control pins. If the control pins (STBY, BUFEN,
DIVSEL) are left floating, the internal register controls
the operational mode. If driven high or low, the control
pins will override certain register bits, as shown in
Table 3.

Applications Information

Variable-Gain Amplifier and Demodulator

The MAX2306 family provides a VGA with exceptional
gain range. The MAX2306/MAX2308 support multimode
applications with dual differential inputs, selectable with
the IN_SEL (IS) control bit. On the MAX2306, this func­tion can be controlled with the MODE pin, which over­rides the IS control bit. The VGA’s gain is controlled
over a 110dB range with the VGC pin. The output of the
VGA drives the RF ports of a quadrature demodulator.
The MAX2306/MAX2308 provide two types of FM
demodulation, controlled by the FM_TYPE (FT) control
bit. When FM_TYPE is “1,” the signal is passed through
both the I and Q signal paths for subsequent lowpass
filtering and A/D conversion at baseband. If FM_TYPE
is “0,” the FM signal is passed through the I mixer only.

Pin Description (continued)

PIN

MAX2306

NAME FUNCTION

25 25 25 BYP

Bypass Node. Must be capacitively decoupled (bypassed)

to ground.
26 26 26 CP_OUT Charge-Pump Output
27 27 27 GND Ground

— 28 21 N.C. No Connection
— — 28 DIVSEL High selects M1/R1; low selects M2/R2.

Exposed Paddle EP Ground

MAX2308 MAX2309

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________ 9

Voltage-Controlled Oscillator,

Buffers, and Quadrature Generation

The LO signal for downconversion is provided by a
voltage-controlled oscillator (VCO) consisting of an on­chip differential oscillator, and an off-chip high-Q reso­nant network. Figure 4 shows a simplified schematic of
the VCO oscillator. Multiband operation is supported by
the MAX2306 with dual VCOs. VCO_H and VCO_L are
selectable with the MODE pin or the VCO_SEL (VS)
control bit. They oscillate at twice the desired LO fre­quency. For applications requiring an external LO, the
VCOs can be bypassed with the VCO_BYP (VB) control
bit.

The MAX2309 buffers the output of the VCO and pro­vides this signal at the LOOUT pin. This signal is
enabled by the BUFEN (BE) control bit or by the
BUFEN control pin. The frequency of this signal is
selected by the BUF_DIV (BD) control bit, and can be
either the VCO frequency or half the VCO frequency.

Quadrature downconversion is realized by providing in­phase (I) and quadrature-phase (Q) components of the
LO signal to the LO ports of the demodulator described
above. The quadrature LO signals are generated by
dividing the VCO output frequency using two latches.

Figure 1. MAX2306 Typical Operating Circuit

MAX2306

BYP
BYP
FM-

FM+

CDMA+

CDMA

FM

3-WIRE

DAC

0.1µF

0.01µF

0.068µF

47pF

2pF

33pF

0.01µF

10kΩ

2.4kΩ

10kΩ

33pF

47pF

33nH

0.01µF

680Ω

CDMA-

LOCK

VGC

V

CC

V

CC

V

CC

V

CC

DATA

CLK

QOUT+

QOUT-

EN

TANKH-

IOUT-

IOUT+

REF

GND

V

CC

MODE

TANKH+

TANKL-

GND

CP_OUT

BYP

SHDN

TANKL+

0.01µF
V

CC

47pF

10kΩ

47kΩ

Q

10kΩ

2pF

33pF

10kΩ

10kΩ

33pF

I

33nH

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

10 ______________________________________________________________________________________

M

S

B

Table 1. MAX2306 Control Register States

MODE

SHDN

PINS

XL

Shutdown pin completely
powers down the chip

SHUTDOWN

ACTION

RESULT

OPERATIONAL

MODE

TEST_MODE

X

CP POL

TEST_EN

XX

TURBOCHARGE

DIVSEL

X

VCO_BYP

VCO_SEL

XX X

BUF_DIV

BUFEN

XX

FM_TYPE

IN_SEL

X

STBY

SHDN

ML
S CONTROL REGISTER S
BB

XX X

X XXH X

0 in shutdown register bit leaves
serial port active

SHUTDOWN X XX X XX X 0X X

X 0XH X

0 in standby register bit turns off
VGA and modulator only

STANDBY XX 10

0HH

Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to high

CDMA X X XX X 1X 1

0FH

Floating mode pin returns control
to register

CDMA 1 1 XX 1 1X 1

0LH

Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to low

FM_IQ X X XX X 10 1

0FH

Floating mode pin returns control
to register

FM_IQ XX 0 10 1

0LH

Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to low

FM_I X X XX X 11 1

0F

H

L

Floating pins return control to
register

FM_I XX 0 11 1

Note: H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low.

The appropriate latch outputs provide I and Q signals
at the desired LO frequency.

Synthesizer

The VCO’s output frequency is controlled by an internal
phase-locked-loop (PLL) dual-modulus synthesizer. The
loop filter is off-chip to simplify loop design for emerg­ing applications. The tunable resonant network is also
off-chip for maximum Q and for system design flexibili­ty. The VCO output frequency is divided down to the
desired comparison frequency with the M counter. The
M counter consists of a 4-bit A swallow counter and a
10-bit P counter. A reference signal is provided from an
external source and is divided down to the comparison
frequency with the R counter. The two divided signals
are compared with a three-state digital phase-frequen-

cy detector. The phase-detector output drives a
charge-pump as well as lock-detect logic and tur­bocharge control logic. The charge-pump output
(CP_OUT) pin is processed by the loop filter and drives
the tunable resonant network, altering the VCO frequen­cy and closing the loop.

Multimode applications are supported by two indepen­dent programmable registers each for the M counter
(M1, M2), the R counter (R1, R2), and the charge-pump
output current magnitude (CP1, CP2). The DIVSEL (DS)
bit selects which set of registers is used. It can be over­ridden by the MAX2306’s MODE pin or the MAX2309’s
DIVSEL pin. Programming these registers is discussed
in the 3-Wire Interface and Registers section.

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________ 11

M

S
B

Table 2. MAX2308 Control Register States

Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter

STBY

OPERATIONAL

MODE

11 10X X0FM_I FM I operation 0H

10 10X X0FM_IQ FM IQ quadrature operation 0H

1X 11X X0CDMA CDMA operation 0H

0 1X X0STANDBY

0 in standby pin turns off VGA and
modulator only

0H

XX LXX XXX XSHUTDOWN

0 in shutdown register bit leaves seri­al port active

XH X XX

XX X

ML
S CONTROL REGISTER S
BB

SHDN

X

IN_SEL

FM_TYPE

X X

BUFEN

BUF_DIV

XX X

VCO_SEL

VCO_BYP

SHUTDOWN

Shutdown pin completely shuts down
chip

DIVSEL

XL X X

TURBOCHARGE

TEST_EN

X

CP_POL

P

I

N

SHDN

TEST_MODE

ACTION
RESULT

When the part initially powers up or changes state, the
synthesizer acquisition time can be reduced by using
the Turbo feature, enabled by the TURBOCHARGE
(TC) control bit. Turbo functionality provides a larger
charge-pump current during acquisition mode. Once
the VCO frequency is acquired, the charge-pump out­put current magnitude automatically returns to the pre­programmed state to maintain loop stability and
minimize spurs in the VCO output signal.

The lock detect output indicates when the PLL is
locked with a logic high.

3-Wire Interface and Registers

The MAX2306 family incorporates a 3-wire interface for
synthesizer programming and device configuration
(Figure 5). The 3-wire interface consists of clock, data,
and enable signals. It controls the VCO dividers (M1
and M2), reference frequency dividers (R1 and R2),
and a 13-bit control register. The control register is
used to set up the operational modes (Table 4). The
input shift is 17 data bits long and requires a total of 18
clock bits (Figure 6). A single clock pulse is required
before enable drops low to initialize the data bus.

Whenever the M or R divide register value is pro­grammed and downloaded, the control register must
also be subsequently updated. This prevents turbolock
from going active when not desired.

The SHDN control bit is notable because it differs from
the SHDN pin. When the SHDN control bit is low, the
registers and serial interface are left active, retaining
the values stored in the latches, while the rest of the
device is shut off. In contrast, the SHDN pin, when low,
shuts down everything, including the registers and seri­al interface. See Functional Diagram.

Registers

Figure 7 shows the programming logic. The 17-bit shift
register is programmed by clocking in data at the rising
edge of CLK. Before the shift register is able to accept
data, it must be initialized by driving it with at least one
full clock cycle at the CLK input with EN high (see
Figure 6). Pulling enable low will allow data to be
clocked into the shift register; pulling enable high loads
the register addressed by A0, A1, and A2, respectively
(Figure 7). Table 5 lists the power-on default values of
all registers. Table 6 lists the charge-pump current,
depending on CP0 and CP1.

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

12 ______________________________________________________________________________________

MAX2308

BYP

BYP

FM-

FM+

CDMA+

3-WIRE

DAC

0.01µF

0.01µF

47pF

2pF

33pF

0.01µF

10kΩ

10kΩ

33pF

47pF

33nH

0.01µF

680Ω

CDMA-

LOCK

VGC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

DATA

CLK

Q_OUT+

Q_OUT-

I_OUT-

I_OUT+

REF

GND

V

CC

TANKH-

GND

CP_OUT

BYP

TANKH+

47pF

10kΩ

47kΩ

10kΩ

0.068µF

2.4kΩ

FM

0.01µF

Q

CDMA

EN

SHDN

Figure 2. MAX2308 Typical Operating Circuit

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________ 13

Table 3. MAX2309 Control Register States

Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter.

1

1

1

1

0 1

X 1

X 0

X X

SHDN

STBY

1/

0

X0

LO BUFFER

ENABLE

If pin is floated, then
BUFEN register bit
controls buffer

H F

XX0

LO BUFFER

ENABLE

BUFEN pin controls the
LO buffer and overrides
the bit

H/

L

H

X

1/

0

0

DIVIDER

SELECT

If DIVSEL pin is floated,
then register bit selects
divider

HH F

XX0

DIVIDER

SELECT

DIVSEL pin overrides
DIVSEL register bit

HH

H/

L

X0STANDBY

0 in standby register bit
turns off VGA and mod­ulator only

H

H/

L

H

X0STANDBY

0 in standby pin turns
off VGA and modulator
only

LH

XX XXX XXX XXSHUTDOWN

0 in shutdown register
bit leaves serial bus
active

XH X XX

XX X

IN_SEL

FM_TYPE

X

BUFEN

OPERATIONAL

MODE

ACTION

RESULT

BUF_DIV

X X

VCO_SEL

VCO_BYP

XX X

DIVSEL

TURBOCHARGE

X

TES_TEN

SHUTDOWN

Shutdown pin com­pletely powers down
the chip

CP_POL

XL X X

TEST_MODE

PINS

STBY

X

BUFEN

SHDN

DIVSEL

ML
S CONTROL REGISTER S
BB

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

14 ______________________________________________________________________________________

MAX2309

BYP

BYP

STBY

CDMA+

3-WIRE

DAC

0.01µF

0.01µF

0.068µF

47pF

2pF

33pF

0.01µF

10kΩ

2.4kΩ

10kΩ

33pF

47pF

33nH

0.01µF

680Ω

CDMA-

LOCK

VGC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

DATA

CLK

QOUT+

QOUT-

EN

BUFEN

IOUT-

IOUT+

REF

GND

V

CC

LOOUT

TANKH-

TANKH+

GND

CP_OUT

BYP

SHDN

DIVSEL

47pF

FM

455kHz

10kΩ10kΩ

LIMITER

DISCRIMINATOR

47kΩ

Q

I

CDMA

Figure 3. MAX2309 Typical Operating Circuit

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________ 15

V

CC

800µA

D1

R1

C

F

C

F

R

B

R

L

TANK_+

TANK_-

R

L

R

E

R

E

R

B

Figure 4. Voltage-Controlled Oscillators

14-BIT M1
COUNTER

14-BIT M2
COUNTER

13-BIT CONTROL

REGISTER

(00)

DATA

CLK

EN

M

U
X

(010)

START BIT

16-BIT

DATA/ADDRESS

REGISTER

(011)

(11X)

(01)

VCO_H

VCO_L

CPI

CP2

F

REF

CPOUT

2-BIT

CP1

11-BIT R1
COUNTER

2-BIT

CP2

11-BIT R2
COUNTER

Figure 5. 3-Wire Control Block Diagram

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

16 ______________________________________________________________________________________

MSB

DATA

CLK

*SB

*START BIT MUST BE LOGIC HIGH.

LSB

EN

RISE AND FALL REQUIRED PRIOR TO EN GOING LOW.

Figure 6. 3-Wire Interface Timing Diagram

Table 4. Control Register, Default State: 0B57h,Address: 110

b

SB

STBY

Logic “0” enables standby mode, which shuts down the VGA and
demodulator stages, leaving the VCO locked and the registers
active.

1

FT FM_TYPE

Active in FM mode. Logic “0” selects quadrature demodulator for
FM mode. Logic “1” selects downconversion to I port.

1

0 3

SD

SHDN

Logic “0” enables register-based shutdown. This mode shuts down
everything except the M and R latches and the serial bus.

1 0

IS IN_SEL Logic “0” selects FM input port. Logic “1” selects CDMA input.1 2

BE

BUFEN

Logic “1” disables LOOUT. Logic “0” enables LOOUT.1 4

VS VCO_SEL Logic “1” selects VCO_H. Logic “0” selects VCO_L.1

DS DIV_SEL Logic “1” selects M1/R1 divide ratios. Logic “0” selects M2/R2.

6

1 8

BD BUF_DIV

Logic “1” selects divide-by-2 on LOOUT port. Logic “0” bypasses
divider.

0 5

VB VCO_BYP Logic “1” bypasses the VCO inputs for external VCO operation.0 7

TE TEST_ENABLE Must be 0 for normal operation.0 10

TC TURBO_CHARGE

Logic “1” activates turbocharge mode, which provides rapid fre­quency acquisition in the PLL.

1 9

POL CP_POL

Logic “1” causes the charge-pump output CP_OUT to source cur­rent when f

REF

/R > f

VCO

/M. This state is used when the VCO tune
polarity is such that increasing voltage produces increasing fre­quency. Logic “0” causes CP_OUT to source current when f

VCO

/M

> f

REF

/R. This state is used when increasing tune voltage causes

the VCO frequency to decrease.

1 11

BIT NAME FUNCTIONBIT ID

TM TEST_MODE Must be 0 for normal operation.0 12

BIT

LOCATION

0 = LSB

POWER-

UP

STATE

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________ 17

CP

2/0

CP

1/1CP1/0R1/10

CP

2/1

/1 R

2/10

M

1/0

M113

M

2

13

M

2/0

A2/M0A1A

0

A2/M0A1A

0

CP2 AND R2 REGISTERS

SHIFT REGISTER

M1 REGISTER

M2 REGISTER

CP1 AND R1 REGISTERS

CTRL REGISTER

ADDRESS

DECODED

START BIT

1

00

1

0

0

1

0

1

1

1

0R

1/0

R

2/0

0

1TM POL TE TC DS VB VS BD BE FT IS SB SD

DATA

Figure 7. Programming Logic

DEFAULTREGISTER

M2 4269

DEC

M1 10519

DEC

CTRL 0B57

HEX

R2 492

DEC

R1 492

DEC

CP1 11

BIN

CP0 11

BIN

Table 5. Register Defaults

CHARGE-PUMP CURRENT

AFTER ACQUISITION

(µA)

CP1

0 210

0 150

CP0

1

0

1

0

1 425

1 300

Table 6. Charge-Pump Control Bits

Chip Information

TRANSISTOR COUNT: 6422

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

18 ______________________________________________________________________________________

Functional Diagram

CP1

CP2

M1 REGISTER

M2 REGISTER

R1 REGISTER

R2 REGISTER

LOGIC

SB

SHIFT REGISTER1

00

14

11

11

010

011

110TM POL TE TC

DS

VBVSBD

BE

FT IS

SB

SD

DATA

CLK

CONTROL

2

2

2

2

2

REF

FM+

FM-

CDMA+
CDMA-

IOUT+

VGC

FT

VB

IOUT-

QOUT+
QOUT-

LO_OUT

TANKL+

VCO_L

MODE

DS

14

11 11

14

14

POL

11

2

IS

VS

DIVSEL

TANKL-

TANKH+
TANKH-

LOCK

BD BE

÷2

TC

BUFEN

R COUNTER M COUNTER

LOCK DET

TURBO

CONTROL

CP_OUT

CHARGE

PUMP

Ø

DET

SB

MAX2309 MAX2309

SD

SHDN

STBY

VCO_H

1401

÷2

BIAS

EN

MAX2306
MAX2308
MAX2309

MAX2306

MAX2309

MAX2306
MAX2308

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________ 19

BYP

BYP

FM- FM+

CDMA+

DAC

CDMA-

LOCK

VGA

AVCC

V

CC

DATA

CLK

QOUT+

QOUT-

EN

TANKH-

IOUT-

IOUT+

REF

DV

CC

MODE

TANKH+

TANKL-

AGND

CP_OUT

BYP

SHDN

TANKL+

/2

0

90

CHARGE

PUMP

PHASE

DETECTOR

/R

/M

MAX2306

V

CC

Block Diagram

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer

Pin Configurations

28

27

26

25

24

23

22

TANKL-

GND

CP_OUT

BYP

BYP

BYP

FM-

8

9

10

11

12

13

14

IOUT+

IOUT-

LOCK

QOUT-

QOUT+

CLK

15

16

17

18

19

20

21

DATA

V

CC

VGC

CDMA-

CDMA+

FM+

7

6

5

4

3

2

1

REF

GND

V

CC

MODE

TANKH-

TANKH+

TANKL+

MAX2306

(T) QFN-EP

TOP VIEW

SHDN

EN

28

27

26

25

24

23

22

DIVSEL

GND

CP_OUT

BYP

BYP

BYP

8

9

10

11

12

13

14

IOUT+

IOUT-

LOCK

QOUT-

QOUT+

CLK

15

16

17

18

19

20

21

DATA

V

CC

VGC

CDMA-

CDMA+

N.C.

7

6

5

4

3

2

1

REF

GND

V

CC

LOOUT

TANKH-

TANKH+

MAX2309

(T) QFN-EP

SHDN

STBY

EN

28

27

26

25

24

23

22

N.C.

GND

CP_OUT

BYP

BYP

BYP

FM-

8

9

10

11

12

13

14

IOUT+

IOUT-

LOCK

QOUT-

QOUT+

CLK

15

16

17

18

19

20

21

DATA

V

CC

VGC

CDMA-

CDMA+

FM+

7

6

5

4

3

2

1

REF

GND

V

CC

N.C.

TANKH-

TANKH+

N.C.

MAX2308

(T) QFN-EP

SHDN

EN

BUFEN

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

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