General Description
The MAX2121 low-cost, direct-conversion tuner IC is
designed for satellite set-top and VSAT applications.
The device directly converts the satellite signals from
the LNB to baseband using a broadband I/Q downconverter. The operating frequency range extends from
925MHz to 2175MHz.
The device includes an LNA and an RF variable-gain
amplifier, I and Q downconverting mixers, and baseband lowpass filters and digitally controlled baseband
variable-gain amplifiers. Together, the RF and baseband variable-gain amplifiers provide more than 80dB
of gain control range.
The device includes fully monolithic VCOs, as well as a
complete fractional-N frequency synthesizer.
Additionally, an on-chip crystal oscillator is provided
along with a buffered output for driving additional tuners
and demodulators. Synthesizer programming and device
configuration are accomplished with a 2-wire serial interface. The IC features a VCO autoselect (VAS) function
that automatically selects the proper VCO. For multituner
applications, the device can be configured to have one
of two 2-wire interface addresses. A low-power standby
mode is available whereupon the signal path is shut
down while leaving the reference oscillator, digital interface, and buffer circuits active, providing a method to
reduce power in single and multituner applications.
The device is the most advanced broadband/VSAT
DBS tuner available. The low noise figure eliminates the
need for an external LNA. A small number of passive
components are needed to form a complete broadband
satellite tuner DVB-S2 RF front-end solution. The tuner
is available in a very small, 5mm x 5mm, 28-pin thin
QFN package.
Applications
VSATs
Features
♦ 925MHz to 2175MHz Frequency Range
♦ Monolithic VCO
Low Phase Noise: -97dBc/Hz at 10kHz
No Calibration Required
♦ High Dynamic Range: -75dBm to 0dBm
♦ Integrated LP Filters: 123.75MHz
♦ Single +3.3V ±5% Supply
♦ Low-Power Standby Mode
♦ Address Pin for Multituner Applications
♦ Differential I/Q Interface
♦ I
2
C 2-Wire Serial Interface
♦ Very Small, 5mm x 5mm, 28-Pin TQFN Package
MAX2121
Complete Direct-Conversion L-Band Tuner
________________________________________________________________
Maxim Integrated Products
1
Functional Diagram
Ordering Information
19-5959; Rev 0; 6/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
*
EP = Exposed pad.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX2121ETI+ -40°C to +85°C 28 TQFN-EP*
CC_BB
V
SDA
26 24 23
MAX2121
FREQUENCY
SYNTHESIZER
QDC-
25
DC OFFSET
CORRECTION
QDC+
IDC-
21
20
19
18
17
16
V
CC_RF2
V
CC_RF1
V
GND
RFIN
GC1
CC_LO
+
1
2
3
4
5
6
ADDR
27
28
INTERFACE LOGIC
AND CONTROL
DIV2/DIV4
EP
SCL
IDC+
IOUT-
IOUT+
QOUT-
QOUT+
V
CC_DIG
V
CC_VCO
XTAL
15
REFOUT
7
10 12
8
BYPVCO
9
TUNEVCO
11 132214
CPOUT
GNDSYN
GNDTUNE
CC_SYN
V
MAX2121
Complete Direct-Conversion L-Band Tuner
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(MAX2121 Evaluation Kit: V
CC_
= +3.13V to +3.47V, f
XTAL
= 27MHz, TA= -40°C to +85°C, V
GC1
= +0.5V (max gain), default register
settings except BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited. Typical values measured at V
CC
=
+3.3V, T
A
= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC_
to GND .........................................................-0.3V to +3.9V
All Other Pins to GND.................................-0.3V to (V
CC
+ 0.3V)
RF Input Power: RFIN .....................................................+10dBm
BYPVCO, CPOUT, XTAL, REFOUT, IOUT_, QOUT_ , IDC_,
QDC_ to GND Short-Circuit Protection...............................10s
Continuous Power Dissipation (T
A
= +70°C)
TQFN (derate 34.5mW/°C above +70°C) ......................2.75W
Operating Temperature Range .............................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
CAUTION! ESD SENSITIVE DEVICE
SUPPLY
Supply Voltage (V
Supply Current
ADDRESS SELECT INPUT (ADDR)
Digital Input-Voltage High, VIH 2.4 V
Digital Input-Voltage Low, VIL 0.5 V
Digital Input-Current High, IIH 50 μA
Digital Input-Current Low, IIL -50 μA
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range Max imum gain = 0.5V 0.5 2.7 V
Input Bias Current -50 +50 μA
VCO TUNING VOLTAGE INPUT (TUNEVCO)
Input Voltage Range 0.4 2.3 V
2-WIRE SERIAL INPUTS (SCL, SDA)
Cloc k Frequenc y 400 kHz
Input Logic-Level High
Input Logic-Level Low
Input Leakage Current Digital inputs = GND or VCC ±0.1 ±1 μA
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low I
PARAMETER CONDITIONS MIN TYP MAX UNITS
) 3.13 3.3 3.47 V
CC_
Receive mode, bit STBY = 0 148 200
Standby mode, bit STBY = 1 3
SINK
= 1mA (Note 2) 0.4 V
0.7 x
V
CC
V
0.3 x
V
CC
mA
V
MAX2121
Complete Direct-Conversion L-Band Tuner
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(MAX2121 Evaluation Kit: V
CC
= +3.13V to +3.47V, TA= -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
values measured at V
CC
= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MAIN SIGNAL PATH PERFORMANCE
Minimum Gain fIN = 2175MHz 72 78 dB
Gain Flatness 925MHz to 2175MHz (Note 2) 4 6 dB
Input Frequency Range (Note 3) 925 2175 MHz
RF Gain-Control Range (GC1) 0.5V < V
Baseband Gain-Control Range Bits BBG[3:0] = 1111 to 0000 11.5 13.5 dB
In-Band Input IP3 (Note 4) +2 dBm
Out-of-Band Input IP3 (Note 5) +15 dBm
Input IP2 (Note 6) +40 dBm
Noise Figure
Minimum RF Input Return Loss 925MHz < f
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing R
I/Q Amplitude Imbalance Measured at 500kH z ±1 dB
I/Q Quadrature Phase Imbalance Measured at 500kH z 3.5 Degrees
Single-Ended I/Q Output
Impedance
Output 1dB Compression Voltage Differential 3 V
Baseband Highpass -3dB
Frequency Corner
BASEBAND LOWPASS FILTERS (5th-Order Butterworth with 1st-Order Group Delay Compensation)
Filter Bandwidth (-3dB) 123.75 MHz
Rejection Ratio At 247.5MHz 31 dB
Group Delay Up to 0.5dB bandwidth 1.0 ns
3dB Bandwidth Tolerance ±10 %
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range 925 2175 MHz
RF-Divider Range (N) 19 251
Reference-Divider Frequency
Range
Reference-Di vider Range (R) 1 1
Phase-Detector Comparison
Frequency
< 2.7V 65 73 dB
GC1
V
is set to 0.5V (maximum RF gain) and BBG[3:0]
GC1
is ad justed to give a 1V
-75dBm CW input tone at 1500MHz
Starting with the same BBG[3:0] setting as above,
V
is adjusted to back off RF gain by 10dB (Note 2)
GC1
< 2175MHz, in 75 system 12 dB
RF
= 200//5pF 0.5 1 V
LOAD
Real Z
47nF capacitors at IDC_, QDC_ 400 Hz
12 30 MHz
12 30 MHz
, from 1MH z to 140MHz 24
O
baseband output leve l for a
P-P
8
9 12
dB
P-P
P-P
MAX2121
Complete Direct-Conversion L-Band Tuner
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2121 Evaluation Kit: V
CC
= +3.13V to +3.47V, TA= -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
values measured at V
CC
= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Note 1: Min/max values are production tested at TA= +25°C. Min/max limits at TA= -40°C and TA= +85°C are guaranteed by
design and characterization.
Note 2: Guaranteed by design and characterization at T
A
= +25°C.
Note 3: Input gain range specifications met over this band.
Note 4: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f
LO
= 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
-26dBm each are applied at 1919MHz and 1663MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the
RF input.
Note 5: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f
LO
= 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
-20dBm each are applied at 1919MHz and 1663MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the
RF input.
Note 6: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (f
LO
= 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm
each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 7: See Table 16 for crystal ESR requirements.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency Range 925 2175 MHz
LO Phase Noise
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency
Range f
XTAL
Input Overdrive Leve l AC-coupled sine-wave input 0.5 1 2.0 V
XTAL Output-Buffer Divider
Range
XTAL Output Voltage Swing 12MHz to 30MHz, C
XTAL Output Duty Cycle 50 %
f
= 10kHz -97
OFFSET
f
= 100kHz -100
OFFSET
= 1MHz -122
f
OFFSET
Paralle l-resonance-mode crystal (Note 7) 12 30 MHz
1 8
= 10pF 1 1.5 2 V
LOAD
dBc/Hz
P-P
P-P
MAX2121
Complete Direct-Conversion L-Band Tuner
_______________________________________________________________________________________
5
Typical Operating Characteristics
(MAX2121 Evaluation Kit: V
CC
= +3.3V, TA= +25°C, baseband output frequency = 5MHz, V
GC1
= +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2121 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.43.33.2
130
135
140
145
150
155
160
165
170
175
125
3.1 3.5
TA = +85°C
TA = +25°C
TA = -40°C
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX2121 toc02
SUPPLY VOLTAGE (V)
STANDBY SUPPLY CURRENT (mA)
3.43.33.2
1.5
2.0
2.5
3.0
1.0
3.1 3.5
TA = +85°C
TA = -40°C
HD3 vs. V
OUT
MAX2121 toc03
V
OUT
(V
P-P
)
BASEBAND 3RD-ORDER HARMONIC (dBc)
2.52.01.5
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-60
1.0 3.0
QUADRATURE PHASE ERROR
vs. LO FREQUENCY
MAX2121 toc04
LO FREQUENCY (MHz)
QUADRATURE PHASE ERROR (DEG)
1900165014001150
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
900 2150
f
BASEBAND
= 50MHz
TA = +85°C
TA = +25°C
TA = -40°C
QUADRATURE MAGNITUDE MATCHING
vs. LO FREQUENCY
MAX2121 toc05
LO FREQUENCY (MHz)
QUADRATURE MAGNITUDE MATCHING (dB)
1900165014001150
0.2
0.4
0.6
0.8
1.0
0
900 2150
f
BASEBAND
= 50MHz
TA = +85°C
TA = +25°C
TA = -40°C
QUADRATURE PHASE ERROR
vs. BASEBAND FREQUENCY
MAX2121 toc06
BASEBAND FREQUENCY (MHz)
QUADRATURE PHASE ERROR (DEG)
101
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.1 100
fLO = 1425MHz
TA = +85°C
TA = +25°C
TA = -40°C
QUADRATURE MAGNITUDE MATCHING
vs. BASEBAND FREQUENCY
MAX2121 toc07
BASEBAND FREQUENCY (MHz)
QUADRATURE MAGNITUDE MATCHING (dB)
101
0.2
0.4
0.6
0.8
1.0
0
0.1 100
fLO = 1425MHz
TA = +85°C
TA = +25°C
TA = -40°C
BASEBAND FILTER FREQUENCY RESPONSE
MAX2121 toc08
BASEBAND FREQUENCY (MHz)
BASEBAND OUTPUT LEVEL (dB)
400300200100
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
-65
0 500
BASEBAND FILTER FREQUENCY RESPONSE
MAX2121 toc09
BASEBAND FREQUENCY (MHz)
BASEBAND OUTPUT LEVEL (dB)
125100755025
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
-10
0 150
TA = +25°C
MAX2121
Complete Direct-Conversion L-Band Tuner
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX2121 Evaluation Kit: V
CC
= +3.3V, TA= +25°C, baseband output frequency = 5MHz, V
GC1
= +1.2V, default register settings
except BBG[3:0] = 1011, unless otherwise noted.)
BASEBAND FILTER 3dB FREQUENCY
vs. TEMPERATURE
MAX2121 toc10
TEMPERATURE (°C)
BASEBAND GAIN ERROR AT f-3dB (dB)
8060-20 0 20 40
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
-40
NORMALIZED AT TA = +25°C
BASEBAND FILTER HIGHPASS
FREQUENCY RESPONSE
MAX2121 toc11
BASEBAND FREQUENCY (Hz)
BASEBAND OUTPUT LEVEL (dB)
1000
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
-10
100 10,000
VOLTAGE GAIN vs. V
GC1
MAX2121 toc12
V
GC1
(V)
VOLTAGE GAIN (dB)
2.52.00.5 1.0 1.5
10
20
30
40
50
60
70
80
0
0 3.0
BBG[3:0] = 1111
NOISE FIGURE vs. LO FREQUENCY
(T
A
= +25°C)
MAX2121 toc13
LO FREQUENCY (MHz)
NOISE FIGURE (dB)
190016501150 1400
7.5
8.0
8.5
9.0
10.0
9.5
10.5
11.0
7.0
900 2150
ADJUST BBG[3:0] FOR 1V
P-P
BASEBAND
OUTPUT WITH PIN = -75dBm AND V
GC1
= 0.5V
10dB BACKED OFF GAIN
INPUT RETURN LOSS vs. FREQUENCY
MAX2121 toc14
FREQUENCY (MHz)
INPUT RETURN LOSS (dB)
202518001350 15751125
-20
-15
-10
-5
0
-25
900 2250
V
GC1
= 2.7V
V
GC1
= 0.5V
PHASE NOISE AT 10kHz OFFSET vs.
CHANNEL FREQUENCY
CHANNEL FREQUENCY (MHz)
PHASE NOISE AT 10kHz OFFSET (dBc/Hz)
MAX2121 toc15
925 1115 1305 1495 1685 1875 2065 2255
-105
-100
-95
-90
PHASE NOISE vs. OFFSET FREQUENCY
MAX2121 toc16
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1.0E+051.0E+04
-120
-110
-100
-90
-130
1.0E+03 1.0E+06
fLO = 1800MHz
LO LEAKAGE vs. LO FREQUENCY
LO FREQUENCY (MHz)
LO LEAKAGE (dBm)
MAX2121 toc17
925 1175 1425 1675 1925 2175
-90
-85
-80
-75
-70
MEASURED AT RF INPUT
VCO: KV vs. VTUNE
VTUNE (V)
KV (MHz/V)
MAX2121 toc18
0 0.5 1.0 1.5 2.0 2.5 3.0
0
50
100
150
200
250
300
350
400
450
SUB-BAND 23
SUB-BAND 12
SUB-BAND 0
MAX2121
Complete Direct-Conversion L-Band Tuner
_______________________________________________________________________________________ 7
Pin Description
Pin Configuration
TOP VIEW
V
CC_RF2
V
CC_RF1
V
V
CC_VCO
GND
RFIN
GC1
CC_LO
SDA
25
CC_BB
V
QDC-
QDC+
IDC-
22
21
IDC+
SCL
ADDR
26 24 23
27
28
1
+
IOUT-
2
3
20
IOUT+
19
MAX2121
QOUT-
4
5
6
7
10 12
8
BYPVCO
9
TUNEVCO
11 13
GNDSYN
GNDTUNE
CPOUT
EP
CC_SYN
V
18
QOUT+
17
16
V
CC_DIG
15
REFOUT
14
XTAL
TQFN
(5mm x 5mm)
PIN NAME FUNCTION
1 V
2 V
CC_RF2
CC_RF1
3 GND Ground. Connect to board’s ground plane for proper operation.
4 RFIN Wideband 75 RF Input. Connect to an RF source through a DC-bloc king capacitor.
5 GC1
6 V
7 V
CC_LO
CC_VCO
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range.
= 0.5V corresponds to the max imum gain setting.
V
GC1
DC Power Supply for LO Generation Circuit s. Connect to a +3.3V low-noi se supply. B ypass to GND
with a 1nF capacitor connected as c lose as po ss ible to the pin. Do not share capacitor ground via s
with other ground connections.
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. By pass to GND with a 1nF
capacitor connected a s close a s possible to the pin. Do not share capacitor ground vias with other
ground connect ions.
MAX2121
Complete Direct-Conversion L-Band Tuner
8 _______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
8 BYPVCO
9 TUNEVCO
10 GNDTUNE Ground for TUNEVCO. Connect to the PCB ground plane.
11 GNDSYN Ground for Synthesiz er. Connect to the PCB ground plane.
12 CPOUT
13 V
14 XTAL
15 REFOUT Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry.
16 V
17 QOUT+
18 QOUT-
19 IOUT+
20 IOUT-
21 IDC+
22 IDC-
23 QDC+
24 QDC-
25 V
26 SDA 2-Wire Serial-Data Interface. Requires 1k pullup res istor to VCC.
27 SCL 2-Wire Serial-Clock Interface. Require s 1k pullup resistor to VCC.
28 ADDR Address. Must be connected to either ground (logic 0) or suppl y (logic 1).
— EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation.
CC_S YN
CC_DIG
CC_BB
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
the pin. Do not share capacitor ground via s with other ground connections.
High-Impedance VCO Tune Input. Connect the PLL loop filter output directl y to this pin with as short of
a connection as possible.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest
connection possible.
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypas s to GND with
a 1nF capacitor connected as close a s possible to the pin. Do not share capacitor ground vias with
other ground connections.
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series
1nF capacitor. See the Typical Application Circuit.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close a s possible to the pin. Do not share capacitor ground vias with
other ground connections.
Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+.
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+.
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close a s possible to the pin. Do not share capacitor ground vias with
other ground connections.
MAX2121
Complete Direct-Conversion L-Band Tuner
_______________________________________________________________________________________ 9
Detailed Description
Register Description
The MAX2121 includes 12 user-programmable registers
and two read-only registers. See Table 1 for register
configurations. The register configuration of Table 1
shows each bit name and the bit usage information for all
registers. Note that all registers must be written after and
no earlier than 100µs after the device is powered up.
Table 1. Register Configuration
X = Don’t care. 0 = Set to 0 for factory-tested operation. 1 = Set to 1 for factory-tested operation.
REG
NUMBER
REGISTER
NAME
1
2
3
4
5
6
7 PLL Write 0x06 D24 CPS ICP X X X X X
8 VCO Write 0x07 VCO[4] VCO[3] VCO[2] VCO[1] VCO[0] VAS ADL ADE
9
10 Control Write 0x09 STBY X
11 Shutdown Write 0x0A X
12 Test Write 0x0 B
13
14
N-Di v id er
MSB
N-Di v id er
LSB
Charge
Pump
F-Divider
MSB
F-Divider
LSB
XTAL
Buffer and
Reference
Divider
Lowpass
Filter
Status
Byte-1
Status
Byte-2
READ/
WRITE
Write 0x00
Writ e 0x01 N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0]
Write 0x02
Write 0x03 F[15] F[14] F[13] F[12] F[11] F[10] F[9] F[8]
Write 0x04 F[7] F[6] F[5] F[4] F[3] F[2] F[1] F[0]
Write 0x05 XD[2] XD[1] XD[0] R[4] R[3] R[2] R[1] R[0]
Write 0x08 10010111
Read 0x0C POR VASA VASE LD X X X X
Re ad 0x 0D VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
REG
ADDRESS
MSB LSB
DATA BYTE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
FRAC
1
CPMP[ 1] 0CPMP[ 0] 0CPLIN[1] 0CPLIN[0]
CPTST[2] 0CPTST[1] 0CPTST[0]
N[14] N[13] N[12] N[11] N[10] N[9] N[8]
F[19] F[18] F[17] F[16]
BB 0RFMIX 0RFVGA 0FE
TURBO
1
LD
MUX[2]
LD
MUX[1]
0
0
PLL
0
PWDN
0
DIV
0
0
1
X BBG[3] BBG[2] BBG[1] BBG[0]
VCO
0
X
0
LD
MUX[0]
0
MAX2121
Complete Direct-Conversion L-Band Tuner
10 ______________________________________________________________________________________
Table 2. N-Divider MSB Register (Address: 0x00)
Table 3. N-Divider LSB Register (Address: 0x01)
Table 4. Charge-Pump Register (Address: 0x02)
Table 5. F-Divider MSB Register (Address: 0x03)
Table 6. F-Divider LSB Register (Address: 0x04)
Table 7. XTAL Buffer and Reference Divider Register (Address: 0x05)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
FRAC 7 1 Users must program to 1 upon powering up the device.
N[14:8] 6–0 0000000
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
N[7:0] 7–0 00100011
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
CPMP[1:0] 7–6 00
CPLIN[1:0] 5–4 00
F[19:16] 3–0 0010
Sets the most significant bits of the PLL integer-divide number (N). N can
range from 19 to 251.
Sets the lea st s ignificant bits of the PLL integer-divide number. N can range
from 19 to 251.
Charge-pump minimum pulse width. Users must program to 00 upon
powering up the device.
Controls charge-pump linearity. U sers must program to 01 upon powering
up the device.
Sets the 4 most significant bits of the PLL fractional divide number.
Default value is F = 194,180 decimal.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
F[15:8] 7–0 11110110
Sets the most significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
F[7:0] 7–0 10000100
Sets the least significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Sets the crystal-divider setting.
000 = Di vide by 1.
001 = Di vide by 2.
XD[2:0] 7–5 000
R[4:0] 4–0 00001
011 = Di vide by 3.
100 = Di vide by 4.
101 through 110 = All di vide va lues from 5 (101) to 7 (110).
111 = Di vide by 8.
Sets the PLL reference-divider (R) number. Users must program to 00001
upon powering up the dev ice.
00001 = Divide by 1; other values are not tested.
MAX2121
Complete Direct-Conversion L-Band Tuner
______________________________________________________________________________________ 11
Table 8. PLL Register (Address: 0x06)
Table 9. VCO Register (Address: 0x07)
Table 10. Lowpass Filter Register (Address: 0x08)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
VCO divider setting.
D24 7 1
CPS 6 1
ICP 5 0
X 4–0 X Don’t care.
0 = Divide by 2. Use for LO frequencies 1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
Charge-pump current mode.
0 = Charge-pump current control led by ICP bit.
1 = Charge-pump current controlled by VCO autoselect (VAS).
Charge-pump current.
0 = 600μA typical.
1 = 1200μA typical.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
VCO[4:0] 7–3 11001
VAS 2 1
ADL 1 0
ADE 0 0
Controls which VCO is activated when using manual VCO programming mode.
This also serves as the starting point for the VCO autoselection (VAS) mode.
VCO autoselection (VAS) circuit.
0 = Disable VCO selection must be programmed through I2C.
1 = Enable VCO selection controlled by autoselection circuit.
Enables or disables the VCO tuning vo ltage ADC latch when the VCO
autoselect mode (VAS) is disabled.
0 = Disables the ADC latch.
1 = Latches the ADC value.
Enables or disables VCO tuning voltage ADC read when the VCO
autoselect mode (VAS) is disabled.
0 = Disables ADC read.
1 = Enables ADC read.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Reserved 7–0 01001011 User must program to 10010111 (97h) upon powering up the device.
MAX2121
Complete Direct-Conversion L-Band Tuner
12 ______________________________________________________________________________________
Table 11. Control Register (Address: 0x09)
Table 12. Shutdown Register (Address: 0x0A)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Software standby control.
0 = Normal operation.
STBY 7 0
X 6 X Don’t care.
PWDN 5 0
X 4 X Don’t care.
BBG[3:0] 3–0 0000
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
X 7 X Don’t care.
PLL 6 0
DIV 5 0
VCO 4 0
BB 3 0
RFMIX 2 0
RFVGA 1 0
FE 0 0
1 = Disables the signal path and frequency synthesizer leaving only the
2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider
active.
Factor y use only.
0 = Normal operation; other value is not tested.
Baseband gain setting (1dB typica l per step).
0000 = Minimum gain (0dB, default).
…
1111 = Maximum gain (15dB typical).
PLL enable.
0 = Normal operation.
1 = Shuts down the PLL. Value not tested.
Divider enable.
0 = Normal operation.
1 = Shuts down the d ivider. Value not tested.
VCO enable.
0 = Normal operation.
1 = Shuts down the VCO. Value not tested.
Baseband enable.
0 = Normal operation.
1 = Shuts down the baseband. Value not te sted.
RF mixer enable.
0 = Normal operation.
1 = Shuts down the RF m ixer. Value not tested.
RF VGA enab le.
0 = Normal operation.
1 = Shuts down the RF VGA. Value not tested.
Front-end enable.
0 = Normal operation.
1 = Shuts down the front-end. Value not te sted.
MAX2121
Complete Direct-Conversion L-Band Tuner
______________________________________________________________________________________ 13
Table 13. Test Register (Address: 0x0B)
Table 14. Status Byte-1 Register (Address: 0x0C)
Table 15. Status Byte-2 Register (Address: 0x0D)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
CPTST[2:0] 7–5 000
X 4 X Don’t care.
TURBO 3 1
LDMUX[2:0] 2 –0 000
Charge-pump test modes.
000 = Normal operation (default).
Charge-pump fast lock.
Users mu st program to 1 after powering up the dev ice.
REFOUT output.
000 = Normal operation; other values are not tested.
BIT NAME BIT LOCATION (0 = LSB) FUNCTION
Power-on reset status.
POR 7
VASA 6
VASE 5
LD 4
X 3–0 Don’t care.
0 = Chip status register has been read with a stop condition since last power-on.
1 = Power-on reset (power cycle) has occurred. Default values have been loaded in
registers.
Indicates whether VCO autoselection was successful.
0 = Indicates the autoselect function is disabled or unsuccessful VCO selection.
1 = Indicates successful VCO autoselection.
Status indicator for the autoselect function.
0 = Indicates the autoselect function is active.
1 = Indicates the autoselect process is inactive.
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
0 = Unlocked.
1 = Loc ked.
BIT NAME BIT LOCATION (0 = LSB) FUNCTION
VCOSBR[4:0] 7–3 VCO band readback.
VAS ADC output readback.
000 = Out of lock.
001 = Locked.
ADC[2:0] 2–0
010 = VAS locked.
101 = VAS locked.
110 = Locked.
111 = Out of lock.
MAX2121
Complete Direct-Conversion L-Band Tuner
14 ______________________________________________________________________________________
2-Wire Serial Interface
The MAX2121 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX2121 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX2121 behaves as a
slave device that transfers and receives data to and
from the master. SDA and SCL must be pulled high
with external pullup resistors (1kΩ or greater) for proper
bus operation. Pullup resistors should be referenced to
the MAX2121’s VCC.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2121 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the
START and STOP Conditions
section). Both SDA
and SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master and the MAX2121 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX2121 has a 7-bit slave address that must be
sent to the device following a START condition to initiate communication. The slave address is internally programmed to 1100000. The eighth bit (R/W) following
the 7-bit address determines whether a read or write
operation occurs.
The MAX2121 continuously awaits a START condition
followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
The write/read address is C0/C1 if ADDR pin is connected to ground. The write/read address is C2/C3 if
the ADDR pin is connected to VCC.
Write Cycle
When addressed with a write command, the MAX2121
allows the master to write to a single register or to multiple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2121 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the address
of the first register it wishes to write to (see Table 1 for
register addresses). If the slave acknowledges the
address, the master can then write one byte to the register at the specified address. Data is written beginning
with the most significant bit. The MAX2121 again issues
an ACK if the data is successfully written to the register.
The master can continue to write data to the successive
internal registers with the MAX2121 acknowledging each
successful transfer, or it can terminate transmission by
issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition.
Figure 1. MAX2121 Slave Address Byte with ADDR Pin
Connected to Ground
Figure 2. Example: Write Registers 0, 1, and 2 with 0x0E, 0xD8, and 0xE1, respectively.
SLAVE ADDRESS
1100000
S
SDA
SCL
1 234567
ACK
R/W
89
WRITE DEVICE
START
ADDRESS
1100000 0 — 0x00 — 0x0E — 0xD8 — 0xE1 —
R/W ACK
WRITE REGISTER
ADDRESS
ACK
WRITE DATA TO
REGISTER 0x00
ACK
WRITE DATA TO
REGISTER 0x01
ACK
WRITE DATA TO
REGISTER 0x02
ACK
STOP
MAX2121
Complete Direct-Conversion L-Band Tuner
______________________________________________________________________________________ 15
Read Cycle
When addressed with a read command, the MAX2121
allows the master to read back a single register, or multiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2121 issues an
ACK if the slave address byte is successfully received.
The bus master must then send the address of the first
register it wishes to read (see Table 1 for register
addresses). The slave acknowledges the address.
Then, a START condition is issued by the master, followed by the seven slave address bits and a read bit
(R/W = 1). The MAX2121 issues an ACK if the slave
address byte is successfully received. The MAX2121
starts sending data MSB first with each SCL clock
cycle. At the 9th clock cycle, the master can issue an
ACK and continue to read successive registers, or the
master can terminate the transmission by issuing a
NACK. The read cycle does not terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which registers 0, 1,
and 2 are read back.
Application Information
The MAX2121 downconverts RF signals in the 925MHz
to 2175MHz range directly to the baseband I/Q signals.
RF Input
The RF input of the MAX2121 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Application Circuit
.
RF Gain Control
The MAX2121 features a variable-gain low-noise amplifier providing 73dB of RF gain range. The voltage control (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB
steps. The VGA gain can be serially programmed
through the I2C interface by setting bits BBG[3:0] in the
Control register.
Baseband Lowpass Filter
The MAX2121 includes an on-chip 5th-order Butterworth
filter with 1st-order group delay compensation.
DC Offset Cancellation
The DC offset cancellation is required to maintain the
I/Q output dynamic range. Connecting an external
capacitor between IDC+ and IDC- forms a highpass filter for the I channel and an external capacitor between
QDC+ and QDC- forms a highpass filter for the Q channel. Keep the value of the external capacitor less than
47nF to form a typical highpass corner of 250Hz.
XTAL Oscillator
The MAX2121 contains an internal reference oscillator,
reference output divider, and output buffer. All that is
required is to connect a crystal through a series 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL).
See Table 16 for crystal (XTAL) ESR (equivalent series
resistance) requirements.
Programming the Fractional
N- Synthesizer
The MAX2121 utilizes a fractional-N type synthesizer for
LO frequency programming. To program the frequency
synthesizer, the N and F values are encoded as
straight binary numbers. Determination of these values
is illustrated by the following example:
fLOis 2170MHz
f
XTAL
is 27 MHz
Phase-detector comparison frequency is from 12MHz
and 30MHz
R divider = R[4:0] = 1
f
COMP
= 27MHz/1 = 27MHz
D = fLO/f
COMP
= 2170/27 = 80.37470
Figure 3. Example: Receive Data from Read Registers
Table 16. Maximum Crystal ESR
Requirement
START
WRITE DEVICE ADDRESS ACK READ FROM STATUS BYTE-1 REGISTER ACK READ FROM STATUS B YTE-2 REGISTER
1100000 1 — — — — —
R/W
ACK/
NACK
STOP
ESR
() XTAL FREQUENCY (MHz)
MAX
80 12 < f
60 14 < f
XTAL
XTAL
14
30
MAX2121
Complete Direct-Conversion L-Band Tuner
16 ______________________________________________________________________________________
Integer portion:
N = 80
N[14:8] = 0
N[7:0] = 0101 0000
Fractional portion:
F = 0.370370 x 2
20
= 388,361 (round up the decimal portion)
F = 0101 1110 1101 0000 1001
Note: When changing LO frequencies, all the divider
registers (integer and fractional) must be programmed
to activate the VAS function regardless of whether individual registers are changed.
VCO Autoselect (VAS)
The MAX2121 includes 24 VCOs. The local oscillator
frequency can be manually selected by programming
the VCO[4:0] bits in the VCO register. The selected VCO
is reported in the Status Byte-2 register (see Table 15).
Alternatively, the MAX2121 can be set to autonomously
choose a VCO by setting the VAS bit in the VCO register to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (register 5) is loaded.
In the event that only the N-divider register or
F-divider MSB word is changed, the F-divider LSB
word must also be loaded last to initiate the VCO
autoselect function. The VCO value programmed in the
VCO[4:0] register serves as the starting point for the automatic VCO selection process.
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits VASE
and VASA are set and the VCO selected is reported in the
Status Byte-2 register (see Table 15). If the search is
unsuccessful, VASA is cleared and VASE is set. This indicates that searching has ended but no good VCO has
been found, and occurs when trying to tune to a frequency outside the VCO’s specified frequency range.
Refer to Application Note 4256:
Extended Characterization
for the MAX2112/MAX2120 Satellite Tuners
.
3-Bit ADC
The MAX2121 has an internal 3-bit ADC connected to
the VCO tune pin (TUNEVCO). This ADC can be used
for checking the lock status of the VCOs.
Table 17 summarizes the ADC output bits and the VCO
lock indication. The VCO autoselect routine only selects
a VCO in the “VAS locked” range. This allows room for
a VCO to drift over temperature and remain in a valid
“locked” range.
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a subsequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the Status Byte-2 register
(see Table 15).
Standby Mode
The MAX2121 features normal operating mode and
standby mode using the I2C interface. Setting a logichigh to the STBY bit in the Control register puts the
device into standby mode, during which only the 2wire-compatible bus, the crystal oscillator, the XTAL
buffer, and the XTAL buffer divider are active.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
mode. Default register values are provided for the
user’s convenience only. It is the user’s responsibility to
load all the registers no sooner than 100µs after the
device is powered up.
Layout Considerations
The MAX2121 EV kit serves as a guide for PCB layout.
Keep RF signal lines as short as possible to minimize
losses and radiation. Use controlled impedance on all
high-frequency traces. For proper operation, the
exposed paddle must be soldered evenly to the board’s
ground plane. Use abundant vias beneath the exposed
paddle for maximum heat dissipation. Use abundant
ground vias between RF traces to minimize undesired
coupling. Bypass each V
CC
pin to ground with a 1nF
capacitor placed as close as possible to the pin.
Table 17. ADC Trip Points and Lock Status
ADC[2:0] LOCK STATUS
000 Out of loc k
001 Loc ked
010 VAS locked
101 VAS locked
110 Loc ked
111 Out of loc k
MAX2121
Complete Direct-Conversion L-Band Tuner
______________________________________________________________________________________ 17
Typical Application Circuit
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN-EP T2855+3
21-0140 90-0023
RF INPUT
V
GC
SERIAL-DATA
INPUT/OUTPUT
SERIAL-CLOCK
INPUT
SCL
SDA
26 24 23
27
V
CC
V
V
CC
V
CC
CC_RF2
V
CC_RF1
GND
RFIN
GC1
V
CC_LO
V
CC
V
CC_VCO
+
1
2
3
4
5
6
7
ADDR
28
INTERFACE LOGIC
AND CONTROL
DIV2
/DIV4
EP
V
CC
CC_BB
V
25
MAX2121
FREQUENCY
SYNTHESIZER
QDC-
QDC+
DC OFFSET
CORRECTION
IDC-
22
IDC+
21
IOUT-
20
IOUT+
19
QOUT-
18
QOUT+
17
V
CC_DIG
16
REFOUT
15
BASEBAND
OUTPUTS
V
CC
10 12
9
8
BYPVCO
TUNEVCO
GNDTUNE
11 13
GNDSYN
CPOUT
V
CC
CC_SYN
V
14
XTAL
MAX2121
Complete Direct-Conversion L-Band Tuner
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 6/11 Initial release —
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
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