General Description
The MAX2120 low-cost, direct-conversion tuner IC is
designed for satellite set-top and VSAT applications.
The IC is intended for QPSK, Digital Video Broadcast
(DVB-S), DSS, and free-to-air applications.
The MAX2120 directly converts the satellite signals
from the LNB to baseband using a broadband I/Q
downconverter. The operating frequency range extends
from 925MHz to 2175MHz.
The device includes an LNA and an RF variable-gain
amplifier, I and Q downconverting mixers, and baseband
lowpass filters with programmable cutoff frequency
control and digitally controlled baseband variable-gain
amplifiers. Together, the RF and baseband variable-gain
amplifiers provide more than 80dB of gain-control range.
The IC is compatible with virtually all QPSK demodulators.
The MAX2120 includes fully monolithic VCOs, as well as
a complete frequency synthesizer. Additionally, an onchip crystal oscillator is provided along with a buffered
output for driving additional tuners and demodulators.
Synthesizer programming and device configuration are
accomplished with a 2-wire serial interface. The IC features a VCO autoselect (VAS) function that automatically
selects the proper VCO. For multituner applications, the
device can be configured to have one of two 2-wire
interface addresses. A low-power standby mode is
available whereupon the signal path is shut down while
leaving the reference oscillator, digital interface, and
buffer circuits active, providing a method to reduce
power in single and multituner applications.
The MAX2120 is the most advanced DBS tuner available
today. The low noise figure eliminates the need for an
external LNA. A small number of passive components are
needed to form a complete DVB, DBS, or VSAT RF frontend solution. The tuner is available in a very small 28-pin
thin QFN package.
Applications
DirecTV and Dish Network DBS
DVB-S
Two-Way Satellite Systems
VSATs
Free-to-Air
Features
o 925MHz to 2175MHz Frequency Range
o Monolithic VCO: No Calibration Required
o -75dBm to 0dBm High Dynamic Range
o 4MHz to 40MHz Integrated Variable BW LP Filters
o Single +3.3V ±5% Supply
o Low-Power Standby Mode
o Address Pin for Multituner Applications
o Differential I/Q Interface
o I2C 2-Wire Serial Interface
o Very Small 28-Pin Thin QFN Package
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
________________________________________________________________
Maxim Integrated Products
1
19-0832; Rev 2; 5/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
VTUNE
GNDSYN
CPOUT
VCC_SYN
XTAL
VCOBYP
SCL
VCC_BB
QDC-
ADDR
QDC+
IDC-
RFIN
GC1
VCC_LO
+
÷
IOUT+
QOUT-
VCC_DIG
GNDTUNE
SDA
19
17
16
3
5
18
4
6
VCC_VCO
REFOUT
15
7
GND
IOUT-
20
2
VCC_RF1
21
IDC+
1
26 24 23
10 12
25
11 132214
27
9
28
8
VCC_RF2
MAX2120
INTERFACE LOGIC
AND CONTROL
DC OFFSET
CORRECTION
LPF BW
CONTROL
DIV2/DIV4
EP
FREQUENCY
SYNTHESIZER
QOUT+
Pin Configuration/
Functional Diagram
Ordering Information
*
EP = Exposed paddle.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX2120CTI+ 0°C to +70°C 28 Thin QFN-EP*
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +3.9V
All Other Pins to GND.................................-0.3V to (V
CC
+ 0.3V)
RF Input Power: RFIN .....................................................+10dBm
VCOBYP, CPOUT, REFOUT, XTAL, IOUT_, QOUT_, IDC_, and
QDC_ Short-Circuit Protection.............................................10s
Continuous Power Dissipation (T
A
= +70°C)
28-Pin Thin QFN (derated 34.5mW/°C above +70°C)........2.75W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DC ELECTRICAL CHARACTERISTICS
(MAX2120 Evaluation Kit: VCC= +3.13V to +3.47V, V
GC1
= +0.5V (max gain), TA= 0°C to +70°C. No input signals at RF, baseband
I/Os are open circuited, and LO frequency = 2150MHz. Default register settings except BBG[3:0] = 1011. Typical values measured
at V
CC
= +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
CAUTION! ESD SENSITIVE DEVICE
PARAMETER CONDITIONS MIN TYP MAX UNITS
SUPPLY
Supply Voltage 3.13 3.3 3.47 V
Supply Current
ADDRESS SELECT INPUT (ADDR)
Digital Input-Voltage High, VIH 2.4 V
Digital Input-Voltage Low, VIL 0.5 V
Digital Input-Current High, IIH 50 µA
Digital Input-Current Low, IIL -50 µA
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range Max imum gain = 0.5V 0.5 2.7 V
Input Bias Current -50 +50 µA
VCO TUNING VOLTAGE INPUT (VTUNE)
Input Voltage Range 0.4 2.3 V
2-WIRE SERIAL INPUTS (SCL, SDA)
Cloc k Frequenc y 400 kH z
Input Logic-Level High
Input Logic-Level Low
Input Leakage Current Digital inputs = GND or VCC ±0.1 ±1 µA
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low I
Receive mode, bit STBY = 0 100 160
Standby mode, bit STBY = 1 3
= 1mA 0.4 V
SINK
0.7 x
V
CC
V
0.3 x
V
CC
mA
V
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(MAX2120 Evaluation Kit: VCC= +3.13V to +3.47V, V
GC1
= +0.5V (max gain), TA= 0°C to +70°C. Default register settings except
BBG[3:0] = 1011. Typical values measured at V
CC
= +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MAIN SIGNAL PATH PERFORMANCE
Input Frequency Range (Note 2) 925 2175 MHz
RF Gain-Control Range (GC1) 0.5V < V
Baseband Gain-Control Range Bits GC2 = 1111 to 0000 13 15 dB
In-Band Input IP3 (Note 3) +2 dBm
Out-of-Band Input IP3 (Note 4) +15 dBm
Input IP2 (Note 5) +40 dBm
Adjacent Channel Protection (Note 6) 25 dB
V
is set to 0.5V (maximum RF gain) and BBG[3:0] is
GC1
adjusted to give a 1V
Noise Figure
Minimum RF Input Return Loss 925MHz < f
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing R
I/Q Amplitude Imbalance Measured at 500kHz; filter set to 22.27MHz ±1 dB
I/Q Quadrature Phase Imbalance Measured at 500kHz; filter set to 22.27MHz 3.5 Degrees
Single-Ended I/Q Output
Impedance
Output 1dB Compression Voltage Differential 3 V
Baseband Highpass -3dB
Frequency Corner
BASEBAND LOWPASS FILTERS
Filter Bandwidth Range 4 40 MHz
Rejection Ratio At 2 x f
Group Delay Up to 1dB bandwidth 37 ns
Ratio of In-Filter-Band to Out-ofFilter-Band Noise
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range 925 2175 MHz
RF-Divider Range (N) 16 2175
Reference-Divider Frequency
Range
Reference-Divider Range (R) 1 31
Phase-Detector Comparison
Frequency
-75dBm CW input tone at 1500MHz
Starting with the same BBG[3:0] setting as above, V
is adjusted to back off RF gain by 10dB (Note 7)
LOAD
Real Z
O
47nF capacitors at IDC_, QDC_ 400 Hz
f
INBAND
112.5MHz
< 2.7V 65 73 dB
GC1
< 2175MHz, in 75Ω system 12 dB
RF
= 2kΩ//10pF 0.5 1 V
, from 1MHz to 40MHz 30 Ω
-3dB
= 100Hz to 22.5MHz, f
baseband output level for a
P-P
OUTBAND
= 87.5MHz to
GC1
4 30 MHz
1 2 MHz
8
912
39 dB
25 dB
dB
P-P
P-P
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2120 Evaluation Kit: VCC= +3.13V to +3.47V, V
GC1
= +0.5V (max gain), TA= 0°C to +70°C. Default register settings except
BBG[3:0] = 1011. Typical values measured at V
CC
= +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
Note 1: Min/max values are production tested at TA= +70°C. Min/max limits at TA= 0°C and TA= +25°C are guaranteed by design
and characterization.
Note 2: Gain-control range specifications met over this band.
Note 3: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f
LO
= 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
-26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the
RF input.
Note 4: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f
LO
= 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
-20dBm each are applied at 2070MHz and 1975MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the
RF input.
Note 5: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (f
LO
= 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm
each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 6: Adjacent channel protection test conditions: GC1 is set to provide the nominal baseband output drive with a 2110MHz
27.5Mbaud signal at -55dBm. GC2 set for mid-scale. The test signal will be set for PR = 7/8 and SNR of -8.5dB. An adjacent
channel at ±40MHz is added at -25dBm. DVB-S BER performance of 2E-4 will be maintained for the desired signal. GC2
may be adjusted for best performance.
Note 7: Guaranteed by design and characterization at T
A
= +25°C.
Note 8: See Table 14 for crystal ESR requirements.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency
Range
LO Phase Noise
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency
Range
Input Overdrive Level AC-coupled sine wave input 0.5 1 2.0 V
XTAL Output-Buffer Divider
Range
XTAL Output Voltage Swing 4MHz to 30MHz, C
XTAL Output Duty Cycle 50 %
T
= 0°C to +70°C 925 2175 MHz
A
f
OFFSET
f
OFFSET
f
OFFSET
Parallel-resonance-mode crystal (Note 8) 4 8 MHz
= 10kHz -82
= 100kHz -102
= 1MHz -122
18
= 10pF 1 1.5 2 V
LOAD
dBc/Hz
P-P
P-P
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
_______________________________________________________________________________________
5
Typical Operating Characteristics
(MAX2120 Evaluation Kit: VCC= +3.3V, baseband output frequency = 5MHz; V
GC1
= 1.2V; TA= +25°C. Default register settings
except BBG[3:0] = 1011.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
98
97
96
95
94
93
92
91
SUPPLY CURRENT (mA)
90
89
88
3.0 3.6
TA = +70°C
TA = +25°C
TA = 0°C
SUPPLY VOLTAGE (V)
HD3 vs. OUTPUT VOLTAGE
-10
-15
-20
-25
-30
-35
-40
-45
-50
BASEBAND 3RD-ORDER HARMONIC (dBc)
-55
-60
1.0 3.5
V
(V
)
OUT
P-P
QUADRATURE PHASE
vs. BASEBAND FREQUENCY
93.5
fLO = 925MHz
92.5
91.5
90.5
89.5
QUADRATURE PHASE (°)
88.5
87.5
86.5
020
BASEBAND FREQUENCY (MHz)
3.53.43.33.23.1
3.02.52.01.5
TA = +70°C
TA = +25°C
MAX2120 toc01
MAX2120 toc04
TA = 0°C
161284
STANDBY MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.900
2.800
2.700
2.600
2.500
SUPPLY CURRENT (mA)
2.400
2.300
TA = +70°C
TA = 0°C, +25°C
3.0 3.6
SUPPLY VOLTAGE (V)
QUADRATURE PHASE vs. LO FREQUENCY
93.5
f
= 10MHz
BASEBAND
92.5
91.5
90.5
89.5
QUADRATURE PHASE (°)
88.5
87.5
86.5
TA = +25°C
TA = +70°C
TA = 0°C
900 2400
LO FREQUENCY (MHz)
MAX2120 toc06a
3.53.43.33.23.1
2100180015001200
QUADRATURE MAGNITUDE MATCHING (dB)
vs. BASEBAND FILTER CUTOFF FREQUENCY
104
102
MAX2120 toc02
100
98
96
94
92
90
SUPPLY CURRENT (mA)
88
86
84
440
BASEBAND FILTER CUTOFF FREQUENCY (MHz)
QUADRATURE MAGNITUDE MATCHING
1.0
f
BASEBAND
0.8
MAX2120 toc05a
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
QUADRATURE MAGNITUDE MATCHING (dB)
-1.0
900 2400
QUADRATURE MAGNITUDE MATCHING
vs. BASEBAND FREQUENCY
1.0
fLO = 925MHz
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
TA = +25°C
020
BASEBAND FREQUENCY (MHz)
SUPPLY CURRENT
vs. LO FREQUENCY
= 10MHz
TA = +25°C
TA = 0°C
LO FREQUENCY (MHz)
TA = +70°C
TA = 0°C
MAX2120 toc03
3628 32242016128
MAX2120 toc05b
TA = +70°C
2100180015001200
MAX2120 toc06b
161284
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX2120 Evaluation Kit: VCC= +3.3V, baseband output frequency = 5MHz; V
GC1
= 1.2V; TA= +25°C. Default register settings
except BBG[3:0] = 1011.)
BASEBAND FILTER
FREQUENCY RESPONSE
MAX2120 toc07
BASEBAND FREQUENCY (MHz)
BASEBAND OUTPUT LEVEL (dB)
604020
-60
-50
-30
-40
-20
-10
0
-80
-70
080
BASEBAND FILTER HIGHPASS
FREQUENCY RESPONSE
MAX2120 toc08
BASEBAND FREQUENCY (MHz)
BASEBAND OUTPUT LEVEL (dB)
1000
-10
-8
-4
-6
-2
0
2
-14
-12
100 10,000
PROGRAMMED f
-3dB
FREQUENCY
vs. MEASURED f
-3dB
FREQUENCY
MAX2120 toc09
PROGRAMMED f
-3dB
FREQUENCY (MHz)
MEASURED f
-3dB
FREQUENCY (MHz)
402015 25 30 35510
5
10
20
15
25
35
30
40
45
0
045
LPF[7:0] = 12 + (f
-3dB
- 4MHz) / 290kHz
BASEBAND FILTER 3dB FREQUENCY
vs. TEMPERATURE
MAX2120 toc10
TEMPERATURE (°C)
BASEBAND GAIN ERROR AT f
-3dB
(dB)
4020 30 605010
-0.8
-0.6
0
-0.4
-0.2
0.2
0.6
0.4
0.8
1.0
-1.0
070
NORMALIZED TO TA = +25°C
INPUT POWER vs. V
GC1
MAX2120 toc11
V
GC1
(V)
INPUT POWER (dBm)
2.52.01.51.0
-60
-50
-40
-30
-20
-10
0
10
-80
-70
0.5 3.0
TA = +70°C
TA = +25°C
ADJUST BBG[3:0] FOR 1V
P-P
BASEBAND OUTPUT WITH
P
IN
= -75dBm AND V
GC1
= 0.5V
NOISE FIGURE vs. FREQUENCY
MAX2120 toc12
FREQUENCY (MHz)
NOISE FIGURE (dB)
210019001700150013001100
8.0
8.5
9.0
9.5
10.0
7.5
900 2300
TA = +70°C
TA = +25°C
ADJUST BBG[3:0] FOR 1V
P-P
BASEBAND OUTPUT WITH
P
IN
= -75dBm AND V
GC1
= 0.5V
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(MAX2120 Evaluation Kit: VCC= +3.3V, baseband output frequency = 5MHz; V
GC1
= 1.2V; TA= +25°C. Default register settings
except BBG[3:0] = 1011.)
NOISE FIGURE vs. INPUT POWER
MAX2120 toc13
INPUT POWER (dBm)
NOISE FIGURE (dB)
-20-30-40-50-60-70
20
10
30
40
50
60
70
0
-80 0-10
ADJUST BBG[3:0] FOR 1V
P-P
BASEBAND OUTPUT WITH
P
IN
= -75dBm AND V
GC1
= 0.5V
f
LO
= 1500MHz
OUT-OF-BAND IIP3 vs. INPUT POWER
MAX2120 toc14
INPUT POWER (dBm)
OUT-OF-BAND IIP3 (dBm)
-20-30-40-50-60-70
-10
-20
0
10
20
30
-30
-80 0-10
SEE NOTE 4 ON PAGE 4 FOR CONDITIONS
IN-BAND IIP3 vs. INPUT POWER
MAX2120 toc15
INPUT POWER (dBm)
IN-BAND IIP3 (dBm)
-20-30-40-50-60-70
-30
-50
-40
-10
-20
0
10
20
30
-60
-80 0-10
SEE NOTE 3 ON PAGE 4 FOR CONDITIONS
IIP2 vs. INPUT POWER
MAX2120 toc16
INPUT POWER (dBm)
IIP2 (dBm)
-20-30-40-50-60-70
0
10
30
20
40
50
60
-10
-80 0-10
SEE NOTE 5 ON PAGE 4 FOR CONDITIONS
INPUT RETURN LOSS vs. FREQUENCY
MAX2120 toc17
FREQUENCY (MHz)
INPUT RETURN LOSS (dB)
202518001350 15751125
-20
-15
-10
-5
0
-25
900 2250
V
GC1
= 2.7V
V
GC1
= 0.5V
PHASE NOISE AT 10kHz OFFSET
vs. CHANNEL FREQUENCY
MAX2120 toc18
CHANNEL FREQUENCY (MHz)
PHASE NOISE AT 10kHz OFFSET (dBc/Hz)
206518751305 1495 16851115
-86
-82
-78
-74
-70
-90
-84
-80
-76
-72
-88
925 2255
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
8 _______________________________________________________________________________________
Pin Description
Typical Operating Characteristics (continued)
(MAX2120 Evaluation Kit: VCC= +3.3V, baseband output frequency = 5MHz; V
GC1
= 1.2V; TA= +25°C. Default register settings
except BBG[3:0] = 1011.)
PHASE NOISE vs. OFFSET FREQUENCY
MAX2120 toc19
OFFSET FREQUENCY (kHz)
PHASE NOISE (dBc/Hz)
100110
-100
-90
-70
-60
-130
-110
-80
-120
0.1 1000
fLO = 1800MHz
LO LEAKAGE vs. LO FREQUENCY
MAX2120 toc20
LO FREQUENCY (MHz)
LO LEAKAGE (dBm)
19251175 16751425
-80
-70
-90
-85
-75
925 2175
MEASURED AT RF INPUT
PIN NAME FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
1 VCC_RF2
connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
2 VCC_RF1
connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
3 GND Ground. Connect to the board’s ground plane for proper operation.
4 RFIN Wideband 75Ω RF Input. Connect to an RF source through a DC-blocking capacitor.
5 GC1
RF Gain-Control Input. High-impedance analog input, with a 0.5V to 2.7V operating range. V
0.5V corresponds to the maximum gain setting.
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
6 VCC_LO
with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias
with other ground connections.
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
7 VCC_VCO
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
8 VCOBYP
9 VTUNE
10 GNDTUNE Ground for VTUNE. Connect to the PCB ground plane.
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
the pin. Do not share capacitor ground vias with other ground connections.
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short
of a connection as possible.
11 GNDSYN Ground for Synthesizer. Connect to the PCB ground plane.
12 CPOUT
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest connection
possible.
GC1
=
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
13 VCC_SYN
14 XTAL
15 REFOUT
16 VCC_DIG
17 QOUT+
18 QOUT-
19 IOUT+
20 IOUT-
21 IDC+
22 IDC-
23 QDC+
24 QDC-
25 VCC_BB
26 SDA 2-Wire Serial Data Interface. Requires a > 1kΩ pullup resistor to VCC.
27 SCL 2-Wire Serial Clock Interface. Requires a > 1kΩ pullup resistor to VCC.
28 ADDR Address. ADDR is at logic-high if unconnected.
—EP
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal by a series 1nF
capacitor. See the Typical Operating Circuit.
Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external
circuitry.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
with a 1nF capacitor connected as close to the pin as possible. Do not share capacitor ground vias
with other ground connections.
Quadrature Baseband Differential Output. AC-couple with a 47nF capacitor to the demodulator input.
In-Phase Baseband Differential Output. AC-couple with a 47nF capacitor to the demodulator input.
I-Channel baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to
IDC+.
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to
QDC+.
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a
1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
Exposed Paddle. Solder evenly to the board’s ground plane for proper operation.
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
10 ______________________________________________________________________________________
Table 1. Register Configuration
0 = Set to “0” for factory-tested operation.
1 = Set to “1” for factory-tested operation.
X = Don’t care.
Table 2. N-Divider MSB Register
Table 3. N-Divider LSB Register
Detailed Description
Register Description
The MAX2120 includes 12 user-programmable registers
and 2 read-only registers. See Table 1 for register con-
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all registers. Note that all registers must be written after and no
earlier than 100µs after the device is powered up.
REGNOREGISTER
1
2
3
4 Not Used Write 0x03 X X X X X X X X
5 Not Used Write 0x04 X X X X X X X X
6
7 PLL Write 0x06 D24 CPS ICP X X X X X
8 VCO Write 0x07 VCO[4] VCO[3] VCO[2] VCO[1] VCO[0] VAS ADL ADE
9 LPF Write 0x08 LPF[7] LPF[6] LPF[5] LPF[4] LPF[3] LPF[2] LPF[1] LPF[0]
10 Control Write 0x09 STBY X
11 Shutdown Write 0x0A X
12 Test Write 0x0B
13
14
NAME
N-Divider
MSB
N-Divider
LSB
Charge
Pump
XTAL
Divider/
R-Divider
Status
Byte-1
Status
Byte-2
READ/
WRITE
Write 0x00 X N[14] N[13] N[12] N[11] N[10] N[9] N[8]
Write 0x01 N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0]
Write 0x02
Write 0x05 XD[2] XD[1] XD[0] R[4] R[3] R[2] R[1] R[0]
Read 0x0C POR VASA VASE LD X X X X
Read 0x0D VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
REG
ADDRESS
MSB LSB
DATA BYTE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
CPMP[1]0CPMP[0]0CPLIN[1]0CPLIN[0]
PWDN
0
PLL
0
CPTST[2]0CPTST[1]0CPTST[0]
DIV
0
0
VCO
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
X 7 X Don’t care.
N[14:8] 6–0 0000011
Sets the most significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
N[7:0] 7–0 10110110
Sets the least significant bits of the PLL integer-divide number (N).
Default value i s N = 950 decimal. N can range from 16 to 2175.
0
X BBG[3] BBG[2] BBG[1] BBG[0]
0
X
XXXX
BB
TURBO
RFMIX0RFVGA0FE
0
LD
MUX[2]
1
0
LD
MUX[1]
0
0
LD
MUX[0]
0
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
______________________________________________________________________________________ 11
Table 4. Charge-Pump Register
Table 5. XTAL Buffer and Reference Divider Register
Table 6. PLL Register
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
CPMP[1:0] 7, 6 00
CPLIN[1:0] 5, 4 00
X 3–0 X Don’t care.
Charge-pump minimum pulse width. Users must program to 00
upon powering up the device.
Controls charge-pump linearity.
00 = Typically balanced charge and sink currents.
Other values are not tested.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Sets the crystal-divider setting.
000 = Divide by 1 (default)
001 = Divide by 2
XD[2:0] 7, 6, 5 000
R[4:0] 4–0 00100
011 = Divide by 3
100 = Divide by 4
101 through 110 = All divide values from 5 (101) to 7 (110)
111 = Divide by 8
Sets the PLL reference-divider (R) number.
00001 = Divide by 1
00010 = Divide by 2
00011 = Divide by 3
00100 = Divide by 4 (default)
00101 through 11110 = All divide values from 3 (00101) to 29
(11110)
11111 = Divide by 31
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
VCO divider setting.
D24 7 1
CPS 6 1
ICP 5 0
X 4–0 X Don’t care.
0 = Divide by 2. Use for LO frequencies ≥ 1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
Charge-pump current mode.
0 = Charge-pump current controlled by ICP bit
1 = Charge-pump current controlled by VCO autoselect (VAS)
Charge-pump current.
0 = 600µA typical
1 = 1200µA typical
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
12 ______________________________________________________________________________________
Table 7. VCO Register
Table 8. Lowpass Filter Register
Table 9. Control Register
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Controls which VCO is activated when using manual VCO
VCO[4:0] 7–3 11001
VAS 2 1
ADL 1 0
ADE 0 0
programming mode. Thi s also serves as the starting point for
the VCO autoselect mode.
VCO Autoselection (VAS) Circuit
0 = Disable VCO selection must be program through I2C
1 = Enable VCO selection controlled by autoselection circuit
Enables or disables the VCO tuning voltage ADC latch when
the VCO autoselect mode (VAS) is disabled.
0 = Disables the ADC latch
1 = Latches the ADC value
Enables or disables VCO tuning vo ltage ADC read when the
VCO autose lect mode (VAS) is disabled.
0 = Disables ADC read
1 = Enables ADC read
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
LPF[7:0] 7–0 01001011
Sets the baseband lowpass filter 3dB corner frequency. 3dB
corner frequency = 4MHz + (LPF[7:0] - 12) x 290kHz.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Software standby control.
0 = Normal operation
STBY 7 0
X 6 X Don’t care.
PWDN 5 0
X 4 X Don’t care.
BBG[3:0] 3–0 0000
1 = Disables the signal path and frequency synthesizer, leaving
only the 2-wire bus, crystal oscillator, XTALOUT buffer, and
XTALOUT buffer divider active
Factory use only.
0 = Normal operation; other value is not tested.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB)
…
1111 = Maximum gain (15dB typical)
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
______________________________________________________________________________________ 13
Table 10. Shutdown Register
Table 11. Test Register
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
X 7 X Don’t care.
PLL enable.
PLL 6 0
DIV 5 0
VCO 4 0
BB 3 0
RFMIX 2 0
0 = Normal operation
1 = Shuts down the PLL. Value not tested.
Divider enable.
0 = Normal operation
1 = Shuts down the divider. Value not tested.
VCO enable.
0 = Normal operation
1 = Shuts down the VCO. Value not tested.
Baseband enable.
0 = Normal operation
1 = Shuts down the baseband. Value not tested.
RF mixer enable.
0 = Normal operation
1 = Shuts down the RF mixer. Value not tested.
RF VGA enable.
RFVGA 1 0
FE 0 0
0 = Normal operation
1 = Shuts down the RF VGA. Value not tested.
RF front-end enable.
0 = Normal operation
1 = Shuts down the RF front-end. Value not tested.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Charge-pump test modes.
000 = Normal operation (default)
001 = Crystal translator ECL to CMOS path
CPTST[2:0] 7, 6, 5 000
X 4 X Don’t care.
TURBO 3 0
LDMUX[2:0] 2, 1, 0 000
100 = Both source and sink currents enabled
101 = Source current enabled
110 = Sink current enabled
111 = High impedance (both source and sink current disabled)
Charge-pump fast lock. Users must program to 1 upon powering
up the device.
REFOUT output.
000 = Normal operation; other values are not tested
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
14 ______________________________________________________________________________________
Table 12. Status Byte-1 Register
Table 13. Status Byte-2 Register
BIT NAME BIT LOCATION (0 = LSB) FUNCTION
Power-on reset status.
POR 7
0 = Chip status register has been read with a stop condition since last power-on
1 = Power-on reset (power cycle) has occurred, default values have been loaded
in registers
VASA 6
VASE 5
LD 4
X 3–0 Don’t care.
Indicates whether VCO autoselection was successful.
0 = Indicates the autoselect function is disabled or unsuccessful VCO selection
1 = Indicates successful VCO autoselection
Status indicator for the autoselect function.
0 = Indicates the autoselect function is active
1 = Indicates the autoselect process is inactive
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
0 = Unlocked
1 = Locked
BIT NAME BIT LOCATION (0 = LSB) FUNCTION
VCOSBR[4:0] 7–3 VCO band readback.
VAS ADC output readback.
000 = Out of lock
001 = Locked
ADC[2:0] 2, 1, 0
010 = VAS locked
101 = VAS locked
110 = Locked
111 = Out of lock
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
______________________________________________________________________________________ 15
2-Wire Serial Interface
The MAX2120 uses a 2-wire I2C-compatible serial
interface consisting of a serial data line (SDA) and a
serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX2120 and the
master at clock frequencies up to 400kHz. The master
initiates a data transfer on the bus and generates the
SCL signal to permit data transfer. The MAX2120
behaves as a slave device that transfers and receives
data to and from the master. SDA and SCL must be
pulled high with external pullup resistors (1kΩ or
greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2120 (8 bits and an
ACK/NACK). The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes
in SDA while SCL is high and stable are considered
control signals (see the
START and STOP Conditions
section). Both SDA and SCL remain high when the bus
is not busy. Pullup resistors should be referenced to the
MAX2120’s VCC.
START and STOP Conditions
The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master and the MAX2120 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX2120 has a 7-bit slave address that must be
sent to the device following a START condition to initiate communication. The slave address is internally programmed to 1100000. The eighth bit (R/W) following
the 7-bit address determines whether a read or write
operation will occur.
The MAX2120 continuously awaits a START condition
followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
The write/read address is C0/C1 if the ADDR pin is connected to ground. The write/read address is C2/C3 if
the ADDR pin is connected to VCC.
Write Cycle
When addressed with a write command, the MAX2120
allows the master to write to a single register or to multiple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2120 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to (see
Table 1 for register addresses). If the slave acknowledges the address, the master can then write one byte
to the register at the specified address. Data is written
beginning with the most significant bit. The MAX2120
again issues an ACK if the data is successfully written
to the register. The master can continue to write data to
the successive internal registers with the MAX2120
acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The
write cycle will not terminate until the master issues a
STOP condition.
Figure 1. MAX2120 Slave Address Byte with ADDR Pin
Connected to Ground
SLAVE ADDRESS
1100000
S
SDA
SCL
1 234567
ACK
R/W
89
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
16 ______________________________________________________________________________________
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Read Cycle
When addressed with a read command, the MAX2120
allows the master to read back a single register, or multiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2120 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read (see Table 1 for register addresses). The
slave acknowledges the address. Then, a START condition is issued by the master, followed by the 7 slave
address bits and a read bit (R/W = 1). The MAX2120
issues an ACK if the slave address byte is successfully
received. The MAX2120 starts sending data MSB first
with each SCL clock cycle. At the 9th clock cycle, the
master can issue an ACK and continue to read successive registers, or the master can terminate the transmission by issuing a NACK. The read cycle does not
terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which registers 0
through 2 are read back.
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
Figure 3. Example: Receive data from read registers.
WRITE
START
DEVICE
ADDRESS
1100000 0 — 0x00 — 0x0E — 0xD8 — 0x0E1 —
R/W ACK
WRITE
REGISTER
ADDRESS
ACK
WRITE DATA
TO REGISTER
ACK
0x00
S
T
A
R
T
DEVICE
ADDRESS
1100000
R / W
A
C
K
REGISTER
ADDRESS
000000000
S
T
A
R
T
ADDRESS
DEVICE
1100000 1
A
C
K
R / W
A
C
K
WRITE DATA
TO REGISTER
0x01
REG 00
DATA
xxxxxxxx
WRITE DATA
ACK
TO REGISTER
0x02
REG 01
A
DATA
C
K
xxxxxxxx
A
C
K
REG 02
DATA
xxxxxxxx
ACK
N
A
C
K
STOP
S
T
O
P
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
______________________________________________________________________________________ 17
Applications Information
The MAX2120 downconverts RF signals in the 925MHz to
2175MHz range directly to the baseband I/Q signals. The
devices are targeted for digital DBS tuner applications.
RF Input
The RF input of the MAX2120 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Operating Circuit
.
RF Gain Control
The MAX2120 features a variable-gain low-noise amplifier providing 73dB of RF gain range. The voltage-control
(VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain-control range programmable in 1dB
steps. The VGA gain can be serially programmed
through the SPI™ interface by setting bits BBG[3:0] in
the Control register.
Baseband Lowpass Filter
The MAX2120 includes a programmable on-chip 7thorder Butterworth filter. The -3dB corner frequency of
the baseband filter is programmable by setting the bits
LPF[7:0] in the Lowpass register. The value of the
LPF[7:0] is determined by the following equation:
where f
-3dB
is in units of MHz.
The filter can be adjusted from approximately 4MHz to
40MHz. Total device supply current depends on the filter BW setting, with increasing current commensurate
with increasing -3dB BW.
DC Offset Cancellation
The DC offset cancellation is required to maintain the I/Q
output dynamic range. Connecting an external capacitor
between IDC+ and IDC- forms a highpass filter for the I
channel, and an external capacitor between QDC+ and
QDC- forms a highpass filter for the Q channel. Keep the
value of the external capacitor less than 47nF to form a
typical highpass corner of 400Hz.
XTAL Oscillator
The MAX2120 contains an internal reference oscillator,
reference output divider, and output buffer. All that is
required is to connect a crystal through a series, 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL
pin). See Table 14 for crystal (XTAL) ESR (equivalent
series resistance) requirements. The typical input
capacitance is 40pF.
VCO Autoselect (VAS)
The MAX2120 includes 24 VCOs. The local oscillator frequency can be manually selected by programming the
VCO[4:0] bits in the VCO register. The selected VCO is
reported in the Status Byte-2 register (see Table 13).
Alternatively, the MAX2120 can be set to autonomously
choose a VCO by setting the VAS bit in the VCO register to logic-high. The VAS routine is initiated once the
N-divider LSB register word (REG 2) is loaded.
In the event that only the R-divider register or Ndivider MSB register word is changed, the N-divider
LSB word must also be loaded last to initiate the
VCO autoselect function. The VCO value pro-
grammed in the VCO[4:0] register serves as the starting point for the automatic VCO selection process.
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits
VASE and VASA are set and the VCO selected is
reported in the Status Byte-2 register (see Table 13). If
the search is unsuccessful, VASA is cleared and VASE
is set. This indicates that searching has ended but no
good VCO has been found, and occurs when trying to
tune to a frequency outside the VCO’s specified
frequency range.
Refer to the MAX2112/MAX2120 VAS application note
for more information.
LPF[7:0]dec =
()
.
,
fMHz
MHz
dB−
−
+
3
4
029
12
SPI is a trademark of Motorola, Inc.
Table 14. Maximum Cystal ESR
Requirements
ESR
() XTAL FREQUENCY (MHz)
MAX
150 4 < f
100 6 < f
40 8 < f
XTAL
XTAL
XTAL
13.5
6
8
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
18 ______________________________________________________________________________________
3-Bit ADC
The MAX2120 has an internal 3-bit ADC connected to
the VCO tune pin (VTUNE). This ADC can be used for
checking the lock status of the VCOs.
Table 15 summarizes the ADC trip points, and the VCO
lock indication. The VCO autoselect routine will only
select a VCO in the “VAS locked” range. This allows
room for a VCO to drift over temperature and remain in
a valid “locked” range.
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a subsequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the Status Byte-2 register
(see Table 13).
Standby Mode
The MAX2120 features normal operating mode and
standby mode using the I
2
C interface. Setting a logichigh to the PWDN bit in the Control register enables
power-down. In this mode, all circuitries except for the 2wire-compatible bus are disabled, allowing for programming of the MAX2120 registers while in power-down.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
mode. Default register values are provided for the
user’s convenience only. It’s the user’s responsibility to
load all the registers no sooner than 100µs after the
device is powered up.
Layout Considerations
The MAX2120 EV kit serves as a guide for PCB
layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on
all high-frequency traces. For proper operation, the
exposed paddle must be soldered evenly to the board’s
ground plane. Use abundant vias beneath the exposed
paddle for maximum heat dissipation. Use abundant
ground vias between RF traces to minimize undesired
coupling. Bypass each V
CC
pin to ground with a 1nF
capacitor placed as close as possible to the pin.
Table 15. ADC Trip Points and Lock Status
ADC[2:0] LOCK STATUS
000 Out of Lock
001 Loc ked
010 VAS Locked
101 VAS Locked
110 Loc ked
111 Out of Lock
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
______________________________________________________________________________________ 19
Typical Operating Circuit
RF INPUT
SERIAL DATA
INPUT/OUTPUT
SERIAL CLOCK
INPUT
SCL
V
CC
V
V
CC
VCC_RF2
CC
VCC_RF1
GND
RFIN
GC1
VCC_LO
V
CC
VCC_VCO
+
1
2
3
4
5
6
7
ADDR
28
INTERFACE LOGIC
AND CONTROL
DIV2/DIV4
EP
SDA
26 24 23
27
VCC_BB
25
MAX2120
LPF BW
CONTROL
FREQUENCY
SYNTHESIZER
V
CC
QDC-
QDC+
DC OFFSET
CORRECTION
IDC-
22
÷
21
20
19
18
17
16
15
IDC+
IOUT-
IOUT+
QOUT-
QOUT+
VCC_DIG
REFOUT
BASEBAND
OUTPUTS
V
CC
8
VCOBYP
9
VTUNE
GNDTUNE
11 13
GNDSYN
CPOUT
VCC
VCC_SYN
14
XTAL
10 12
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
20 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN T2855+3
21-0140 90-0023
Chip Information
PROCESS: BiCMOS
MAX2120
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Revision History
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
21
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION
NUMBER
0 6/07 Initial release —
1 3/08
2 5/10 Corrected D24 bit Function in Table 6 11
REVISION
DATE
DESCRIPTION
Corrected errors in data sheet, replaced Read Cycle section and Figure 3,
added Table 14
PAGES
CHANGED
1–18
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