The MAX2065 high-linearity, analog/digital variablegain amplifier (VGA) is designed to operate in the
50MHz to 1000MHz frequency range with two independent attenuators (see the
Typical Application Circuit
).
The digital attenuator is controlled as a slave peripheral
using either the SPI™-compatible interface or a parallel
bus with 31dB total adjustment range in 1dB steps. An
added feature allows “rapid-fire” gain selection
between each of four steps, preprogrammed by the
user through the SPI-compatible interface. The 2-pin
control allows the user to quickly access any one of
four customized attenuation states without reprogramming the SPI bus. The analog attenuator is controlled
using an external voltage or through the SPI-compatible
interface using an on-chip 8-bit DAC.
Because each of the three stages has its own RF input
and RF output, this component can be configured to
either optimize NF (amplifier configured first), OIP3 (amplifier last), or a compromise of NF and OIP3. The device’s
performance features include 22dB amplifier gain (amplifier only), 6.5dB NF at maximum gain (includes attenuator
insertion losses), and a high OIP3 level of +42dBm. Each
of these features makes the MAX2065 an ideal VGA for
numerous receiver and transmitter applications.
In addition, the MAX2065 operates from a single +5V
supply with full performance, or a single +3.3V supply
with slightly reduced performance, and has an
adjustable bias to trade current consumption for linearity
performance. This device is available in a compact 40pin thin QFN package (6mm x 6mm) with an exposed
pad. Electrical performance is guaranteed over the
extended temperature range (TC= -40°C to +85°C).
Applications
IF and RF Gain Stages
Temperature Compensation Circuits
Cellular Band WCDMA and cdma2000®Base
Stations
GSM 850/GSM 900 EDGE Base Stations
WiMAX and LTE Base Stations and Customer
Premise Equipment
Fixed Broadband Wireless Access
Wireless Local Loop
Military Systems
Video-on-Demand (VOD) and DOCSIS®-
Compliant EDGE QAM Modulation
Cable Modem Termination Systems (CMTS)
Features
♦ 50MHz to 1000MHz RF Frequency Range
♦ Pin-Compatible Family Includes:
MAX2066 (Digital VGA)
MAX2067 (Analog VGA)
♦ +19.4dB (Typ) Maximum Gain
♦ 0.5dB Gain Flatness Over 100MHz Bandwidth
♦ 62dB Gain Range (31dB Analog + 31dB Digital)
♦ Built-in DAC for Analog Attenuation Control
♦ Supports Four “Rapid-Fire” Preprogrammed
Attenuator States
Quickly Access Any One of Four Customized
Attenuation States Without Reprogramming
the SPI Bus
Ideal for Fast-Attack, High-Level Blocker Protection
Prevents ADC Overdrive Condition
♦ Excellent Linearity (Configured with Amplifier
Last)
+42dBm OIP3
+63dBm OIP2
+19dBm Output 1dB Compression Point
-67dBc HD2
-83dBc HD3
♦ 6.5dB Typical Noise Figure (NF)
♦ Fast, 25ns Digital Switching
♦ Very Low Digital VGA Amplitude Overshoot/
Undershoot
♦ Single +5V Supply (Optional +3.3V Operation)
♦ External Current-Setting Resistors Provide Option
for Operating Device in Reduced-Power/
Reduced-Performance Mode
, high-current (HC) mode, VCC= +3.0V to +3.6V, TC= -40°C to +85°C. Typical values are at VCC= +3.3V
and T
C
= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Based on junction temperature TJ= TC+ (θJCx VCCx ICC). This formula can be used when the temperature of the exposed
pad is known while the device is soldered down to a printed-circuit board (PCB). See the
Applications Information
section
for details. The junction temperature must not exceed +150°C.
Note 2: Junction temperature T
J
= TA+ (θJAx VCCx ICC). This formula can be used when the ambient temperature of the PCB is
known. The junction temperature must not exceed +150°C.
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.
Note 4: T
C
is the temperature on the exposed pad of the package. TAis the ambient temperature of the device and PCB.
VCC_ to GND ........................................................-0.3V to +5.5V
VDD_LOGIC, DATA, CS, CLK, SER/PAR, VDAC_EN,
VREF_SELECT.....................................-0.3V to (VCC_ + 0.3V)
STATE_A, STATE_B, D0–D4 ....................-0.3V to (VCC_ + 0.3V)
AMP_IN, AMP_OUT, VREF_IN,
ANALOG_VCTRL ................................-0.3V to (VCC_ + 0.3V)
ATTEN1_IN, ATTEN1_OUT, ATTEN2_IN,
ATTEN2_OUT...................................................-1.2V to + 1.2V
RSET to GND........................................................-0.3V to + 1.2V
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, VCC= +4.75 to +5.25V, HC mode with each attenuator set for maximum gain, 50MHz ≤ fRF≤ 1000MHz,
T
C
= -40°C to +85°C. Typical values are at VCC= +5.0V, HC mode, PIN= -20dBm, fRF= 200MHz, and TC= +25oC, unless otherwise
noted.) (Note 5)
Note 5: All limits include external component losses. Output measurements are performed at RF output port of the
Typical
Application Circuit
.
Note 6: Operating outside this range is possible, but with degraded performance of some parameters.
Note 7: Guaranteed by design and characterization.
Note 8: It is advisable not to operate continuously the VGA RF input above +15dBm.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Analog Control Input Impedance80kΩ
Input Return Loss50Ω source22dB
Output Return Loss50Ω load22dB
D/A CONVERTER
Number of Bits8Bits
Output Voltage
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speedf
Data-to-Clock Setup Timet
Data-to-Clock Hold Timet
Clock-to-CS Setup Timet
CS Positive Pulse Widtht
CS Setup Timet
Clock Pulse Widtht
DAC code = 000000000.25
DAC code = 111111112.75
CLK
CS
CH
ES
EW
EWS
CW
20MHz
2ns
2.5ns
3ns
7ns
3.5ns
5ns
V
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
(VCC= +5.0V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
(VCC= +5.0V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
S21 PHASE CHANGE OVER DIGITAL
ATTENUATOR SETTING vs. RF FREQUENCY
60
50
40
30
20
10
S21 PHASE CHANGE (DEG)
0
REFERENCED TO HIGH GAIN STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
-10
501050
RF FREQUENCY (MHz)
GAIN vs. ANALOG ATTENUATOR SETTING
22
17
12
7
2
GAIN (dB)
-3
-8
-13
-18
TC = -40°C, +25°C, +85°C
0256
DAC CODE
RF = 200MHz
12864 96224160 19232
MAX2065 toc10
850450650250
MAX2065 toc13
GAIN OVER ANALOG ATTENUATOR
SETTING vs. RF FREQUENCY
22
17
12
DAC CODE 32
7
2
GAIN (dB)
-3
DAC CODE 128
-8
-13
-18
501050
RF FREQUENCY (MHz)
DAC CODE 0
DAC CODE 64
DAC CODE 256
GAIN vs. ANALOG ATTENUATOR SETTING
22
17
12
7
2
GAIN (dB)
-3
-8
-13
-18
0256
VCC = 4.75V, 5.00V, 5.25V
12864 96224160 19232
DAC CODE
850450650250
RF = 200MHz
MAX2065 toc11
GAIN (dB)
MAX2065 toc14
INPUT MATCH (dB)
GAIN vs. ANALOG ATTENUATOR SETTING
22
17
12
7
2
1000MHz
-3
-8
-13
-18
0256
50MHz
200MHz
450MHz
12864 96224160 19232
DAC CODE
INPUT MATCH
vs. ANALOG ATTENUATOR SETTING
0
-5
-10
-15
-20
-25
-30
0256
50MHz
1000MHz
200MHz
12864 96224160 19232
DAC CODE
450MHz
MAX2065 toc12
MAX2065 toc15
OUTPUT MATCH
vs. ANALOG ATTENUATOR SETTING
0
-5
450MHz
-10
-15
-20
OUTPUT MATCH (dB)
50MHz
-25
-30
0256
1000MHz
200MHz
12864 96224160 19232
DAC CODE
ATTENUATOR SETTING vs. RF FREQUENCY
-30
MAX2065 toc16
-40
-50
REVERSE ISOLATION (dB)
-60
-70
REVERSE ISOLATION OVER ANALOG
DAC CODE 0
DAC CODE 255
250450650850
501050
RF FREQUENCY (MHz)
80
70
MAX2065 toc17
60
50
40
30
20
S21 PHASE CHANGE (DEG)
10
0
-10
0258
S21 PHASE CHANGE
vs. ANALOG ATTENUATOR SETTING
REFERENCED TO HIGH GAIN STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
1000MHz
32 64 96 128 160224192
DAC CODE
450MHz
200MHz
50MHz
MAX2065 toc18
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
(VCC= +5.0V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
(VCC= +5.0V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
2nd HARMONIC
vs. ANALOG ATTENUATOR STATE
P
= 0dBm
OUT
RF = 200MHz
TC = +25°C
TC = +85°C
32 64 96 128 160 192 224
TC = -40°C
DAC CODE
3rd HARMONIC
vs. DIGITAL ATTENUATOR STATE
P
= 0dBm
OUT
TC = +25°C
TC = +85°C
TC = -40°C
RF = 200MHz
2nd HARMONIC vs. RF FREQUENCY
80
VCC = 5.25V
70
60
2nd HARMONIC (dBc)
50
40
VCC = 4.75V
250450650850
501050
RF FREQUENCY (MHz)
VCC = 5.00V
3rd HARMONIC vs. RF FREQUENCY
110
100
90
80
3rd HARMONIC (dBc)
70
TC = +85°C
TC = +25°C
TC = -40°C
2nd HARMONIC
vs. DIGITAL ATTENUATOR STATE
MAX2065 toc28
2nd HARMONIC (dBc)
80
TC = -40°C
75
70
TC = +85°C
65
60
4812 16 20 24 28
032
DIGITAL ATTENUATOR STATE (dB)
TC = +25°C
P
= 3dBm
OUT
P
= 0dBm
OUT
RF = 200MHz
MAX2065 toc29
2nd HARMONIC (dBc)
80
75
70
65
60
0256
3rd HARMONIC vs. RF FREQUENCY
100
MAX2065 toc32
3rd HARMONIC (dBc)
95
90
85
80
75
MAX2065 toc31
3rd HARMONIC (dBc)
110
100
P
= 3dBm
OUT
VCC = 5.25V
VCC = 5.00V
90
80
70
VCC = 4.75V
P
= 3dBm
OUT
MAX2065 toc30
MAX2065 toc33
60
501050
250450650850
RF FREQUENCY (MHz)
3rd HARMONIC
vs. ANALOG ATTENUATOR STATE
100
95
90
85
80
3rd HARMONIC (dBc)
75
70
TC = +25°C
TC = +85°C
TC = -40°C
32 64 96 128 160 192 224 256
0
DAC CODE
P
= 0dBm
OUT
RF = 200MHz
MAX2065 toc34
60
501050
250450650850
RF FREQUENCY (MHz)
OIP2 vs. RF FREQUENCY
75
70
65
60
55
OIP2 (dBm)
50
45
40
50
TC = -40°C
TC = +25°C
2504506508501050
RF FREQUENCY (MHz)
P
OUT
TC = +85°C
= 0dBm/TONE
MAX2065 toc35
70
4812 16 20 24 28 32
0
DIGITAL ATTENUATOR STATE (dB)
OIP2 vs. RF FREQUENCY
75
70
65
60
55
OIP2 (dBm)
50
45
40
VCC = 4.75V
501050
250450650850
RF FREQUENCY (MHz)
VCC = 5.00V
P
OUT
VCC = 5.25V
= 0dBm/TONE
MAX2065 toc36
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
(VCC= +5.0V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
(VCC= +5.0V, LC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal reference
used, unless otherwise noted.)
(VCC= +5.0V, LC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal reference
used, unless otherwise noted.)
OUTPUT P1dB vs. RF FREQUENCY
(LOW CURRENT MODE)
18
TC = -40°C
17
16
15
OUTPUT P1dB (dBm)
14
13
TC = +85°C
2504506508501050
50
RF FREQUENCY (MHz)
OUTPUT IP3 vs. RF FREQUENCY
(LOW CURRENT MODE)
45
40
VCC = 5.00V
TC = +25°C
VCC = 5.25V
MAX2065 toc56
OUTPUT P1dB (dBm)
MAX2065 toc59
OUTPUT P1dB vs. RF FREQUENCY
(LOW CURRENT MODE)
18
17
16
15
14
13
VCC = 5.25V
2504506508501050
50
VCC = 5.00V
RF FREQUENCY (MHz)
VCC = 4.75V
OUTPUT IP3 vs. DIGITAL ATTENUATOR
STATE (LOW CURRENT MODE)
45
TC = +25°C LSB, USB
40
P
= -3dBm/TONE
OUT
RF = 200MHz
MAX2065 toc57
OUTPUT IP3 (dBm)
MAX2065 toc60
OUTPUT IP3 vs. RF FREQUENCY
(LOW CURRENT MODE)
45
40
35
30
25
50
TC = +25°C
TC = -40°C
TC = +85°C
2504506508501050
RF FREQUENCY (MHz)
OUTPUT IP3 vs. ANALOG ATTENUATOR
STATE (LOW CURRENT MODE)
45
P
= -3dBm/TONE
OUT
RF = 200MHz
40
MAX2065 toc58
MAX2065 toc61
35
OUTPUT IP3 (dBm)
30
25
VCC = 4.75V
2504506508501050
50
RF FREQUENCY (MHz)
2nd HARMONIC vs. RF FREQUENCY
(LOW CURRENT MODE)
80
70
60
2nd HARMONIC (dBc)
50
40
2504506508501050
50
RF FREQUENCY (MHz)
TC = +25°C
P
= 3dBm
OUT
TC = -40°C
TC = +85°C
OUTPUT IP3 (dBm)
MAX2065 toc62
2nd HARMONIC (dBc)
35
TC = -40°C LSB, USB
30
25
48 12 16 20 24 28 32
0
DIGITAL ATTENUATOR STATE (dB)
TC = +85°C LSB, USB
2nd HARMONIC vs. RF FREQUENCY
(LOW CURRENT MODE)
80
VCC = 5.00V
70
60
VCC = 4.75V
50
40
2504506508501050
50
RF FREQUENCY (MHz)
P
= 3dBm
OUT
VCC = 5.25V
OUTPUT IP3 (dBm)
MAX2065 toc63
2nd HARMONIC (dBc)
35
30
25
TC = -40°C, +25°C, +85°C
TONE = LSB, USB
32 64 98 128 160 192 224 256
0
DAC CODE
2nd HARMONIC vs. DIGITAL ATTENUATOR
STATE (LOW CURRENT MODE)
80
75
70
65
60
TC = -40°C
TC = +85°C
TC = +25°C
0
4812201624 28 32
DIGITAL ATTENUATOR STATE (dB)
P
= 0dBm
OUT
RF = 200MHz
MAX2065 toc64
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
(VCC= +5.0V, LC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal reference
used, unless otherwise noted.)
2nd HARMONIC vs. ANALOG ATTENUATOR
STATE (LOW CURRENT MODE)
DAC CODE
2nd HARMONIC (dBc)
32 64 96160128192 224 256
80
60
75
70
65
0
MAX2065 toc65
TC = +85°C
TC = -40°C
TC = +25°C
P
OUT
= 0dBm
RF = 200MHz
3rd HARMONIC vs. RF FREQUENCY
(LOW CURRENT MODE)
RF FREQUENCY (MHz)
3rd HARMONIC (dBc)
2504506508501050
110
60
100
90
80
70
50
MAX2065 toc66
TC = +85°C
TC = -40°C
TC = +25°C
P
OUT
= 3dBm
OIP2 vs. RF FREQUENCY
(LOW CURRENT MODE)
RF FREQUENCY (MHz)
OIP2 (dBm)
2504506508501050
75
40
70
65
60
45
50
55
50
MAX2065 toc71
VCC = 5.25V
VCC = 5.00V
VCC = 4.75V
P
OUT
= 0dBm/TONE
OIP2 vs. DIGITAL ATTENUATOR
STATE (LOW CURRENT MODE)
DIGITAL ATTENUATOR STATE (dB)
OIP2 (dBm)
84121620242832
75
40
70
65
60
45
50
55
0
MAX2065 toc72
P
OUT
= -3dBm/TONE
RF = 200MHz
TC = +85°C
TC = -40°C
TC = +25°C
OIP2 vs. ANALOG ATTENUATOR
STATE (LOW CURRENT MODE)
DAC CODE
OIP2 (dBm)
643296 128 160 192 224 256
75
40
70
65
60
45
50
55
0
MAX2065 toc73
P
OUT
= -3dBm/TONE
RF = 200MHz
TC = +85°C
TC = -40°C
TC = +25°C
3rd HARMONIC vs. RF FREQUENCY
(LOW CURRENT MODE)
RF FREQUENCY (MHz)
3rd HARMONIC (dBc)
2504506508501050
110
60
100
90
80
70
50
MAX2065 toc67
VCC = 5.25V
VCC = 5.00V
VCC = 4.75V
P
OUT
= 3dBm
3rd HARMONIC vs. DIGITAL ATTENUATOR
STATE (LOW CURRENT MODE)
DIGITAL ATTENUATOR STATE (dB)
3rd HARMONIC (dBc)
4812 16 20 24 28 32
100
70
95
90
85
75
80
0
MAX2065 toc68
TC = +25°C
TC = +85°C
TC = -40°C
P
OUT
= 0dBm
RF = 200MHz
3rd HARMONIC vs. ANALOG ATTENUATOR
STATE (LOW CURRENT MODE)
DAC CODE
3rd HARMONIC (dBc)
32 64 96 128 160 192 224 256
100
70
95
90
85
75
80
0
MAX2065 toc69
TC = +25°C
TC = +85°C
TC = -40°C
P
OUT
= 0dBm
RF = 200MHz
OIP2 vs. RF FREQUENCY
(LOW CURRENT MODE)
RF FREQUENCY (MHz)
OIP2 (dBm)
2504506508501050
75
40
70
65
60
45
50
55
50
MAX2065 toc70
TC = +25°C
TC = +85°C
TC = -40°C
P
OUT
= 0dBm/TONE
MAX2065
Typical Operating Characteristics (continued)
(VCC= +3.3V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
(VCC= +3.3V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
(VCC= +3.3V, HC mode, both attenuators set for maximum gain, PIN= -20dBm, fRF= 200MHz, and TC= +25°C, internal DAC reference used, unless otherwise noted.)
3rd HARMONIC vs. RF FREQUENCY
RF FREQUENCY (MHz)
3rd HARMONIC (dBc)
2504506508501050
110
50
100
90
80
70
60
50
MAX2065 toc93
TC = -40°C
P
OUT
= 3dBm
TC = +85°C
TC = +25°C
VCC = 3.3V
3rd HARMONIC vs. RF FREQUENCY
RF FREQUENCY (MHz)
3rd HARMONIC (dBc)
2504506508501050
110
50
100
90
80
70
60
50
MAX2065 toc94
P
OUT
= 3dBm
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V
3rd HARMONIC
vs. DIGITAL ATTENUATOR STATE
DIGITAL ATTENUATOR STATE (dB)
3rd HARMONIC (dBc)
4812 16 20 24 28 32
90
70
85
80
75
0
MAX2065 toc95
TC = -40°C
P
OUT
= 0dBm
TC = +25°C, +85°C
VCC = 3.3V
RF = 200MHz
3rd HARMONIC
vs. ANALOG ATTENUATOR STATE
DAC CODE
3rd HARMONIC (dBc)
32 64 96 128 160 192 224 256
110
50
100
90
80
70
60
0
MAX2065 toc96
TC = -40°C
P
OUT
= 0dBm
TC = +85°C
TC = +25°C
VCC = 3.3V
RF = 200MHz
OIP2 vs. RF FREQUENCY
RF FREQUENCY (MHz)
OIP2 (dBm)
2504506508501050
70
30
60
50
40
50
MAX2065 toc97
TC = -40°C
P
OUT
= 0dBm/TONE
TC = +85°C
TC = +25°C
VCC = 3.3V
OIP2 vs. RF FREQUENCY
RF FREQUENCY (MHz)
OIP2 (dBm)
2504506508501050
70
30
60
50
40
50
MAX2065 toc98
P
OUT
= 0dBm/TONE
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V
OIP2 vs. DIGITAL ATTENUATOR STATE
DIGITAL ATTENUATOR STATE (dB)
OIP2 (dBm)
4812 16 20 24 28 32
70
30
60
50
40
0
MAX2065 toc99
TC = -40°C
TC = +25°C
P
OUT
= 0dBm/TONE
TC = +85°C
VCC = 3.3V
RF = 200MHz
OIP2 vs. ANALOG ATTENUATOR STATE
DAC CODE
OIP2 (dBm)
32 64 96 128 160 192 224 256
70
30
60
50
40
0
MAX2065 toc100
TC = -40°C
TC = +25°C
P
OUT
= -3dBm/TONE
TC = +85°C
VCC = 3.3V
RF = 200MHz
2nd HARMONIC
vs. ANALOG ATTENUATOR STATE
DAC CODE
2nd HARMONIC (dBc)
32 64 96 128 160 192 224 256
80
30
70
60
50
40
0
MAX2065 toc92
TC = -40°C
P
OUT
= 0dBm
TC = +85°C
TC = +25°C
VCC = 3.3V
RF = 200MHz
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
18RSETDriver Amplifier Bias-Setting. See the External Bias section.
20AMP_INDriver Amplifier Input (50Ω)
21VC C _AMPDriver Amplifier Supply Voltage Input
23ATTEN2_OUT5-Bit Digital Attenuator Output (50Ω)
29ATTEN2_IN5-Bit Digital Attenuator Input (50Ω)
32ATTEN1_OUTAnalog Attenuator Output (50Ω)
37ATTEN1_INAnalog Attenuator Input (50Ω)
38VC C _ANALOG Analog Bias and Control Supply Voltage Input
39AN ALOG_V C TRL Analog Attenuator Voltage Control Input
40VREF_INExternal DAC Voltage Reference Input
—EP
GNDGround
DAC Reference Voltage Selection Logic Input. Logic 1 = internal DAC reference voltage,
Log i c 0 = exter nal D AC r efer ence vol tag e. Log i c i np ut d i sab l ed ( d on’ t car e) w hen V D AC _E N = Log i c 0.
Digital Attenuator SPI or Parallel Control Selection Logic Input. Logic 0 = parallel control,
Logic 1 = serial control.
State AState BDigital Attenuator
Logic = 0Logic = 0Preprogrammed State 1
Logic = 1Logic = 0Preprogrammed State 2
Logic = 0Logic = 1Preprogrammed State 3
Logic = 1Logic = 1Preprogrammed State 4
E xp osed P ad . Inter nal l y connected to GN D . C onnect E P to GN D for p r op er RF p er for m ance and
enhanced ther m al d i ssi p ati on.
The MAX2065 high-linearity analog/digital variable-gain
amplifier is a general-purpose, high-performance
amplifier designed to interface with 50Ω systems operating in the 50MHz to 1000MHz frequency range.
The MAX2065 integrates one digital attenuator and one
analog attenuator to provide 62dB of total gain control,
as well as a driver amplifier optimized to provide high
gain, high IP3, low noise figure, and low power consumption. For applications that do not require high linearity, the
bias current of the amplifier can be adjusted by an external resistor to further reduce power consumption.
The digital attenuator is controlled as a slave peripheral
using either the SPI-compatible interface or a parallel
bus with 31dB total adjustment range in 1dB steps. An
added feature allows “rapid-fire” gain selection
between each of the four unique steps (preprogrammed by the user through the SPI-compatible interface). The 2-pin control allows the user to quickly
access any one of four customized attenuation states
without reprogramming the SPI bus. The analog attenuator is controlled using an external voltage or through
the SPI-compatible interface using an on-chip DAC.
Because each of the three stages has its own external
RF input and RF output, this component can be configured to either optimize NF (amplifier configured first),
OIP3 (amplifier last), or a compromise of NF and OIP3.
The device’s performance features include 22dB standalone amplifier gain (amplifier only), 6.5dB NF at maximum gain (includes attenuator insertion loss for both
attenuators), and a high OIP3 level of +42dBm. Each of
these features makes the MAX2065 an ideal VGA for
numerous receiver and transmitter applications.
In addition, the MAX2065 operates from a single +5V
supply, or a single +3.3V supply with slightly reduced
performance, and has adjustable bias to trade current
consumption for linearity performance.
Analog and 5-Bit Digital
Attenuator Control
The MAX2065 integrates one analog attenuator and
one 5-bit digital attenuator to achieve a high level of
dynamic range. The analog attenuator has a 31dB
range and is controlled using an external voltage or
through the 3-wire serial peripheral interface (SPI) using
an on-chip 8-bit DAC. The digital attenuator has a 31dB
control range, a 1dB step size, and is programmed
through the 3-wire SPI. See the
Applications Information
section and Table 1 for attenuator programming details.
The attenuators can be used for both static and dynamic power control.
Driver Amplifier
The MAX2065 includes a high-performance driver with
a fixed gain of 22dB. The driver amplifier circuit is optimized for high linearity for the 50MHz to 1000MHz frequency range.
Applications Information
SPI Interface and Attenuator Settings
The digital attenuator is programmed through the 3-wire
SPI/MICROWIRE™-compatible serial interface using
5-bit words. Twenty-eight bits of data are shifted in MSB
first and is framed by CS. When CS is low, the clock is
active and data is shifted on the rising edge of the
clock. When CS transitions high, the data is latched
and the attenuator setting changes (Figure 1). See
Table 2 for details on the SPI data format.
Table 1. Control Logic
X = Don’t care.
MICROWIRE is a trademark of National Semiconductor Corp.
VDAC_ENSER/PARVR EF _ SEL EC T
00X
101
01X
110
ATTENUATOR
Controlled by external
control voltage
Controlled by on-chip
DAC
Controlled by external
control voltage
Controlled by on-chip
DAC
ANALOG
DIGITAL
ATTENUATOR
Parallel controlledDisabled
Parallel controlled
SPI controlledDisabled
SPI controlled
D/A CONVERTER
Enabled (DAC uses onchip voltage reference)
Enabled (DAC uses
external voltage
reference)
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
The analog attenuator is controlled by an external control voltage applied at ANALOG_VCTRL (pin 39) or by
the on-chip 8-bit DAC, while the digital attenuator is controlled through the SPI-compatible interface or parallel
bus. The DAC enable/disable logic-input pin
(VDAC_EN), digital attenuator SPI or parallel control
selection logic-input pin (SER/PAR), and the DAC reference voltage selection logic-input pin (VREF_SELECT)
determine how the attenuators are controlled. The onchip DAC can also be enabled or disabled. When the
DAC is enabled, either the on-chip voltage reference or
the external voltage reference can be selected. See
Table 1 for the attenuator and DAC operation truth table.
Digital Attenuator Settings
Using the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the
MAX2065 offers a supplemental 5-bit parallel control
interface. The digital logic attenuator-control pins
(D0–D4) enable the attenuator stages (Table 3).
Direct access to this 5-bit bus enables the user to avoid
any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states needed for critical “fast-attack”
automatic gain control (AGC) applications.
“Rapid-Fire” Preprogrammed
Attenuation States
The MAX2065 has an added feature that provides
“rapid fire” gain selection between four preprogrammed attenuation steps. As with the supplemental
5-bit bus mentioned above, this “rapid fire” gain selection allows the user to quickly access any one of four
customized digital attenuation states without incurring
the delays associated with reprogramming the device
through the SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel bus. However, by
employing this specific feature, the digital attenuator
I/O is further reduced by a factor of either 5 or 2.5 (5
control bits vs. 1 or 2, respectively) depending on the
number of states desired.
Table 3. Digital Attenuator Settings (Parallel Control)
FUNCTIONBITDESCRIPTION
D7Bit 7 (MSB) of on-chip DAC used to program the analog attenuator
D6Bit 6 of DAC
D5Bit 5 of DAC
On-Chip DAC
D4Bit 4 of DAC
D3Bit 3 of DAC
D2Bit 2 of DAC
D1Bit 1 of DAC
D0 (LSB)Bit 0 (LSB) of the on-chip DAC
INPUTLOGIC = 0 (OR GROUND)LOGIC = 1
D0Disable 1dB attenuator, or when SPI is default programmerEnable 1dB attenuator
D1Disable 2dB attenuator, or when SPI is default programmerEnable 2dB attenuator
D2Disable 4dB attenuator, or when SPI is default programmerEnable 4dB attenuator
D3Disable 8dB attenuator, or when SPI is default programmerEnable 8dB attenuator
D4Disable 16dB attenuator, or when SPI is default programmerEnable 16dB attenuator
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
The user can employ the STATE_A and STATE_B logicinput pins to apply each step as required (Table 4).
Toggling just the STATE_A pin (one control bit) yields
two preprogrammed attenuation states; toggling both
the STATE_A and STATE_B pins together (two control
bits) yield four preprogrammed attenuation states.
As an example, assume that the AGC application
requires a static attenuation adjustment to trim out gain
inconsistencies within a receiver lineup. The same AGC
circuit can also be called upon to dynamically attenuate
an unwanted blocker signal that could de-sense the
receiver and lead to an ADC overdrive condition. In this
example, the MAX2065 would be preprogrammed
(through the SPI bus) with two customized attenuation
states—one to address the static gain trim adjustment,
the second to counter the unwanted blocker condition.
Toggling just the STATE_A control bit enables the user
to switch quickly between the static and dynamic attenuation settings with only one I/O pin.
If desired, the user can also program two additional
attenuation states by using the STATE_B control bit as
a second I/O pin. These two additional attenuation settings are useful for software-defined radio applications
where multiple static gain settings may be needed to
account for different frequencies of operation, or where
multiple dynamic attenuation settings are needed to
account for different blocker levels (as defined by multiple wireless standards).
Cascaded OIP3 Considerations
Due to both attenuator’s finite IP3 performance, the
cascaded OIP3 degrades when both attenuators are
set at higher attenuation states.
External Bias
Bias currents for the driver amplifier are set and optimized through external resistors. Resistors R1 and R1A
connected to RSET (pin 18) set the bias current for the
amplifier. The external biasing resistor values can be
increased for reduced current operation at the expense
of performance.
The MAX2065 features an optional +3.3V supply voltage
operation with slightly reduced linearity performance.
Layout Considerations
The pin configuration of the MAX2065 has been optimized to facilitate a very compact physical layout of the
device and its associated discrete components.
The exposed paddle (EP) of the MAX2065’s 40-pin thin
QFN-EP package provides a low thermal-resistance
path to the die. It is important that the PCB on which the
MAX2065 is mounted be designed to conduct heat
from the EP. In addition, provide the EP with a lowinductance path to electrical ground. The EP must be
soldered to a ground plane on the PCB, either directly
or through an array of plated via holes.
Amplitude Overshoot Reduction
To reduce amplitude overshoot during digital attenuator state change, connect a bandpass filter (parallel
LC type) from ATTEN2_OUT (pin 23) to ground. L =
18nH and C = 47pF are recommended for 169MHz
operation (Figure 2). Contact the factory for recommended components for other operating frequencies.
Figure 2. Bandpass Filter to Reduce Amplitude Overshoot
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
QFN THIN.EPS
MAX2065
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
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