The MAX2064 high-linearity, dual analog variable-gain
amplifier (VGA) operates in the 50MHz to 1000MHz frequency range. Each analog attenuator is controlled using
an external voltage, or through the SPI™-compatible
interface using an on-chip 8-bit DAC.
Since each of the stages has its own external RF
input and RF output, this component can be configured to either optimize noise figure (NF) (amplifier configured first) or OIP3 (amplifier last). The
device’s performance features include 24dB amplifier gain (amplifier only), 4.4dB NF at maximum gain
(includes attenuator insertion losses), and a high
OIP3 level of +41dBm. Each of these features makes
the device an ideal VGA for multipath receiver and
transmitter applications.
In addition, the device operates from a single +5V
supply with full performance, or a +3.3V supply for an
enhanced power-savings mode with lower performance.
The device is available in a compact 48-pin TQFN
package (7mm x 7mm) with an exposed pad. Electrical
performance is guaranteed over the extended temperature range, from T
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
ABSOLUTE MAXIMUM RATINGS
V
CC_AMP_1
PD_1, PD_2, AMPSET to GND .............................-0.3V to +3.6V
A_VCTL_1, A_VCTL_2 to GND .............................-0.3V to +3.6V
DAT, CS, CLK, AA_SP to GND ............................-0.3V to +3.6V
AMP_IN_1, AMP_IN_2 to GND ..........................+0.95V to +1.2V
AMP_OUT_1, AMP_OUT_2 to GND .....................-0.3V to +5.5V
A_ATT_IN_1, A_ATT_IN_2, A_ATT_OUT_1,
A_ATT_OUT_2 to GND ......................................... 0V to +3.6V
MAX2064
REG_OUT to GND ................................................-0.3V to +3.6V
RF Input Power (A_ATT_IN_1, A_ATT_IN_2) ................. +20dBm
Note 1: Based on junction temperature TJ = TC + (qJC x VCC x ICC). This formula can be used when the temperature of the
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
Note 3: Junction temperature T
Note 4: T
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
, V
CC_AMP_2
exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details.
The junction temperature must not exceed +150NC.
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
known. The junction temperature must not exceed +150NC.
is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
C
, V
to GND ..........-0.3V to +5.5V
CC_RG
= TA + (qJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is
J
RF Input Power (AMP_IN_1, AMP_IN_2) ....................... +18dBm
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (each path, unless otherwise noted)
(Typical Application Circuit, VCC = V
RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P f
values are at maximum gain setting, V
(Typical Application Circuit, VCC = V
RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P f
values are at maximum gain setting, V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Output -1dB Compression PointP
MAX2064
Second HarmonicP
Third HarmonicP
Group DelayIncludes EV kit PCB delays0.9ns
Amplifier Power-Down Time
Amplifier Power-Up Time
Input Return LossRL
Output Return LossRL
ANALOG ATTENUATOR (each path, unless otherwise noted)
Insertion LossIL2.2dB
Input Second-Order Intercept
Point
Input Third-Order Intercept PointIIP3
Attenuation Range32.9dB
Gain Control SlopeAnalog control input-13.3dB/V
Maximum Gain Control SlopeOver analog control input range-35.2dB/V
Insertion Phase ChangeOver analog control input range16.5Deg/V
Attenuator Response Time
Group Delay vs. Control Voltage
Analog Control Input Range0.252.75V
Analog Control Input Impedance19.2
Input Return Loss
Output Return Loss
(Typical Application Circuit, VCC = V
RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P f
values are at maximum gain setting, V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
D/A CONVERTER
Number of Bits8Bits
Output Voltage
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed20MHz
Data-to-Clock Setup Timet
Data-to-Clock Hold Timet
Clock-to-CS Setup Time
= +4.75V to +5.25V, attenuators are set for maximum gain,
CC_RG
P 500MHz, TC = -40NC to +85NC. Typical
RF
2ns
2.5ns
3ns
7ns
3.5ns
5ns
V
MAX2064
+3.3V SUPPLY AC ELECTRICAL CHARACTERISTICS (each path, unless otherwise noted)
(Typical Application Circuit, VCC = V
gain, RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, 100MHz P f
values are at maximum gain setting, V
5DATSPI Data Digital Input
6CLKSPI Clock Digital Input
7
8V
20A_ATT_IN_2
22A_VCTL_2
23A_ATT_OUT_2
24V
26AMP_IN_2
27PD_2Power-Down, Path 2. See Table 2 for operation details.
29AMP_OUT_2
GNDGround
CS
CC_RG
SPI Chip-Select Digital Input
Regulator Supply Input. Connect to a 3.3V or 5V external power supply. V
except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to the pin.
Analog Attenuator Input (50I), Path 2. Requires a 1000pF DC-blocking capacitor.
Analog Attenuator Voltage-Control Input, Path 2. Bypass to ground with a 150pF capacitor
if DAC 2 is used (AA_SP = 1).
Analog Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
CC_AMP_2
Driver Amplifier Supply-Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
Driver Amplifier Input (50I), Path 2. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_2 through a 1000pF capacitor.
Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to V
Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
Pin Description (continued)
PINNAMEFUNCTION
30REG_OUT
31AMPSET
32AMP_OUT_1
MAX2064
34PD_1Power-Down, Path 1. See Table 2 for operation details.
35AMP_IN_1
37V
38A_ATT_OUT_1
39A_VCTL_1
40AA_SP
41A_ATT_IN_1
—EP
CC_AMP_1
Regulator Output. Bypass with 1FF capacitor.
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V operation on pins
V
CC_AMP_1
Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to V
Driver Amplifier Input (50I), Path 1. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_1 through a 1000pF capacitor.
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
Analog Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
Analog Attenuator Voltage-Control Input, Path 1. Bypass to ground with a 150pF capacitor
if on-chip DAC is used (AA_SP = 1).
DAC Enable/Disable Logic Input for Analog Attenuators. Set AA_SP to logic 1 to enable on-chip
DAC circuit and digital SPI control. Set AA_SP to logic 0 to disable DAC circuit and digital SPI
control. When AA_SP = 0, use analog control lines (A_VCTL_1 and A_VCTL_2).
Analog Attenuator Input (50I), Path 1. Requires a 1000pF DC-blocking capacitor.
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper RF
performance and enhanced thermal dissipation.
and V
CC_AMP_2
. Set to logic 0 for 5V operation.
CC_.
Detailed Description
The MAX2064 high-linearity analog VGA is a general-purpose, high-performance amplifier designed to
interface with 50I systems operating in the 50MHz to
1000MHz frequency range.
Each channel of the device integrates an analog attenuator to provide 33dB of total gain control, as well as a driver
amplifier optimized to provide high gain, high IP3, low NF,
and low power consumption.
Each analog attenuator is controlled using an external
voltage or through the SPI-compatible interface using
an on-chip 8-bit DAC. See the Applications Information
section and Table 3 for attenuator programming details.
Because each of the two stages in the separate signal
paths has its own RF input and RF output, this component can be configured to either optimize NF (amplifier
configured first) or OIP3 (amplifier last). The device’s performance features include 24dB amplifier gain (amplifier
only), 4.4dB NF at maximum gain (includes attenuator
insertion losses), and a high OIP3 level of +41dBm. Each
of these features makes the device an ideal VGA for mul-
In addition, the device operates from a single +5V
supply with full performance, or a +3.3V supply for an
enhanced power-savings mode with lower performance.
The device is available in a compact 48-pin TQFN package (7mm x 7mm) with an exposed pad. Electrical performance is guaranteed over the extended temperature
range, from T
= -40NC to +85NC.
C
Analog Attenuator Control
The device integrates two analog attenuators. Each
analog attenuator has a 33dB range and is controlled
using an external voltage, or through the 3-wire SPI interface using an on-chip 8-bit DAC. See the Applications Information section and Table 3 for attenuator programming details. The attenuators can be used for both static
and dynamic power control.
Note that when the analog attenuators are controlled by the
DACs through the SPI bus, the DAC output voltage shows
on A_VCTL_1 and A_VCTL_2 (pins 39 and 22, respectively). Therefore, in SPI mode, the A_VCTL_1 and A_VCTL_2
pins must only connect to the resistor and capacitor to
ground, as shown in the Typical Application Circuit.
Enabled (DAC output voltage shows on A_VCTL__ pins);
DAC uses on-chip voltage reference
MAX2064
Table 2. Operating Modes
RESULTVCC (V)AMP_SETPD_1PD_2
All on
AMP1 off
AMP2 on
AMP1 on
AMP2 off
All off
Each path of the device includes a high-performance
driver with a fixed gain of 24dB. The driver amplifier
circuits are optimized for high linearity for the 50MHz to
1000MHz frequency range.
5000
3.3100
5010
3.3110
5001
3.3101
5011
3.3111
Driver Amplifier
MSBLSB
DAT
DND1D0D(N-1)
Applications Information
Operating Modes
The device features an optional +3.3V supply voltage operation with reduced linearity performance. The
AMPSET pin needs to be biased accordingly in each
mode, as listed in Table 2. In addition, the driver amplifiers
can be shut down independently to conserve DC power.
See the biasing scheme outlined in Table 2 for details.
SPI Interface and Attenuator Settings
The attenuators can be programmed through the 3-wire
SPI/MICROWIREK-compatible serial interface using
5-bit words. Fifty-six bits of data are shifted in MSB first
and are framed by CS. The first 28 bits set the first attenuator and the following 28 bits set the second attenuator.
When CS is low, the clock is active and data is shifted on
the rising edge of the clock. When CS transitions high,
the data is latched and the attenuator setting changes
(Figure 1). See Table 3 for details on the SPI data format.
CLK
t
CS
t
EWS
NOTES:
DATA ENTERED ON CLOCK RISING EDGE.
ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE.
N = NUMBER OF DATA BITS.
D0 IS AN ADDRESS BIT, D1/DN ARE DATA BITS (WHERE N P 20).
Figure 1. SPI Timing Diagram
MICROWIRE is a trademark of National Semiconductor Corp.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
Table 3. SPI Data Format
FUNCTIONBITDESCRIPTION
D55 (MSB)
D54
D53
D52
MAX2064
Reserved
On-Chip DAC
(Path 2)
D51
D50
D49
D48
D47
D46
D45
D44
D43
D42
D41
D40
D39
D38
D37
D36
D35Bit 7 (MSB) of on-chip DAC used to program the Path 2 analog attenuator
D34Bit 6 of DAC
D33Bit 5 of DAC
D32Bit 4 of DAC
D31Bit 3 of DAC
D30Bit 2 of DAC
D29Bit 1 of DAC
D28Bit 0 (LSB) of DAC
D9
D8
D7Bit 7 (MSB) of on-chip DAC used to program the Path 1 analog attenuator
D6Bit 6 of DAC
D5Bit 5 of DAC
D4Bit 4 of DAC
D3Bit 3 of DAC
D2Bit 2 of DAC
D1Bit 1 of DAC
Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
Power-Supply Sequencing
The sequence to be used is:
1) Power supply
2) Control lines
Layout Considerations
The pin configuration of the device is optimized to facilitate a very compact physical layout of the device and its
MAX2064
associated discrete components. The exposed pad (EP)
the PCB on which the device is mounted be designed
to conduct heat from the EP. In addition, provide the EP
with a low inductance path to electrical ground. The EP
MUST be soldered to a ground plane on the PCB, either
directly or through an array of plated via holes. The layout of the PCB should include proper top-layer ground
shielding to isolate the amplifier’s inputs and outputs
from each other. Shielding between the paths (inputs and
outputs) is important for channel-to-channel isolation.
of the device’s 48-pin TQFN-EP package provides a low
thermal-resistance path to the die. It is important that
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
48 TQFN-EPT4877+7
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
21-014490-0133
Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
Revision History
REVISION
NUMBER
012/10Initial release—
MAX2064
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600