The MAX2010 adjustable RF predistorter is designed to
improve power amplifier (PA) adjacent-channel power
rejection (ACPR) by introducing gain and phase expansion in a PA chain to compensate for the PA’s gain and
phase compression. With its +23dBm maximum input
power level and wide adjustable range, the MAX2010
can provide up to 12dB of ACPR improvement for
power amplifiers operating in the 500MHz to 1100MHz
frequency band. Higher frequencies of operation can
be achieved with this IC’s counterpart, the MAX2009.
The MAX2010 is unique in that it provides up to 6dB of
gain expansion and 21° of phase expansion as the input
power is increased. The amount of expansion is configurable through two independent sets of control: one set
adjusts the gain expansion breakpoint and slope, while
the second set controls the same parameters for phase.
With these settings in place, the linearization circuit can
be run in either a static set-and-forget mode, or a more
sophisticated closed-loop implementation can be
employed with real-time software-controlled distortion
correction. Hybrid correction modes are also possible
using simple lookup tables to compensate for factors
such as PA temperature drift or PA loading.
The MAX2010 comes in a 28-pin thin QFN exposed
pad (EP) package (5mm x 5mm) and is specified for
the extended (-40°C to +85°C) temperature range.
Applications
cdma2000™, GSM/EDGE, and iDEN Base Stations
Feed-Forward PA Architectures
Digital Baseband Predistortion Architectures
Military Applications
Features
♦ Up to 12dB ACPR Improvement*
♦ Independent Gain and Phase Expansion Controls
♦ Gain Expansion Up to 6dB
♦ Phase Expansion Up to 21°
♦ 500MHz to 1100MHz Frequency Range
♦ Exceptional Gain and Phase Flatness
♦ Group Delay <2.4ns (Gain and Phase Sections
Combined)
♦ ±0.03ns Group Delay Ripple Over a 100MHz Band
♦ Capable of Handling Input Drives Up to +23dBm
♦ On-Chip Temperature Variation Compensation
♦ Single +5V Supply
♦ Low Power Consumption: 75mW (typ)
♦ Fully Integrated into Small 28-Pin Thin QFN
Package
*Performance dependent on amplifier, bias, and modulation.
= +4.75V to +5.25V; no RF signal applied; INP, ING, OUTP, OUTG are AC-coupled and terminated to
50Ω. V
PF_S1
= open; PBEXP shorted to PBRAW; V
PDCS1
= V
PDCS2
= 0.8V; V
PBIN
= V
GBP
= V
GCS
= GND; V
GFS
= V
CCG;TA
= -40°C to
+85°C. Typical values are at V
CCG
= V
CCP
= +5.0V, TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CCG
, V
CCP
to GND ..............................................-0.3V to +5.5V
ING, OUTG, GCS, GFS, GBP to GND......-0.3V to (V
CCG
+ 0.3V)
INP, OUTP, PFS_, PDCS_, PBRAW,
PBEXP, PBIN to GND ............................-0.3V to (V
Note 1: Guaranteed by design and characterization.
Note 2: All limits reflect losses and characteristics of external components shown in the Typical Application Circuit, unless otherwise
noted.
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2010 EV kit, V
CCG
= V
CCP
= +4.75V to +5.25V, 50Ω environment, PIN= -20dBm, fIN= 500MHz to 1100MHz, V
The MAX2010 adjustable predistorter can provide up to
12dB of ACPR improvement for high-power amplifiers
by introducing gain and phase expansion to compensate for the PA’s gain and phase compression. The
MAX2010 enables real-time software-controlled distortion correction, as well as set-and-forget tuning through
the adjustment of the expansion starting point (breakpoint) and the rate of expansion (slope). The gain and
phase breakpoints can be set over a 20dB input power
range. The phase expansion slope is variable from
0.3°/dB to 2.0°/dB and can be adjusted for a maximum
of 21° of phase expansion. The gain expansion slope is
variable from 0.1dB/dB to 0.53dB/dB and can be
adjusted for a maximum of 6dB gain expansion.
The following sections describe the tuning methodology
best implemented with a class A amplifier. Other classes
of operation may require significantly different settings.
Pin Description
PINNAMEFUNCTION
1, 2, 4, 5, 7,
8, 10, 16, 20,
22, 26, 28
3ING
6OUTP
9INPRF Phase Input. Connect INP to a coupling capacitor. This pin is interchangeable with OUTP.
11PFS1Fine Phase-Slope Control Input 1. See the Typical Application Circuit.
12PFS2Fine Phase-Slope Control Input 2. See the Typical Application Circuit.
13PDCS1Digital Coarse Phase-Slope Control Range Input 1. Set to logical zero for the steepest slope.
14PDCS2Digital Coarse Phase-Slope Control Range Input 2. Set to logical zero for the steepest slope.
15V
17PBINPhase Breakpoint Control Input
18PBEXPPhase Expansion Output. Connect PBEXP to PBRAW to use PBIN as the breakpoint control voltage.
19PBRAWUncompensated Phase Breakpoint Input
21V
23GBPGain Breakpoint Control Input
GNDGround. Internally connected to the exposed paddle.
RF Gain Input. Connect ING to a coupling capacitor if it is not connected to OUTP. ING is
interchangeable with OUTG.
RF Phase Output. Connect OUTP to a coupling capacitor if it is not connected to INP. OUTP is
interchangeable with INP.
CCP
CCG
Phase-Control Supply Voltage. Bypass with a 0.01µF capacitor to ground as close to the device as
possible. Phase section can operate without V
Gain-Control Supply Voltage. Bypass with a 0.01µF capacitor to ground as close to the device as
possible. Gain section can operate without V
CCP
CCG
.
.
24GFSFine Gain-Slope Control Input
25GCSCoarse Gain-Slope Control Input
27OUTGRF Gain Output. Connect OUTG to a coupling capacitor. OUTG is interchangeable with ING.
EPGNDExposed Ground Paddle. Solder EP to the ground plane.
Figure 1 shows a typical PA’s phase behavior with
respect to input power. For input powers less than the
breakpoint level, the phase remains relatively constant.
As the input power becomes greater than the breakpoint level, the phase begins to compress and deteriorate the power amplifier’s linearity. To compensate for
this AM-PM distortion, the MAX2010 provides phase
expansion, which occurs at the same breakpoint level
but with the opposite slope. The overall result is a flat
phase response.
Phase Expansion Breakpoint
The phase expansion breakpoint is typically controlled
by a digital-to-analog converter (DAC) connected
through the PBIN pin. The PBIN input voltage range of
0V to VCCcorresponds to a breakpoint input power
range of 0.7dBm to 23dBm. To achieve optimal performance, the phase expansion breakpoint of the
MAX2010 must be set to equal the phase compression
breakpoint of the PA.
Phase Expansion Slope
The phase expansion slope of the MAX2010 must also
be adjusted to equal the opposite slope of the PA’s
phase compression curve. The phase expansion slope
of the MAX2010 is controlled by the PFS1, PFS2, PDCS1,
and PDCS2 pins. With pins PFS1 and PFS2 AC-coupled
and connected to a variable capacitor or varactor diode,
the PFS1 and PFS2 pins perform the task of fine tuning
the phase expansion slope. Since off-chip varactor
diodes are recommended for this function, they must
be closely matched and identically biased. A minimum
effective capacitance of 2pF to 6pF is required
to achieve the full phase slope range as specified in
the Electrical Characteristics tables.
As shown in Figure 2, the varactors connected to PFS1
and PFS2 are in series with three internal capacitors on
each pin. By connecting and disconnecting these internal capacitors, a larger change in phase expansion
slope can be achieved through the logic levels presented at the PDCS1 and PDCS2 pins. The phase expansion slope is at its maximum when both V
PDCS1
and
V
PDCS2
equal 0V. The phase tuning has a minimal
effect on the small-signal gain.
Gain Expansion Circuitry
In addition to phase compression, the PA also suffers
from gain compression (AM-AM) distortion, as shown in
Figure 3. The PA gain curve remains flat for input powers below the breakpoint level, and begins to compress
at a given rate (slope) for input powers greater than the
breakpoint level. To compensate for such gain compression, the MAX2010 generates a gain expansion,
which occurs at the same breakpoint level with the
opposite slope. The overall result is a flat gain response
at the PA output.
Figure 1. PA Phase Compression Canceled by MAX2010 Phase Expansion
The gain expansion breakpoint is usually controlled by
a DAC connected through the GBP pin. The GBP input
voltage range of 0.5V to 5V corresponds to a breakpoint input power range of -2.5dBm to 23dBm. To
achieve the optimal performance, the gain expansion
breakpoint of the MAX2010 must be set to equal the
gain compression point of the PA. The GBP control has
a minimal effect on the small-signal gain when operated from 0.5V to 5V.
Gain Expansion Slope
In addition to properly setting the breakpoint, the gain
expansion slope of the MAX2010 must also be adjusted
to compensate for the PA’s gain compression. The
slope should be set using the following equation:
where:
MAX2010_SLOPE = MAX2010 gain section’s slope in
dB/dB.
PA_SLOPE = PA’s gain slope in dB/dB, a negative
number for compressive behavior.
To modify the gain expansion slope, two adjustments
must be made to the biases applied on pins GCS and
GFS. Both GCS and GFS have an input voltage range of
0V to VCC, corresponding to a slope of approximately
0.1dB/dB to 0.53dB/dB. The slope is set to maximum
when V
GCS
= 0V and V
GFS
= +5V, and the slope is at its
minimum when V
GCS
= +5V and V
GFS
= 0V.
Unlike the GBP pin, modifying the gain expansion slope
bias on the GCS pin causes a change in the part’s insertion loss and noise figure. For example, a smaller slope
caused by GCS results in a better insertion loss and
lower noise figure. The GFS does not affect the insertion
loss. It can provide up to -30% or +30% total slope variation around the nominal slope set by GCS.
Large amounts of GCS bias adjustment can also lead to
an undesired (or residual) phase expansion/compression behavior. There exists an optimal bias voltage that
minimizes this parasitic behavior (typically GCS = 1.0V).
Control voltages higher than the optimal result in parasitic phase expansion, lower control voltages result in
phase compression. GFS does not contribute to the
phase behavior and is preferred for slope control.
Applications Information
The following section describes the tuning methodology
best implemented with a class A amplifier. Other classes
of operation may require significantly different settings.
Gain and Phase Expansion Optimization
The best approach to improve the ACPR of a PA is to
first optimize the AM-PM response of the phase section. For most high-frequency LDMOS amplifiers,
improving the AM-PM response provides the bulk of the
ACPR improvement. Figure 4 shows a typical configuration of the phase tuning circuit. A power sweep on a
network analyzer allows quick real-time tuning of the
AM-PM response. First, tune PBIN to achieve the phase
expansion starting point (breakpoint) at the same point
where the PA’s phase compression begins. Next, use
control pins PF_S1, PDCS1, and PDCS2 to obtain the
optimal AM-PM response. The typical values for these
pins are shown in Figure 4.
To further improve the ACPR, connect the phase output to the gain input through a preamplifier. The preamplifier is used to compensate for the high insertion
loss of the gain section. Figure 5 shows a typical application circuit of the MAX2010 with the phase section
cascaded to the gain section for further ACPR optimization. Similar to tuning the phase section, first tune
the gain expansion breakpoint through the GBP pin
and adjust for the desired gain expansion with pins
GCS and GFS. To minimize the effect of GCS on the
parasitic phase response, minimize the control voltage
to around 1V. Some retuning of the AM-PM response
may be necessary.
Layout Considerations
A properly designed PC board is an essential part of any
high-frequency circuit. In order to minimize external components, the PC board can be designed to incorporate
small values of inductance and capacitance to optimize
the input and output VSWR (refer to the MAX2009/
MAX2010 EV Kit). The phase section’s PFS1 and PFS2
pins are sensitive to external parasitics. Minimize trace
lengths and keep varactor diodes close to the pins.
Remove the ground plane underneath the traces can further help reduce the parasitic capacitance. For best performance, route the ground pin traces directly to the
grounded EP underneath the package. Solder the EP on
the bottom of the device package evenly to the board
ground plane to provide a heat transfer path along with
signal grounding.
The exposed paddle (EP) of the MAX2010’s 28-pin thin
QFN-EP package provides a low inductance path to
ground. It is important that the EP be soldered to the
ground plane on the PC board, either directly or
through an array of plated via holes.
Figure 4. AM-PM Response Tuning Circuit
Table 1. Suggested Components of
Typical Application Circuit
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
PIN # 1
I.D.
D
C
0.15 C A
D/2
0.15
C B
E/2
E
0.10
C
A
0.08 C
A3
A1
(NE-1) X e
DETAIL A
L
D2
C
k
e
(ND-1) X e
L
ee
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
L
D2/2
b
0.10 M
E2/2
L
DOCUMENT CONTROL NO.
21-0140
C A B
PIN # 1 I.D.
0.35x45
C
E2
L
k
QFN THIN.EPS
CC
L
L
REV.
1
C
2
COMMON DIMENSIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
EXPOSED PAD VARIATIONS
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
2
C
2
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