The MAX199 multi-range, 12-bit data-acquisition system
(DAS) requires only a single +5V supply for operation,
and converts analog signals up to ±4V at its inputs. This
system provides eight analog input channels that are
independently software programmable for a variety of
ranges: ±V
REF
, ±V
REF/2
, 0V to V
, or 0V to V
REF
REF/2
This increases effective dynamic range to 14 bits, and
provides the user flexibility to interface 4mA-to-20mA,
±12V, and ±15V powered sensors to a single +5V system. In addition, the converter is fault-protected to
±16.5V; a fault condition on any channel will not affect
the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, 100ksps
throughput rate, internal/external clock, internal/external
acquisition control, 8+4 parallel interface, and operation
with an internal 4.096V or external reference.
A hardware SHDN pin and two programmable powerdown modes (STBYPD, FULLPD) provide low-current
shutdown between conversions. In STBYPD mode, the
reference buffer remains active, eliminating start-up
delays.
The MAX199 employs a standard microprocessor (µP)
interface. Its three-state data I/O interface is configured
to operate with 8-bit data buses, and data-access and
bus-release timing specifications are compatible with
most popular µPs. All logic inputs and outputs are
TTL/CMOS compatible.
The MAX199 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.
For a different combination of input ranges (±10V, ±5V,
0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12bit bus interfaces, see the MAX196/MAX198 data sheet.
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
♦ 8 Analog Input Channels
♦ 6µs Conversion Time, 100ksps Sampling Rate
♦ Internal or External Acquisition Control
♦ Two Power-Down Modes
♦ Internal or External Clock
______________Ordering Information
PART
MAX199ACNI
MAX199BCNI
MAX199ACWI0°C to +70°C
MAX199BCWI0°C to +70°C28 Wide SO
MAX199ACAI0°C to +70°C28 SSOP
MAX199BCAI0°C to +70°C28 SSOP
MAX199BC/D0°C to +70°CDice*
Ordering Information continued at end of data sheet.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
= +70°C)
A
DD
DD
DD
DD
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T
ACCURACY (Note 1)
Offset Error
Channel-to-Channel Offset
Error Matching
Gain Error
(Note 2)
Gain Temperature Coefficient
(Note 2)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±4.096Vp-p, f
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
Output Low Voltage
Output High Voltage
Three-State Output Capacitance
= T
to T
A
MIN
, unless otherwise noted.)
MAX
DD
Normal mode, bipolar ranges
Normal mode, unipolar ranges
I
DD
Standby power-down (STBYPD)
Full power-down mode (FULLPD) (Note 7)
(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T
CS Pulse Width
WR Pulse Width
CS to WR Setup Time
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
CLK to WR Hold Time
Data Valid to WR Setup
Data Valid to WR Hold
RD Low to Output Data Valid
HBEN High or HBEN Low to
Output Valid
RD High to Output Disable
RD Low to INTHigh Delay
Note 1: Accuracy specifications tested at VDD= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Note 2: External reference: V
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale. V
Note 9: External acquisition timing: starts at rising edge of WR
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t
Note 12: t
Note 13: t
Rejection test. Tested for the ±4.096V input range.
ACQMOD = high.
and t
DO
or 2.4V.
is defined as the time required for the data lines to change by 0.5V.
TR
= T
to T
A
MIN
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V