Datasheet MAX199ACAI, MAX199BEAI, MAX199BCWI, MAX199BCNI, MAX199BCAI Datasheet (Maxim)

19-0401; Rev 0; 6/95

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

_______________General Description

The MAX199 multi-range, 12-bit data-acquisition system
(DAS) requires only a single +5V supply for operation,
and converts analog signals up to ±4V at its inputs. This
system provides eight analog input channels that are
independently software programmable for a variety of
ranges: ±V

REF

, ±V

REF/2

, 0V to V

, or 0V to V

REF

REF/2

This increases effective dynamic range to 14 bits, and
provides the user flexibility to interface 4mA-to-20mA,
±12V, and ±15V powered sensors to a single +5V sys­tem. In addition, the converter is fault-protected to
±16.5V; a fault condition on any channel will not affect
the conversion result of the selected channel. Other fea­tures include a 5MHz bandwidth track/hold, 100ksps
throughput rate, internal/external clock, internal/external
acquisition control, 8+4 parallel interface, and operation
with an internal 4.096V or external reference.

A hardware SHDN pin and two programmable power­down modes (STBYPD, FULLPD) provide low-current
shutdown between conversions. In STBYPD mode, the
reference buffer remains active, eliminating start-up
delays.

The MAX199 employs a standard microprocessor (µP)
interface. Its three-state data I/O interface is configured
to operate with 8-bit data buses, and data-access and
bus-release timing specifications are compatible with
most popular µPs. All logic inputs and outputs are
TTL/CMOS compatible.

The MAX199 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.

For a different combination of input ranges (±10V, ±5V,
0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12­bit bus interfaces, see the MAX196/MAX198 data sheet.

________________________Applications

Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications

Functional Diagram appears at end of data sheet.

____________________________Features

♦ 12-Bit Resolution, 1/2LSB Linearity
♦ Single +5V Operation
♦ Software-Selectable Input Ranges:

±V

, ±V

REF

♦ Internal 4.096V or External Reference

.

♦ Fault-Protected Input Multiplexer (±16.5V)

REF/2

, 0V to V

REF

, 0V to V

REF/2

♦ 8 Analog Input Channels
♦ 6µs Conversion Time, 100ksps Sampling Rate
♦ Internal or External Acquisition Control
♦ Two Power-Down Modes
♦ Internal or External Clock

______________Ordering Information

PART

MAX199ACNI
MAX199BCNI
MAX199ACWI 0°C to +70°C
MAX199BCWI 0°C to +70°C 28 Wide SO
MAX199ACAI 0°C to +70°C 28 SSOP
MAX199BCAI 0°C to +70°C 28 SSOP
MAX199BC/D 0°C to +70°C Dice*

Ordering Information continued at end of data sheet.

*Dice are specified at T

TEMP. RANGE PIN-PACKAGE

0°C to +70°C
0°C to +70°C

A

= +25°C, DC parameters only.

28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO

__________________Pin Configuration

TOP VIEW

CLK

1

CS

2

WR

3

RD

4

HBEN

5

SHDN

D7
D6
D5

D4
D3/D11
D2/D10

D1/D9
D0/D8

DIP/SO/SSOP/Ceramic SB

MAX199

6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

DGND
V

DD

REF
REFADJ
INT
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
AGND

MAX199

________________________________________________________________

Maxim Integrated Products

Call toll free 1-800-722-8266 for free samples or literature.

1

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

ABSOLUTE MAXIMUM RATINGS

VDDto AGND............................................................-0.3V to +7V

AGND to DGND.....................................................-0.3V to +0.3V

REF to AGND..............................................-0.3V to (V

REFADJ to AGND.......................................-0.3V to (V

Digital Inputs to DGND...............................-0.3V to (V

Digital Outputs to DGND............................-0.3V to (V

CH0–CH7 to AGND ..........................................................±16.5V

MAX199

Continuous Power Dissipation (T

Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

= +70°C)

A

DD
DD
DD
DD

+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T

ACCURACY (Note 1)

Offset Error

Channel-to-Channel Offset
Error Matching

Gain Error
(Note 2)

Gain Temperature Coefficient
(Note 2)

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±4.096Vp-p, f

Aperture Jitter

= T

to T

A

MIN

, unless otherwise noted.)

MAX

MAX199A

INLIntegral Nonlinearity

MAX199B

Unipolar

Bipolar
Unipolar

Bipolar
Unipolar

Bipolar
Unipolar

Bipolar

SINADSignal-to-Noise + Distortion Ratio

Up to the 5th harmonic

50kHz, VIN= ±4V (Note 3)
External CLK mode/external acquisition control
External CLK mode/external acquisition

control
Internal CLK mode/internal acquisition

control (Note 4)

Wide SO (derate 12.50mW/°C above +70°C)..............1000mW

SSOP (derate 9.52mW/°C above +70°C) ......................762mW

Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW

Operating Temperature Ranges

MAX199_C_ _ .......................................................0°C to +70°C

MAX199_E_ _.....................................................-40°C to +85°C

MAX199_M_ _..................................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

= 4.096V; 4.7µF at REF pin; external clock, f

REF

CONDITIONS

±1/2

±1

MAX199A
MAX199B
MAX199A
MAX199B

MAX199A
MAX199B
MAX199A
MAX199B

SAMPLE

MAX199A
MAX199B

±0.1
±0.5

= 100ksps)

70
69

±3
±5
±5

±10

±7

±10

±7

±10
3
5

10

CLK

= 2.0MHz

UNITSMIN TYP MAXSYMBOLPARAMETER

ppm/°C

Bits12Resolution
LSB
LSB±1DNLDifferential Nonlinearity

LSB

LSB

LSB

dB
dB-85 -78THDTotal Harmonic Distortion

dB80SFDRSpurious-Free Dynamic Range
dB-86Channel-to-Channel Crosstalk
ns15Aperture Delay

ps<50

ns

2 _______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T

ANALOG INPUT

Small-Signal Bandwidth

Input Voltage Range

Input Dynamic Resistance

INTERNAL REFERENCE

REF Output Voltage
REF Output Tempco

(

Contact Maxim Applications
for guaranteed temperature
drift specifications

Load Regulation

REFERENCE INPUT (Buffer disabled, reference input applied to REF pin)

Input Current V

Input Resistance

REFADJ Threshold for
Buffer Disable

= T

to T

A

MIN

)

, unless otherwise noted.)

MAX

f

= 2.0MHz

CLK

-3dB rolloff

Unipolar (see Table 2)

Bipolar (see Table 2)
Unipolar range
Bipolar
Unipolar

Bipolar
(Note 5)

TA= +25°C

REF

MAX199_C

TC V

MAX199_E ±30

REF

MAX199_M ±40

0mA to 0.5mA output current (Note 6) 7.5
0mA to 0.1mA output current (Note 6)

With recommended circuit (Figure 1) %±1.5REFADJ Adjustment Range

= 4.18V

REF

Normal, or STANDBY power-down mode kΩ10
FULL power-down mode 5 MΩ

REF

CONDITIONS

= 4.096V; 4.7µF at REF pin; external clock, f

±V

range

REF

±V

range

REF/2

0V to V
0V to V

±V

Normal, or STANDBY
power-down mode
FULL power-down
mode

REF
REF/2

REF
REF/2

range

range

range

range

-V

-V

REF/2

-1200 10±V

-600 10

5

2.5

2.5

1.25
0V
0V

REF

0.1 10

10

±15

0.8

V

V

CLK

REF

REF/2

REF

REF/2

400

1

MAX199

= 2.0MHz

UNITSMIN TYP MAXSYMBOLPARAMETER

µs3Track/Hold Acquisition Time

MHz

V

µAInput Current

MΩ40

kΩ
pF40Input Capacitance

V4.076 4.096 4.116V

ppm/°C

mA30Output Short-Circuit Current
mV

µF4.7Capacitive Bypass at REF

V2.465 2.500 2.535REFADJ Output Voltage

V/V1.6384Buffer Voltage Gain

V2.4 4.18Input Voltage Range

µA

VVDD- 50mV

_______________________________________________________________________________________ 3

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T

POWER REQUIREMENTS

Supply Voltage

MAX199

Supply Current

Power-Supply Rejection Ratio
(Note 8)

TIMING

Internal Clock Frequency
External Clock Frequency Range MHz

Acquisition Time

Conversion Time

Throughput Rate

Bandgap Reference
Start-Up Time

Reference Buffer Settling
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)

Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
Output Low Voltage
Output High Voltage
Three-State Output Capacitance

= T

to T

A

MIN

, unless otherwise noted.)

MAX

DD

Normal mode, bipolar ranges
Normal mode, unipolar ranges

I

DD

Standby power-down (STBYPD)
Full power-down mode (FULLPD) (Note 7)

PSRR

t

t

t

External reference = 4.096V
Internal reference ±1/

C

= 100pF MHz1.25 1.56 2.00f

CLK
CLK

ACQI

ACQE

CONV

INH

OUT

CLK

Internal acquisition
External acquisition (Note 9)

After FULLPD or STBYPD
External CLK
Internal CLK, C
External CLK
Internal CLK, C

Power-up (Note 10) µs200

To 0.1mV, REF
bypass capacitor
fully discharged

INL

VIN= 0V or V

IN

(Note 5) pF15C

IN

VDD= 4.75V, I

OL

VDD= 4.75V, I

OH

(Note 5) pF15C

CONDITIONS

CLK

CLK

DD

SINK
SOURCE

= 4.096V; 4.7µF at REF pin; external clock, f

REF

18

610

700 850

60 120

±1/

2

0.1 2.0f
External CLK
Internal CLK

= 100pF 6.0 7.7 10.0

= 100pF 62

C

= 4.7µF

REF

C

= 33µF

REF

= 1.6mA V0.4V

= 1mA VVDD- 1V

3.0

3.0 5.0

3.0

5

6.0

100

8

60

CLK

2

= 2.0MHz

UNITSMIN TYP MAXSYMBOLPARAMETER

V4.75 5.25V

mA

µA

LSB

µs

µs

ksps

ms

V2.4V
V0.8V

µA±10I

4 _______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

TIMING CHARACTERISTICS

(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T

CS Pulse Width
WR Pulse Width
CS to WR Setup Time
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
CLK to WR Hold Time
Data Valid to WR Setup
Data Valid to WR Hold
RD Low to Output Data Valid

HBEN High or HBEN Low to
Output Valid

RD High to Output Disable
RD Low to INTHigh Delay

Note 1: Accuracy specifications tested at VDD= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Note 2: External reference: V

Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale. V
Note 9: External acquisition timing: starts at rising edge of WR

Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t
Note 12: t

Note 13: t

Rejection test. Tested for the ±4.096V input range.

ACQMOD = high.

and t

DO

or 2.4V.

is defined as the time required for the data lines to change by 0.5V.

TR

= T

to T

A

MIN

are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V

DO1

, unless otherwise noted.)

MAX

CONDITIONS

CS

WR

CSWS

CSWH

CSRS
CSRH

CWS
CWH

DS
DH

Figure 2, CL= 100pF (Note 12)

DO

Figure 2, CL= 100pF (Note 12)

DO1

(Note 13) ns

t

TR

INT1

= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.

REF

= 4.75V to 5.25V.

DD

= tF= 5ns from a voltage level of 0.8V to 2.4V.

R

= 4.096V; 4.7µF at REF pin; external clock, f

REF

with control bit ACQMOD = low; ends at rising edge of WR with

CLK

70

= 2.0MHz

UNITSMIN TYP MAXSYMBOLPARAMETER

ns80t
ns80t
ns0t
ns0t
ns0t
ns0t
ns100t
ns50t
ns60t
ns0t
ns120t

ns120t

ns120t

MAX199

_______________________________________________________________________________________ 5

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITY

0.250

0.200

MAX199

0.150

0.100

0.050
0

-0.050

INTEGRAL NONLINEARITY (LSB)

-0.100

-0.150
0 1000 3000

vs. DIGITAL CODE

0

MAX199-1

-20

-40

-60

AMPLITUDE (dB)

-80

-100

2000 4000

DIGITAL CODE

-120

REFERENCE OUTPUT VOLTAGE (V

vs. TEMPERATURE

4.100

4.095

(V)

4.090

REF

V

= 1.6384

A

V

4.085

4.080

-55

-35 45

+2.5V

INTERNAL

REFERENCE

525 65

-15
TEMPERATURE (°C)

REFADJ

85

CHANNEL-TO-CHANNEL

OFFSET-ERROR MATCHING vs. TEMPERATURE

0.20


0.18

0.16

0.14

CHANNEL-TO-CHANNEL

0.12

OFFSET-ERROR MATCHING (LSB)

0.10

-70 -50 50 110

-30 -10 10 30 70 90
TEMPERATURE (°C)

FFT PLOT



05025

)

REF

REF

105 125



FREQUENCY (kHz)

MAX199-4



MAX199-6

130





12.0

= 100kHz

MAX199-2

11.5

11.0

10.5

EFFECTIVE NUMBER OF BITS

10.0

f

TONE

f

SAMPLE

= 10kHz

POWER-SUPPLY REJECTION RATIO

vs. TEMPERATURE

0.4



120Hz

0.2

0

100Hz

-0.2

PSRR (LSB)

-0.4

-0.6

-70 -50

-30 -10 10 30 70 90
TEMPERATURE (°C)

CHANNEL-TO-CHANNEL

GAIN-ERROR MATCHING vs. TEMPERATURE

0.33

0.32

0.31

0.30

0.29

CHANNEL-TO-CHANNEL

GAIN-ERROR MATCHING (LSB)

0.28

0.27

-70 -50 50 110

-30 -10 10 30 70 90
TEMPERATURE (°C)

EFFECTIVE NUMBER OF BITS

vs. INPUT FREQUENCY

f

= 100kHz

SAMPLE

1 10 100

INPUT FREQUENCY (kHz)

V

= 5V ±0.25V

DD

MAX199-5



110

50

130

130



MAX199-7



MAX199-3

6 _______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

______________________________________________________________Pin Description

PIN

27

Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,

CLK1

place a capacitor (C
with C

CLK

= 100pF.

) from this pin to ground to set the internal clock frequency; f

CLK

Chip Select, active low.CS2
When CS is low, in the internal acquisition mode, a rising edge on WRlatches in configuration data and starts an

WR3

acquisition plus a conversion cycle. When CSis low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WRends acquisition and starts a conversion cycle.

When CS is low, a falling edge on RD will enable a read operation on the data bus.RD4

HBEN5

Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.

Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.SHDN6
Three-State Digital I/OD7–D47–10
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).D3/D1111
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).D2/D1012
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).D1/D913
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.D0/D814
Analog GroundAGND15
Analog Input ChannelsCH0–CH716–23
INT goes low when conversion is complete and output data is ready.INT24

REFADJ25

Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to VDDwhen using an external reference at the REF pin.

Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a

REF26

4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.

+5V Supply. Bypass with 0.1µF capacitor to AGND.V

DD

Digital GroundDGND28

FUNCTIONNAME

= 1.56MHz typical

CLK

MAX199

+5V

100k

24k

510k

0.01µF

Figure 1. Reference-Adjust Circuit

_______________________________________________________________________________________ 7

REFADJ

MAX199

D

OUT

and VOL to V

C

LOAD

OH

b) High-Z to VOL and VOH to V

3k

a) High-Z to V

OH

Figure 2. Load Circuits for Enable Time

+5V

3k

D

OUT

C

LOAD

OL

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

_______________Detailed Description

The MAX199, a multi-range, fault-tolerant ADC, uses
successive approximation and internal input track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. The parallel-output format provides easy
interface to microprocessors (µPs). Figure 3 shows the

MAX199

MAX199 in its simplest operational configuration.

In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris­ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo­lar mode, a low-impedance input source, which settles
in less than 1.5µs, is required to maintain conversion
accuracy at the maximum conversion rate.

When configured for unipolar mode, the input does not
need to be driven from a low-impedance source. The
acquisition time (tAZ) is a function of the source output
resistance (RS), the channel input resistance (RIN), and
the T/H capacitance.

Acquisition time is calculated by:

For 0V to V
For 0V to V

µP

CONTROL

INPUTS

µP DATA BUS

Figure 3. Operational Diagram

: tAZ= 9 x (RS+ RIN) x 16pF

REF

: tAZ= 9 x (RS+ RIN) x 32pF

REF/2

1

CLK

100pF

2

CS

3

WR

4

RD

5

HBEN

6

SHDN

7

D7

8

D6

9

D5

10

D4

11

D3/D11

12

D2/D10

13

D1/D9

14

D0/D8

Converter Operation

Analog-Input Track/Hold

28

DGND

V

REF

REFADJ

CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0

AGND

27

DD

26
25

0.1µF

24

INT

23
22
21
20
19
18
17
16

15

OUTPUT STATUS

MAX199

ANALOG

INPUTS

+5V

+4.096V

4.7µF

where RIN= 7kΩ, and tAZis never less than 2µs (0V to
V

range) or 3µs (0V to V

REF

REF/2

range).

In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second WR
rising edge with D5 = 0. See the

External Acquisition

section.

Input Bandwidth

The ADC’s input tracking circuitry has a 5MHz small­signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre­quency band of interest, anti-alias filtering is recom­mended (MAX274/MAX275 continuous-time filters).

Input Range and Protection

Figure 4 shows the equivalent input circuit. The MAX199
can be programmed for input ranges of ±V
0V to V

, or 0V to V

REF

by setting the appropriate

REF/2

REF

, ±V

REF/2

control bits (D3, D4) in the control byte (see Tables 1 and

2). When an external reference is applied at REFADJ, the
voltage at REF is given by V
< V

< 4.18V).

REF

S1

5.12k

5.12k

CH_

S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH

Figure 4. Equivalent Input Circuit

S2

REF

BIPOLAR

UNIPOLAR

OFF

ON

= 1.6384 x V

C

HOLD

S3

TRACKHOLD

REFADJ

VOLTAGE
REFERENCE

S4

T/H
OUT

(2.4V

HOLDTRACK

,

8 _______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.

Even with VDD= 0V, the input resistive network provides
current-limiting that adequately protects the device.

Digital Interface

Input data (control byte) and output data are multiplexed
on a three-state parallel interface. This parallel I/O can
easily be interfaced with a µP. CS, WR, and RD control
the write and read operations. CS is the standard chip­select signal, which enables a µP to address the MAX199
as an I/O port. When high, it disables the WR and RD
inputs and forces the interface into a high-Z state.

The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 1 shows the control­byte format.

The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When read­ing the output data, CS and RD must be low. When
HBEN is low, the lower eight bits are read. When HBEN
is high, the upper four MSBs are available and the out­put data bits D4–D7 are either set low (in unipolar
mode) or set to the value of the MSB (in bipolar mode)
(Table 5).

Input Format

Output Data Format

Table 1. Control-Byte Format

D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)

PD1 PD0 ACQMOD RNG BIP A2 A1 A0

BIT NAME DESCRIPTION

7, 6 PD1, PD0 These two bits select the clock and power-down modes (Table 3).

5 ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
4 RNG Selects the full-scale voltage magnitude at the input (Table 2).
3 BIP Selects unipolar or bipolar conversion mode (Table 2).

2, 1, 0 A2, A1, A0 These are address bits for the input mux to select the “on” channel (Table 4).

Table 2. Range and Polarity Selection

BIP RNG INPUT RANGE (V)

0 0 0 to V
0 1 0 to V
1 0 ±V
1 1 ±V

REF/2

REF

REF/2

REF

Table 3. Clock and Power-Down Selection

PD1 PD0 DEVICE MODE

0 0 Normal Operation / External Clock Mode
0 1 Normal Operation / Internal Clock Mode

1 0

1 1

Standby Power-Down (STBYPD); clock mode
is unaffected

Full Power-Down (FULLPD); clock mode is
unaffected

MAX199

Table 4. Channel Selection

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

_______________________________________________________________________________________ 9

∗

∗

∗

∗

∗

∗

∗

∗

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

Table 5. Data-Bus Output

PIN HBEN = LOW HBEN = HIGH

D0 B0 (LSB) B8
D1 B1 B9
D2 B2 B10
D3 B3 B11 (MSB)

MAX199

D4 B4 B11 (BIP = 1) / 0 (BIP = 0)
D5 B5 B11 (BIP = 1) / 0 (BIP = 0)
D6 B6 B11 (BIP = 1) / 0 (BIP = 0)
D7 B7 B11 (BIP = 1) / 0 (BIP = 0)

Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX199 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.

CS

WR

D7–D0

INT

How to Start a Conversion

t

CS

t

CONTROL

BYTE

ACQMOD ="0"

ACQI

t

CSWS

t

WR

t

DS



t

t

DH

CSWH

t

CONV

Writing a new control byte during the conversion cycle
will abort the conversion in progress and start a new
acquisition interval.

Internal Acquisition

Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3µs with
f

= 2MHz) ends. See Figure 5.

CLK

External Acquisition

Use the external acquisition timing mode for precise con­trol of the sampling aperture and/or independent control of
acquisition and conversion times. The user controls acqui­sition and start-of-conversion with two separate write puls­es. The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates acquisi­tion and starts conversion on WR’s rising edge (Figure 6).
However, if the second control byte contains ACQMOD =
1, an indefinite acquisition interval is restarted.

The address bits for the input mux must have the same
values on the first and second write pulses. Power­down mode bits (PD0, PD1) can assume new values on
the second write pulse (see

t

CSRS

t

INT1

Power-Down Mode

t

CSRH

).

RD

HBEN

t

D0

DOUT

Figure 5. Conversion Timing Using Internal Acquisition Mode

10 ______________________________________________________________________________________

HIGH / LOW
BYTE VALID

t

D01

HIGH / LOW
BYTE VALID

t

TR

HIGH-ZHIGH-Z

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

t

CS

CS

WR

D7–D0

INT

RD

HBEN

DOUT

t

CSWS

t

DS

ACQMOD = "1"

t

WR

CONTROL

BYTE

t

ACQI

t

CSHW

t

DH

CONTROL

BYTE

ACQMOD = "0"

HIGH-Z HIGH-Z

Figure 6. Conversion Timing Using External Acquisition Mode

t

CONV

t

CSRS

t

INT1

t

HIGH / LOW

BYTE VALID

D01

HIGH / LOW
BYTE VALID

t

D0

t

CSRH

t

TR

MAX199



A standard interrupt signal, INT, is provided to allow the

How to Read a Conversion

device to flag the µP when the conversion has ended
and a valid result is available. INT goes low when the
conversion is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.

Clock Modes

The MAX199 operates with either an internal or an
external clock. Control bits (D6, D7) select either inter­nal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, the MAX199 defaults to external clock mode.

Internal Clock Mode

Select internal clock mode to free the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7

______________________________________________________________________________________ 11

shows a linear relationship between the internal clock
period and the value of the external capacitor used.

2000

1500

1000

500

INTERNAL CLOCK PERIOD (ns)

0

0 50 250 350

100 150 200 300

CLOCK PIN CAPACITANCE (pF)

Figure 7. Internal Clock Period vs. Clock Pin Capacitance

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

Select external clock mode by writing the control byte

External Clock Mode

with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz

MAX199

CLK

WR

ACQMOD = "0"

t

CWH

CLK

WR

ACQMOD = "0"

Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)

ACQUISITION STARTS

t

CWS

ACQUISITION STARTS

ACQUISITION STARTS

WR GOES HIGH WHEN CLK IS HIGH

WR GOES HIGH WHEN CLK IS LOW

external clock with 45% to 55% duty cycle is required
for proper operation. Operating at clock frequencies
lower than 100kHz will cause a voltage droop across
the hold capacitor, and subsequently degrade perfor­mance.

ACQUISITION ENDS

ACQUISITION ENDS

ACQUISITION ENDS

CONVERSION STARTS

CONVERSION STARTS

CONVERSION STARTS

CLK

t

CWS

ACQMOD = "0"

ACQMOD = "0"

CLK

t

DH

WR

ACQMOD = "1"

ACQUISITION STARTS

t

DH

WR

ACQMOD = "1"

WR GOES HIGH WHEN CLK IS HIGH

ACQUISITION ENDS

WR GOES HIGH WHEN CLK IS LOW

t

CWH

Figure 8b. External Clock and WR Timing (External Acquisition Mode)

12 ______________________________________________________________________________________

CONVERSION STARTS

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

__________Applications Information

Power-On Reset

At power-up, the internal power-supply circuitry sets INT
high and puts the device in normal operation / external
clock mode. This state is selected to keep the internal
clock from loading the external clock driver when the
part is used in external clock mode.

Internal or External Reference

The MAX199 can operate with either an internal or external
reference. An external reference can be connected to
either the REF pin or to the REFADJ pin (Figure 9).

To use the REF input directly, disable the internal buffer
by tying REFADJ to VDD. Using the REFADJ input elimi­nates the need to buffer the reference externally.
When the reference is applied at REFADJ, bypass
REFADJ with a 0.01µF capacitor to AGND.

The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at the REF pin from a 2.5V reference.

Internal Reference

The internally trimmed 2.50V reference is gained
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.

External Reference

At REF and REFADJ, the input impedance is a mini­mum of 10kΩ for DC currents. During conversions, an

external reference at REF must be able to deliver
400µA DC load currents, and must have an output
impedance of 10Ω or less. If the reference has higher
input impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor to AGND.

With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, the
increase in the ratio of the RMS noise to the LSB value
(FS / 4096) results in performance degradation (loss of
effective bits).

26

MAX199

A

= 1.638

V

10k

2.5V

Figure 9b. External Reference at REF

REF

25REFADJ

4.7µF
C

REF

V

4.096V

DD

MAX199

MAX199

A

= 1.638

V

10k

2.5V

Figure 9a. Internal Reference

______________________________________________________________________________________ 13

REF

26 4.096V

25REFADJ

4.7µF
C

REF

0.01µF

REF

26 4.096V

MAX199

A

= 1.638

V

10k

2.5V

Figure 9c. The external reference at REFADJ overdrives the
internal reference.

4.7µF
C

REF

25REFADJ

2.5V

0.01µF

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

To save power, you can put the converter into low-

Power-Down Mode

current shutdown mode between conversions. Two
programmable power-down modes are available, in
addition to a hardware shutdown. Select STBYPD or
FULLPD by programming PD0 and PD1 in the input
control byte. When software power-down is asserted, it
becomes effective only after the end of conversion. In all

MAX199

power-down modes, the interface remains active and
conversion results may be read. Input overvoltage pro­tection is active in all power-down modes. The device
returns to normal operation on the first WR falling edge
during a write operation.

For hardware-controlled (FULLPD) power-down, pull
the SHDN pin low. When hardware shutdown is assert­ed, it becomes effective immediately and the conver­sion is aborted.

Choosing Power-Down Modes

The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the

4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with this
mode, without regard to start-up delays.

OUTPUT CODE

11... 111

11... 110

11... 101

FULL-SCALE

TRANSITION

1 LSB =

FS

4096

However, in FULLPD mode, only the bandgap refer­ence is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversion and to reduce transients when the buffer is
enabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows a
conversion to begin immediately after power-down
ends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (less
than a fraction of an LSB), run a STBYPD power-down
cycle prior to starting conversions. Take into account
that the reference buffer recharges the bypass capaci­tor at an 80mV/ms slew rate and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
currents of 470µA, using the recommended 33µF
capacitor value.

Auto-Shutdown

Selecting STBYPD on every conversion automatically
shuts the MAX199 down after each conversion without
requiring any start-up time on the next conversion.

OUTPUT CODE

011... 111

011... 110

1 LSB =

2FS

4096

000... 001

000... 000

111... 111


00... 011

00... 010

00... 001

00... 000
0

123

INPUT VOLTAGE (LSB)

Figure 10. Unipolar Transfer Function

14 ______________________________________________________________________________________

FS

FS - 3/2 LSB

100... 010

100... 001

100... 000

-FS

Figure 11. Bipolar Transfer Function

0V +FS - 1 LSB

INPUT VOLTAGE (LSB)

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

Output data coding for the MAX199 is binary in unipolar

Transfer Function

mode with 1LSB = (FS / 4096) and twos-complement
binary in bipolar mode with 1LSB = [(2 x |FS|) / 4096].
Code transitions occur halfway between successive­integer LSB values. Figures 10 and 11 show the
input/output (I/O) transfer functions for unipolar and
bipolar operations, respectively.

Layout, Grounding, and Bypassing

Careful printed circuit board layout is essential for best
system performance. For best performance, use a
ground plane. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Digital
ground lines can run between digital signal lines to
minimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possi­ble. Connect the logic grounds directly to the supply
ground. Bypass VDDwith 0.1µF and 4.7µF capacitors
to AGND to minimize high- and low-frequency fluctua­tions. If the supply is excessively noisy, connect a 5Ω
resistor between the supply and VDD, as shown in
Figure 12.

SUPPLY

+5V

DIGITAL

CIRCUITRY

GND

DGND

+5V

R* = 5Ω



* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE

4.7µF

0.1µF

V

DD

**

DGNDAGND

MAX199

_Ordering Information (continued)

PIN-PACKAGETEMP. RANGEPART

MAX199AENI
MAX199BENI

**

Contact factory for availability and processing to MIL-STD-883.

-40°C to +85°C

-40°C to +85°CMAX199AEWI

28 Narrow Plastic DIP-40°C to +85°C
28 Narrow Plastic DIP
28 Wide SO
28 Wide SO-40°C to +85°CMAX199BEWI
28 SSOP-40°C to +85°CMAX199AEAI
28 SSOP-40°C to +85°CMAX199BEAI
28 Narrow Ceramic SB**-55°C to +125°CMAX199AMYI
28 Narrow Ceramic SB**-55°C to +125°CMAX199BMYI

___________________Chip Topography

V

V

CLKWR

CS

RD

HBEN
SHDN

D7

D6
D5

D4

D3

D2

0.144"

(3.659mm)

TRANSISTOR COUNT: 2956
SUBSTRATE CONNECTED TO GND

DD

CH0

CC

REFDGND

REFADJ
INT

CH7

0.231"

(5.870mm)

CH6

CH5

CH4
CH3
CH2

CH1D0D1AGND

MAX199

Figure 12. Power-Supply Grounding Connection

______________________________________________________________________________________ 15

Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface

_________________________________________________________Functional Diagram

REF REFADJ

CH7

MAX199

CH6
CH5
CH4
CH3
CH2
CH1
CH0

CLK

CS

WR

RD

SHDN

INT

SIGNAL

CONDITIONING

BLOCK

OVERVOLTAGE

TOLERANT

MUX

CLOCK

&

CONTROL LOGIC

LATCHES

AV = 

1.638

T/H

CHARGE REDISTRIBUTION

12-BIT DAC

12

SUCCESSIVE-

APPROXIMATION

REGISTER

4

&

8

THREE-STATE, BIDIRECTIONAL

4

I/O INTERFACE

8-BIT DATA BUS

8
8

MUX

8

D0–D7

10k

COMP

MAX199

+2.5V

REFERENCE

HBEN

V

DD

AGND
DGND

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

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© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.