The MAX196/MAX198 multirange, 12-bit data-acquisition systems (DAS) require only a single +5V supply for
operation, yet convert analog signals at their inputs up
to ±10V (MAX196) and ±4V (MAX198). These systems
provide six analog input channels that are independently software programmable for a variety of ranges:
±10V, ±5V, 0V to +10V, and 0V to +5V for the MAX196;
±V
, ±V
REF
/2, 0V to +V
REF
, and 0V to +V
REF
REF
/2 for
the MAX198. This range switching increases the effective dynamic range to 14 bits and provides the flexibility
to interface ±12V, ±15V, and 4mA to 20mA powered
sensors to a single +5V system. In addition, these converters are fault protected to ±16.5V; a fault condition
on any channel will not affect the conversion result of
the selected channel. Other features include a 5MHz
bandwidth track/hold, 100ksps throughput rate, software-selectable internal/external clock, internal/external
acquisition control, 12-bit parallel interface, and internal
4.096V or external reference.
Two programmable power-down modes (STBYPD,
FULLPD) provide low-current shutdown between conversions. In STBYPD mode, the reference buffer
remains active, eliminating start-up delays.
The MAX196/MAX198 employ a standard microprocessor (µP) interface. A three-state data I/O port is configured to operate with 16-bit data buses, and dataaccess and bus-release timing specifications are compatible with most popular µPs. All logic inputs and outputs are TTL/CMOS compatible.
These devices are available in 28-pin DIP, wide SO,
SSOP (55% smaller in area than wide SO), and ceramic
SB packages. For 8+4 bus interface, see the MAX197
and the MAX199 data sheets. An evaluation kit will be
available after December 1995 (MAX196EVKIT-DIP).
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
= +70°C)
A
DD
DD
DD
DD
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T
MAX196/MAX198
ACCURACY (Note 1)
Offset Error
Channel-to-Channel Offset
Error Matching
Gain Error
(Note 2)
Gain Temperature Coefficient
(Note 2)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX196) or ±4.096Vp-p (MAX198), f
= T
to T
A
MIN
; unless otherwise noted. Typical values are at TA= +25°C.)
MAX
MAX196A/MAX198A
INLIntegral Nonlinearity
MAX196B/MAX198B
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
SINADSignal-to-Noise + Distortion Ratio
MAX196A/MAX198A
MAX196B/MAX198B69
Up to the 5th harmonic
(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS
DIGITAL OUTPUTS (D11–D0, INT)
Output Low VoltageV
Output High VoltageV
Three-State Output CapacitanceC
= T
to T
A
MIN
; unless otherwise noted. Typical values are at TA= +25°C.)
MAX
OL
OH
OUT
SINK
SOURCE
= 4.096V; 4.7µF at REF pin; external clock, f
REF
= 1.6mA
= 1mA
VDD- 1VVDD= 4.75V, I
CLK
0.4VVDD= 4.75V, I
15pF(Note 5)
= 2.0MHz
TIMING CHARACTERISTICS
(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, V
with 50% duty cycle; T
PARAMETERSYMBOLMINTYPMAXUNITS
CS Pulse Widtht
WR Pulse Widtht
CS to WR Setup Time
CS to WR Hold Timet
CS to RD Setup Time
CS to RD Hold Timet
CLK to WR Setup Time
CLK to WR Hold Timet
Data Valid to WR Setup
Data Valid to WR Holdt
RD Low to Output Data Valid
RD High to Output Disable
RD Low to INT High Delay
Note 1: Accuracy specifications tested at VDD= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Note 2: External reference: V
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale.
Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t
Note 12: t
Note 13: t
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
= high control byte.
is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
DO
is defined as the time required for the data lines to change by 0.5V.