Maxim MAX195AMDE, MAX195BMDE, MAX195BEWE, MAX195BEPE, MAX195BC-D Datasheet
...
_______________General Description
The MAX195 is a 16-bit successive-approximation analog-to-digital converter (ADC) that combines high
speed, high accuracy, low power consumption, and a
10µA shutdown mode. Internal calibration circuitry corrects linearity and offset errors to maintain the full rated
performance over the operating temperature range without external adjustments. The capacitive-DAC architecture provides an inherent 85ksps track/hold function.
The MAX195, with an external reference (up to +5V),
offers a unipolar (0V to V
REF
) or bipolar (-V
REF
to V
REF
)
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
The chip select (CS) input controls the three-state serialdata output. The output can be read either during conversion as the bits are determined, or following conversion at
up to 5Mbps using the serial clock (SCLK). The end-ofconversion (EOC) output can be used to interrupt a
processor, or can be connected directly to the convert
input (CONV) for continuous, full-speed conversions.
The MAX195 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages.
________________________Applications
Portable Instruments
Audio
Industrial Controls
Robotics
Multiple Transducer Measurements
Medical Signal Acquisition
Vibrations Analysis
Digital Signal Processing
____________________________Features
♦ 16 Bits, No Missing Codes
♦ 90dB SINAD
♦ 9.4µs Conversion Time
♦ 10µA (max) Shutdown Mode
♦ Built-In Track/Hold
♦ AC and DC Specified
♦ Unipolar (0V to V
REF
) and Bipolar (-V
REF
to V
REF
)
Input Range
♦ Three-State Serial-Data Output
♦ Small 16-Pin DIP, SO, and Ceramic SB Packages
______________Ordering Information
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDDA
VSSA
AGND
AIN
VDDD
SCLK
CLK
BP/UP/SHDN
TOP VIEW
MAX195
REF
VSSD
RESET
CONV
CS
EOC
DGND
DOUT
DIP/Wide SO/Ceramic SB
MAX195
AIN
REF
CONV
SCLK
CLK
BP/UP/SHDN
CS
RESET
VSSD
DGND
VDDD
VDDA
AGND
VSSA
DOUT
EOC
SAR
CONTROL LOGIC
COMPARATOR
CALIBRATION
DACs
THREE-STATE BUFFER
4
6
11
16
14
15
5
7
10
8
1
9
3
2
13
12
MAIN DAC
Σ
________________Functional Diagram
__________________Pin Configuration
19-0377; Rev 1; 12/97
PART
MAX195BCPE
MAX195BCWE
MAX195ACDE 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 Plastic DIP
16 Wide SO
16 Ceramic SB
MAX195BC/D 0°C to +70°C Dice*
MAX195BEPE -40°C to +85°C 16 Plastic DIP
MAX195BEWE -40°C to +85°C 16 Wide SO
MAX195AEDE -40°C to +85°C 16 Ceramic SB
MAX195AMDE -55°C to +125°C 16 Ceramic SB**
MAX195BMDE -55°C to +125°C 16 Ceramic SB**
EVALUATION KIT
AVAILABLE
*
Dice are specified at TA= +25°C, DC parameters only.
**
Contact factory for availability and processing to MIL-STD-883.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDD to DGND .....................................................................+7V
VDDA to AGND......................................................................+7V
VSSD to DGND.........................................................+0.3V to -6V
VSSA to AGND.........................................................+0.3V to -6V
VDDD to VDDA, VSSD to VSSA..........................................±0.3V
AIN, REF ....................................(VSSA - 0.3V) to (VDDA + 0.3V)
AGND to DGND..................................................................±0.3V
Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V)
Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW
Operating Temperature Ranges
MAX195_C_E........................................................0°C to +70°C
MAX195_E_E .....................................................-40°C to +85°C
MAX195_MDE..................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX195A
16 (t
CLK
)
TA= +25°C
TA= +25°C
Unipolar
V
REF
= 4.75V
MAX195A
MAX195B
MAX195A, V
REF
= 4.75V
VSSA = -5.25V to -4.75V, V
REF
= 4.75V
MAX195B, V
REF
= 4.75V
VDDA = 4.75V to 5.25V, V
REF
= 4.75V
CONDITIONS
MHz1.7f
CLK
Clock Frequency
(Notes 3, 4)
µs9.4t
CONV
Conversion Time
dB-90Peak Spurious Noise (Note 2)
dB-97 -90THD
Total Harmonic Distortion (up to
the 5th harmonic) (Note 2)
V
0 V
REF
Input Range
dB
65
Power-Supply Rejection
Ratio (VDDA and VSSA only)
65
±1
Bits16RESResolution
ppm/°C0.1Full-Scale Tempco
%FSRUnipolar Full-Scale Error ±0.0075
Unipolar/Bipolar Offset Tempco ppm/°C0.4
±0.003
%FSR
±0.004
INLIntegral Nonlinearity
±3
LSB
±4
Unipolar/Bipolar Offset Error
UNITSMIN TYP MAXSYMBOLPARAMETER
Unipolar
pF
250
Input Capacitance
TA= +25°C dB87 90SINAD
Signal-to-Noise plus Distortion
Ratio (Note 2)
MHz5f
SCLK
Serial Clock Frequency
Bipolar
Bipolar 125
-V
REF
V
REF
V
REF
= 4.75V %FSRBipolar Full-Scale Error ±0.018
MAX195B
LSB
±2
DNL
ACCURACY (Note 1)
ANALOG INPUT
DYNAMIC PERFORMANCE (fs= 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1)
Differential Nonlinearity
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
BP/UP/SHDN = open
VDDD = 5.25V
BP/UP/SHDN = open
BP/UP/SHDN = 0V
BP/UP/SHDN = VDDD
Digital inputs = 0 or 5V
VDDD = 4.75V
CONDITIONS
nA-100 +100
BP/UP/SHDN Max Allowed
Leakage, Mid Input
V2.75V
FLT
BP/UP/SHDN Voltage,
Floating
V1.5 VDDD - 1.5V
IM
BP/UP/SHDN
Mid Input Voltage
µA-4.0I
IL
BP/UP/SHDN
Input Current, Low
µA4.0I
IH
BP/UP/SHDN
Input Current, High
V0.5V
IL
BP/UP/SHDN
Input Low Voltage
V2.4V
IH
CLK, CS, CONV, RESET, SCLK
Input High Voltage
VVDDD - 0.5V
IH
BP/UP/SHDN
Input High Voltage
µA±10
CLK, CS, CONV, RESET, SCLK
Input Current
V0.8V
IL
CLK, CS, CONV, RESET, SCLK
Input Low Voltage
pF10
CLK, CS, CONV, RESET, SCLK
Input Capacitance (Note 3)
UNITSMIN TYP MAXSYMBOLPARAMETER
Output Low Voltage V
OL
VDDD = 4.75V, I
SINK
= 1.6mA 0.4 V
Output High Voltage V
OH
VDDD = 4.75V, I
SOURCE
= 1mA VDDD - 0.5 V
DOUT Leakage Current I
LKG
DOUT = 0 or 5V ±10 µA
Output Capacitance (Note 2) 10 pF
VDDD 4.75 5.25 V
VSSD -5.25 -4.75 V
VDDA By supply-rejection test 4.75 5.25 V
VSSA By supply-rejection test -5.25 -4.75 V
VDDD Supply Current I
DDD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 2.5 4 mA
VSSD Supply Current I
SSD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 0.9 2 mA
VDDA Supply Current I
DDA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 3.8 5 mA
VSSA Supply Current I
SSA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 3.8 5 mA
DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN)
DIGITAL OUTPUTS (DOUT, EOC)
POWER REQUIREMENTS
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
4 _______________________________________________________________________________________
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
CONDITIONS
mW80Power Dissipation
µA0.1 5I
SSA
VSSA Shutdown Supply Current
µA0.1 5I
DDA
VDDA Shutdown Supply Current
µA1.6 5I
DDD
VDDD Shutdown Supply Current
(Note 5)
µA0.1 5I
SSD
VSSD Shutdown Supply Current
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f
CLK
= 1.7MHz, V
REF
= +5V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C.)
TIMING CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
Note 1: Accuracy and dynamic performance tests performed after calibration.
Note 2: Guaranteed by design, not tested.
Note 3: Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
Note 4: See
External Clock
section.
Note 5: Measured in shutdown mode with CLK and SCLK low.
POWER REQUIREMENTS (cont.)
PARAMETER SYMBOL CONDITIONS
TA= +25°C
TYP
TA= 0°C to
+70°C
MIN MAX
TA= -40°C to
+85°C
MIN MAX
TA= -55°C to
+125°C
MIN MAX
UNITS
CONV Pulse Width
t
CW
20 30 35 ns
CONV to CLK Falling
Synchronization (Note 2)
t
CC1
10 10 10 ns
CONV to CLK Rising
Synchronization (Note 2)
t
CC2
40 40 ns
Data Access Time t
DV
CL= 50pF 80 80
40
ns
Bus Relinquish Time t
DH
CL= 10pF 40 40 40 ns
CLK to EOC High
t
CEH
CL= 50pF 300 300 350 ns
CLK to EOC Low
t
CEL
CL= 50pF 300 300 350 ns
CLK to DOUT Valid t
CD
CL= 50pF 100 350 100 375 100 400 ns
SCLK to DOUT Valid t
SD
CL= 50pF 20 140 20 160 20 160 ns
CS to SCLK Setup Time
t
CSS
75 75 75 ns
CS to SCLK Hold Time
t
CSH
-10 -10 -10 ns
Acquisition Time t
AQ
2.4 2.4 2.4 µs
Calibration Time t
CAL
14,000 x t
CLK
8.2 8.2 8.2 ms
RESET to CLK Setup Time
t
RCS
-40 -40 -40 ns
RESET to CLK Hold Time
t
RCH
120 120 120
Start-Up Time (Note 6) t
SU
Exiting
shutdown
50
ns
90
µs
Note 6: Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
_______________Detailed Description
The MAX195 uses a successive-approximation register
(SAR) to convert an analog input to a 16-bit digital
code, which outputs as a serial data stream. The data
bits can be read either during the conversion, at the
CLK clock rate, or between conversions asynchronous
with CLK at the SCLK rate (up to 5Mbps).
The MAX195 includes a capacitive digital-to-analog
converter (DAC) that provides an inherent track/hold
input. The interface and control logic are designed for
easy connection to most microprocessors (µPs), limiting
the need for external components. In addition to the
SAR and DAC, the MAX195 includes a serial interface, a
sampling comparator used by the SAR, ten calibration
DACs, and control logic for calibration and conversion.
The DAC consists of an array of 16 capacitors with
binary weighted values plus one “dummy LSB” capacitor (Figure 1). During input acquisition in unipolar
mode, the array’s common terminal is connected to
AGND and all free terminals are connected to the input
signal (AIN). After acquisition, the common terminal is
disconnected from AGND and the free terminals are
disconnected from AIN, trapping a charge proportional
to the input voltage on the capacitor array.
The free terminal of the MSB (largest) capacitor is connected to the reference (REF), which pulls the common
terminal (connected to the comparator) positive.
Simultaneously, the free terminals of all other capacitors in the array are connected to AGND, which drives
the comparator input negative. If the analog input is
near V
REF
, connecting the MSB’s free terminal to REF
only pulls the comparator input slightly positive.
However, connecting the remaining capacitor’s free terminals to ground drives the comparator input well
below ground, so the comparator input is negative, the
comparator output is low, and the MSB is set high. If
the analog input is near ground, the comparator output
is high and the MSB is low.
Following this, the next largest capacitor is disconnected from AGND and connected to REF, and the comparator determines the next bit. This continues until all
bits have been determined. For a bipolar input range,
the MSB capacitor is connected to REF rather than AIN
during input acquisition, which results in an input range
of V
REF
to -V
REF
.
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________ 5
______________________________________________________________Pin Description
PIN NAME FUNCTION
1
BP/UP/SHDN
Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown.
0V = shutdown, +5V = unipolar, floating = bipolar.
2 CLK Conversion Clock Input
3 SCLK Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.
4 VDDD +5V Digital Power Supply
5 DOUT Serial Data Output, MSB first
6 DGND Digital Ground
7
EOC
End-of-Conversion/Calibration Output—normally low. Rises one clock cycle after the beginning of conversion
or calibration and falls one clock cycle after the end of either. May be used as an output framing signal.
8
CS
Chip-Select Input—active low. Enables the serial interface and the three-state data output (DOUT).
9
CONV
Convert-Start Input—active low. Conversion begins on the falling edge after CONV goes low if the input
signal has been acquired; otherwise, on the falling clock edge after acquisition.
10
RESET
Reset Input. Pulling RESET low places the ADC in an inactive state. Rising edge resets control logic and
begins calibration.
11 VSSD -5V Digital Power Supply
12 REF Reference Input, 0 to 5V
13 AIN Analog Input, 0 to V
REF
unipolar or ±V
REF
bipolar range
14 AGND Analog Ground
15 VSSA -5V Analog Power Supply
16 VDDA +5V Analog Power Supply
MAX195
Calibration
In an ideal DAC, each of the capacitors associated with
the data bits would be exactly twice the value of the
next smaller capacitor. In practice, this results in a
range of values too wide to be realized in an economically feasible size. The capacitor array actually consists
of two arrays, which are capacitively coupled to reduce
the LSB array’s effective value. The capacitors in the
MSB array are production trimmed to reduce errors.
Small variations in the LSB capacitors contribute
insignificant errors to the 16-bit result.
Unfortunately, trimming alone does not yield 16-bit performance or compensate for changes in performance
due to changes in temperature, supply voltage, and
other parameters. For this reason, the MAX195 includes
a calibration DAC for each capacitor in the MSB array.
These DACs are capacitively coupled to the main DAC
output and offset the main DAC’s output according to
the value on their digital inputs. During calibration, the
correct digital code to compensate for the error in each
MSB capacitor is determined and stored. Thereafter,
the stored code is input to the appropriate calibration
DAC whenever the corresponding bit in the main DAC
is high, compensating for errors in the associated
capacitor.
The MAX195 calibrates automatically on power-up. To
reduce the effects of noise, each calibration experiment
is performed many times and the results are averaged.
Calibration requires about 14,000 clock cycles, or
8.2ms at the highest clock (CLK) speed (1.7MHz). In
addition to the power-up calibration, bringing RESET
low halts MAX195 operation, and bringing it high again
initiates a calibration (Figure 2).
16-Bit, 85ksps ADC with 10µA Shutdown
6 _______________________________________________________________________________________
MSB
AIN
REF
AGND
DUMMYLSB
32,768C
16,384C 4C 2C C C
EOC
CLK
RESET
CALIBRATION
BEGINS
CALIBRATION
ENDS
MAX195
OPERATION HALTS
t
CAL
t
RCS
t
RCH
Figure 1. Capacitor DAC Functional Diagram
Figure 2. Initiating Calibration
If the power supplies do not settle within the MAX195’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrated. If so, recalibrate the converter (pulse RESET low)
before use. For best DC accuracy, calibrate the
MAX195 any time there is a significant change in supply voltages, temperature, reference voltage, or clock
characteristics (see
External Clock
section) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parameters can be tolerated.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to maintain accuracy or to recalibrate if the MAX195 has been
held in shutdown for long periods. However, recalibration is recommended if it is likely that ambient temperature or supply voltages have significantly changed
since the previous calibration.
Digital Interface
The digital interface pins consist of BP/UP/SHDN, CLK,
SCLK, EOC, CS, CONV, and RESET.
BP/UP/SHDN is a three-level input. Leave it floating to
configure the MAX195’s analog input in bipolar mode
(AIN = -V
REF
to V
REF
) or connect it high for a unipolar
input (AIN = 0V to V
REF
). Bringing BP/UP/SHDN low
places the MAX195 in its 10µA shutdown mode.
A logic low on RESET halts MAX195 operation. The ris-
ing edge of RESET initiates calibration as described in
the
Calibration
section above.
Begin a conversion by bringing CONV low. After conversion begins, additional convert start pulses are
ignored. The convert signal must be synchronized with
CLK. The falling edge of CONV must occur during the
period shown in Figures 3 and 4. When CLK is not
directly controlled by your processor, two methods of
ensuring synchronization are to drive CONV from EOC
(continuous conversions) or to gate the conversion-start
signal with the conversion clock so that CONV can go
low only while CLK is low (Figure 5). Ensure that the
maximum propagation delay through the gate is less
than 40ns.
The MAX195 automatically ensures four CLK periods
for track/hold acquisition. If, when CONV is asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and EOC will go high on the
following falling CLK edge (Figure 3). If, when convert
is asserted, less than three clock cycles have passed,
a conversion will begin on the fourth falling clock edge
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________ 7
TRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
t
AQ
*
*
THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
t
CEL
t
CW
t
CEH
t
CC2
t
CC1
EOC
CONV
Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
MAX195
after the end of the previous conversion and EOC will
go high on the following CLK falling edge (Figure 4).
External Clock
The conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the minimum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temperatures up to +70°C or 1kHz at +125°C due to leakage
of the sampling capacitor array. In addition, CLK
should not remain high longer than 50ms at temperatures up to +70°C or 500µs at +125°C. If CLK is held
high longer than this, RESET must be pulsed low to initiate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by coupling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
Output Data
The conversion result, clocked out MSB first, is available on DOUT only when CS is held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold CS low
during the conversion. To read results between conversions, hold CS low and clock SCLK at up to 5MHz.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after CONV goes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT timing specification. See the
Operating Modes and
SPI™/QSPI™ Interfaces
section for additional information. Reading the serial data during the conversion
results in the maximum conversion throughput,
because a new conversion can begin immediately after
the input acquisition period following the previous conversion.
16-Bit, 85ksps ADC with 10µA Shutdown
8 _______________________________________________________________________________________
TRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
t
AQ
*
*
THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
t
CEL
t
CW
t
CEH
t
CC2
t
CC1
EOC
CONV
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
If you read the data bits between conversions, you can:
1) count CLK cycles until the end of the conversion, or
2) poll EOC to determine when the conversion is
finished, or
3) generate an interrupt on EOC’s falling edge.
Note that the MSB conversion result appears at DOUT
after CS goes low, but before the first SCLK pulse.
Each subsequent SCLK pulse shifts out the next conversion bit. The 15th SCLK pulse shifts out the LSB.
Additional clock pulses shift out zeros.
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________ 9
CLK
START
CONV
MAX195
CONV
START
CLK
SEE
DIGITAL INTERFACE
SECTION
Figure 5. Gating CONV to Synchronize with CLK
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
CS
CONV
t
CW
CLK
(CASE 1)
CLK
(CASE 2)
EOC
DOUT
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
t
DV
B15 FROM PREVIOUS
CONVERSION
CONVERSION
BEGINS
t
CEH
t
CD
B15
B14 B13 B12 B2 B1 B0 B15
MSB
LSB
CONVERSION
ENDS
t
CEL
t
DH
Loading...