MAXIM MAX19538 Technical data

General Description

The MAX19538 is a 3.3V, 12-bit, 95Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input accepts single-ended or differential signals. The MAX19538 is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX19538 ideal for intermediate frequency (IF) sampling applications.

Powered from a single 3.3V supply, the MAX19538 consumes only 492mW while delivering a typical 68.4dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX19538 features a 63µW power-down mode to conserve power during idle periods.

A flexible reference structure allows the MAX19538 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX19538 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.

The MAX19538 supports either a single-ended or differential input clock drive. The internal clock duty-cycle equalizer accepts a wide range of clock duty cycles.

Analog-to-digital conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply allowing the MAX19538 to interface with various logic levels.

The MAX19538 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range.

See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs.

Applications

IF and Baseband Communication Receivers Cellular, Point-to-Point Microwave, HFC Medical Imaging Including Positron

Emission Tomography (PET) Video Imaging Portable Instrumentation Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance

70.9dB/68.4dB SNR at fIN= 3MHz/175MHz

89.0dBc/76.2dBc SFDR at fIN= 3MHz/175MHz

-71.5dBFS Small-Signal Noise Floor

♦ 3.3V Low-Power Operation

465mW (Single-Ended Clock Mode) 492mW (Differential Clock Mode) 63µW (Power-Down Mode)

♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Full-Scale Analog Input Range: ±0.35V

to ±1.10V

♦ Common-Mode Reference ♦ CMOS-Compatible Outputs in Two’s Complement

or Gray Code

♦ Data-Valid Indicator Simplifies Digital Design ♦ Data Out-of-Range Indicator ♦ Miniature 6mm x 6mm x 0.8mm 40-Pin Thin QFN

Package with Exposed Paddle

♦ Evaluation Kit Available (Order MAX1211EVKIT)

MAX19538

12-Bit, 95Msps, 3.3V ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3403; Rev 0; 10/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

+Denotes lead-free package. *All devices are specified over the -40°C to +85°C operating

range.

PART* PIN-PACKAGE PKG CODE

MAX19538ETL 40 Thin QFN T4066-3

MAX19538ETL+

40 Thin QFN T4066-3

Pin-Compatible Versions

SAMPLING

PART

MAX12555 95 14 IF/Baseband

MAX12554 80 14 IF/Baseband

MAX12553 65 14 IF/Baseband

MAX19538 95 12 IF/Baseband

MAX1209 80 12 IF

MAX1211 65 12 IF

MAX1208 80 12 Baseband

MAX1207 65 12 Baseband

MAX1206 40 12 Baseband

RATE

(Msps)

RESOLUTION

(BITS)

TARGET

APPLICATION

MAX19538

12-Bit, 95Msps, 3.3V ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/

T = low, f

CLK

= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND...........................................................-0.3V to +3.6V

to GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V

INP, INN to GND ...-0.3V to the lower of (V

+ 0.3V) and +3.6V

REFIN, REFOUT, REFP, REFN,

COM to GND.....-0.3V to the lower of (V

+ 0.3V) and +3.6V

CLKP, CLKN, CLKTYP, G / T, DCE,

PD to GND ........-0.3V to the lower of (V

+ 0.3V) and +3.6V

D11–D0, I.C., DAV,

DOR to GND........................................-0.3V to (OV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated

26.3mW/°C above +70°C) ......................................2105.3mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering 10s) ..................................+300°C

PARAMETER

CONDITIONS

DC ACCURACY (Note 2)

Resolution 12 Bits

Integral Nonlinearity INL fIN = 3MHz

LSB

Differential Nonlinearity DNL

LSB

Offset Error V

REFIN

= 2.048V

Gain Error V

REFIN

= 2.048V

ANALOG INPUT (INP, INN)

Differential Input Voltage Range V

DIFF

Differential or single-ended inputs

Common-Mode Input Voltage

PAR

Fixed capacitance to ground 2

Input Capacitance (Figure 3)

Switched capacitance 4.5

CONVERSION RATE

Maximum Clock Frequency f

CLK

Minimum Clock Frequency 5

Data Latency Figure 6 8.5

DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)

Small-Signal Noise Floor SSNF Input at less than -35dBFS

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 70MHz at -0.5dBFS

Signal-to-Noise Ratio SNR

= 175MHz at -0.5dBFS (Note 3)

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 70MHz at -0.5dBFS

Signal-to-Noise and Distortion SINAD

= 175MHz at -0.5dBFS (Note 3)

SYMBOL

= 3M H z, n o m i ssi ng codes over tem per atur e -0.55 ±0.30 +0.95

MIN TYP MAX UNITS

-1.7 ±0.4 +1.4

±0.10 ±0.58 %FS

±0.6 ±4.9 %FS

±1.024

/ 2

SAMPLE

-71.5 dBFS

67.2 70.9

70.4

65.5 68.4

66.5 70.8

70.0

63.3 67.5

MHz

Clock

cycles

MAX19538

12-Bit, 95Msps, 3.3V ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f

CLK

= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 70MHz at -0.5dBFS

Spurious-Free Dynamic Range SFDR

= 175MHz at -0.5dBFS (Note 3)

dBc

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 70MHz at -0.5dBFS

Total Harmonic Distortion THD

= 175MHz at -0.5dBFS (Note 3)

dBc

fIN = 3MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Second Harmonic HD2

= 175MHz at -0.5dBFS

dBc

fIN = 3MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Third Harmonic HD3

= 175MHz at -0.5dBFS

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

Intermodulation Distortion IMD

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

Third-Order Intermodulation IM3

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

Two-Tone Spurious Free Dynamic Range

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

Aperture Delay t

Figure 4 1.2 ns

Aperture Jitter t

Figure 4

RMS

Output Noise n

OUT

INP = INN = COM

LSB

RMS

Overdrive Recovery Time ±10% beyond full scale 1

Clock

cycles

INTERNAL REFERENCE (REFIN = REFOUT; V

REFP

, V

REFN

, and V

COM

are generated internally)

REFOUT Output Voltage

COM Output Voltage V

COM

/ 2

Differential-Reference Output Voltage

REF

= V

REFP

- V

REFN

= V

REFIN

x 3/4

REFOUT Load Regulation -1.0mA < I

REFOUT

< 0.1mA 35

mV/mA

REFOUT Temperature Coefficient

REF

ppm/°C

Short to VDD, sinking

REFOUT Short-Circuit Current

Short to GND, sourcing 2.1

SFDR

REFOUT

73.5 89.0

83.5

67.2 76.2

-86.3 -72.9

-81.2

-74.7 -66.2

-92.4

-91.3

-82.3

-89.6

-83.7

-76.2

-82.5

-73.6

-84.3

-76.0

84.7

75.6

<0.2

0.36

1.996 2.048 2.063

1.65

1.536

+50

0.24

MAX19538

12-Bit, 95Msps, 3.3V ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f

CLK

= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

BUFFERED EXTERNAL REFERENCE (REFIN driven externally; V

REFIN

= 2.048V, V

REFP

, V

REFN

, and V

COM

are generated

internally)

REFIN Input Voltage V

REFIN

REFP Output Voltage V

REFP

/ 2) + (V

REFIN

x 3/8)

REFN Output Voltage V

REFN

/ 2) - (V

REFIN

x 3/8)

COM Output Voltage V

COM

/ 2

Differential-Reference Output Voltage

REF

= V

REFP

- V

REFN

= V

REFIN

x 3/4

Differential-Reference Temperature Coefficient

ppm/°C

REFIN Input Resistance

MΩ

UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V

REFP

, V

REFN

, and V

COM

are applied externally)

COM Input Voltage V

COM

/ 2

REFP Input Voltage V

REFP

- V

COM

REFN Input Voltage V

REFN

- V

COM

D i ffer enti al - Refer ence Inp ut V ol tag e

REF

= V

REFP

- V

REFN

= V

REFIN

x 3/4

REFP Sink Current I

REFP

= 2.418V 1.4 mA

REFN Source Current I

REFN

= 0.882V 1.0 mA

COM Sink Current I

COM

= 1.65V 1.0 mA

REFP, REFN Capacitance 13 pF

COM Capacitance 6pF

CLOCK INPUTS (CLKP, CLKN)

Single-Ended-Input High Threshold

CLKTYP = GND, CLKN = GND

0.8 x V

Single-Ended-Input Low Threshold

CLKTYP = GND, CLKN = GND

0.2 x V

Differential Input Voltage Swing CLKTYP = high 1.4 V

P-P

Differential Input Common-Mode Voltage

CLKTYP = high

Input Resistance R

CLK

Figure 5 5 kΩ

Input Capacitance C

CLK

2pF

DIGITAL INPUTS (CLKTYP, DCE, G / TTTT , PD)

Input High Threshold V

0.8 x V

Input Low Threshold V

0.2 x V

VIH = OV

±5

Input Leakage Current

= 0 ±5

µA

Input Capacitance C

DIN

5pF

SYMBOL

MIN TYP MAX

2.048

2.418

0.882

1.60 1.65 1.70

1.462 1.536 1.594

±25

>50

1.65

+0.768

-0.768

1.536

/ 2

MAX19538

12-Bit, 95Msps, 3.3V ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f

CLK

= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

DIGITAL OUTPUTS (D11–D0, DAV, DOR)

D11–D0, DOR, I

SINK

= 200µA 0.2

Output-Voltage Low V

DAV, I

SINK

= 600µA 0.2

D11–D0, DOR, I

SOURCE

= 200µA

0.2

Output-Voltage High V

DAV, I

SOURCE

= 600µA

0.2

Tri-State Leakage Current I

LEAK

(Note 4) ±5 µA

D11–D0, DOR Tri-State Output Capacitance

OUT

(Note 4) 3 pF

DAV Tri-State Output Capacitance

DAV

(Note 4) 6 pF

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Output Supply Voltage OV

1.7 1.8

Normal operating mode,

single-ended clock

Normal operating mode,

differential clock

163

Analog Supply Current I

VDD

Power-down mode clock idle PD = OV

Normal operating mode,

single-ended clock

Normal operating mode,

differential clock

538

Analog Power Dissipation P

DISS

Power-down mode clock idle PD = OV

Normal operating mode, f

= 175MHz at -0.5dBFS, CL ≈ 5pF

9.9 mA

Digital Output Supply Current I

OVDD

Power-down mode clock idle PD = OV

1.0 µA

SYMBOL

fIN = 175MHz at -0.5dBFS CLKTYP = GND,

fIN = 175MHz at -0.5dBFS CLKTYP = OVDD,

fIN = 175MHz at -0.5dBFS CLKTYP = GND,

fIN = 175MHz at -0.5dBFS CLKTYP = OVDD,

MIN TYP MAX

3.15 3.30 3.60

141

149

0.22

465

492

0.3V

0.063

MAX19538

12-Bit, 95Msps, 3.3V ADC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f

CLK

= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

TIMING CHARACTERISTICS (Figure 6)

Clock Pulse-Width High t

Clock Pulse-Width Low t

Data-Valid Delay t

DAV

CL ≈ 5pF (Note 5) 6.8 ns

Data Setup Time Before Rising Edge of DAV

SETUP

CL ≈ 5pF (Notes 5, 6) 5.7 ns

Data Hold Time After Rising Edge of DAV

HOLD

CL ≈ 5pF (Notes 5, 6) 4.2 ns

Wake-Up Time from Power-Down

WAKE

REFIN

= 2.048V 10 ms

Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Note 2: See definitions in the Parameter Definitions section at the end of this data sheet. Note 3: Limit specifications include performance degradations due to production test socket. Performance is improved when the

MAX19538 is soldered directly to the PC board.

Note 4: During power-down, D11–D0, DOR, and DAV are high impedance. Note 5: Digital outputs settle to V

or VIL.

Note 6: Guaranteed by design and characterization.

SYMBOL

MIN TYP MAX

5.26

MAX19538

12-Bit, 95Msps, 3.3V ADC

_______________________________________________________________________________________ 7

Typical Operating Characteristics

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

MAX19538 toc01

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

HD4

CLK

= 95MHz

= 3.00354004MHz

= -0.519dBFS SNR = 70.89dB SINAD = 70.83dB THD = -89.3dBc SFDR = 93.6dBc

HD3

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

MAX19538 toc02

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

HD2

HD5

CLK

= 95MHz

= 47.30285645MHz

= -0.510dBFS SNR = 70.80dB SINAD = 70.41dB THD = -81.0dBc SFDR = 83.2dBc

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

MAX19538 toc03

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

HD3

HD5

HD2

CLK

= 95MHz

= 69.89318848MHz

= -0.472dBFS SNR = 70.65dB SINAD = 70.35dB THD = -82.1dBc SFDR = 85.8dBc

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

MAX19538 toc04

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

HD3

HD5

HD2

CLK

= 95MHz

= 174.8895264MHz

= -0.521dBFS SNR = 69.02dB SINAD = 68.19dB THD = -75.8dBc SFDR = 76.8dBc

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

MAX19538 toc05

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

HD3

HD5

HD2

CLK

= 95MHz

= 224.8944092MHz

= -0.531dBFS SNR = 68.14dB SINAD = 66.42dB THD = -71.3dBc SFDR = 72.4dBc

TWO-TONE FFT PLOT

(16,384-POINT DATA RECORD)

MAX19538 toc06

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

2 × f

IN1

+ f

IN2

IN1

+ f

IN2

3 × f

IN1

+ 2 × f

IN2

2 × f

IN2

+ f

IN1

IN2

IN1

CLK

= 95MHz

IN1

= 68.50739MHz

IN1

= -7.0dBFS

IN2

= 71.51093MHz

IN2

= -7.0dBFS

SFDR

= 84.7dB IMD = -82.4dBc IM3 = -84.3dBc

TWO-TONE FFT PLOT

(16,384-POINT DATA RECORD)

MAX19538 toc07

FREQUENCY (MHz)

AMPLITUDE (dBFS)

454030 3510 15 20 255

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-110 0

2 × f

IN1

+ f

IN2

IN1

+ f

IN2

- f

IN1

2 × f

IN2

+ f

IN1

IN2

IN1

CLK

= 95MHz

IN1

= 172.4716MHz

IN1

= -7.0dBFS

IN2

= 177.4698MHz

IN2

= -7.0dBFS

SFDR

= 75.5dBc IMD = -73.6dBc IM3 = -76.0dBc

INTEGRAL NONLINEARITY

MAX19538 toc08

DIGITAL OUTPUT CODE

INL (LSB)

358430722048 25601024 1536512

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0 0 4096

DIFFERENTIAL NONLINEARITY

MAX19538 toc09

DIGITAL OUTPUT CODE

DNL (LSB)

358430722048 25601024 1536512

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0 0 4096

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.

MAX19538

12-Bit, 95Msps, 3.3V ADC

8 _______________________________________________________________________________________

SNR, SINAD vs. SAMPLING RATE

MAX19538 toc10

CLK

(MHz)

SNR, SINAD (dB)

100755025

0125

SNR SINAD

fIN = 70MHz

SFDR, -THD vs. SAMPLING RATE

MAX19538 toc11

CLK

(MHz)

SFDR, -THD (dBc)

100

1007550250125

SFDR

-THD

fIN = 70MHz

POWER DISSIPATION

vs. SAMPLING RATE

MAX19538 toc12

CLK

(MHz)

POWER DISSIPATION (mW)

100755025

350

400

450

500

550

300

0125

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

= 70MHz

≈ 5pF

SNR, SINAD vs. SAMPLING RATE

MAX19538 toc13

CLK

(MHz)

SNR, SINAD (dB)

100755025

0125

SNR SINAD

fIN = 175MHz

SFDR, -THD

vs. SAMPLING RATE

MAX19538 toc14

CLK

(MHz)

SFDR, -THD (dBc)

100

1007550250125

SFDR

-THD

fIN = 175MHz

POWER DISSIPATION

vs. SAMPLING RATE

MAX19538 toc15

CLK

(MHz)

POWER DISSIPATION (mW)

100755025

350

400

450

500

550

600

650

700

300

0125

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

= 175MHz

≈ 5pF

SNR, SINAD

vs. ANALOG INPUT FREQUENCY

MAX19538 toc16

ANALOG INPUT FREQUENCY (MHz)

SNR, SINAD (dB)

350300200 250100 15050

0400

SNR SINAD

CLK

= 95MHz

SFDR, -THD

vs. ANALOG INPUT FREQUENCY

MAX19538 toc17

SFDR, -THD (dBc)

100

ANALOG INPUT FREQUENCY (MHz)

350300200 250100 150500400

SFDR

-THD

CLK

= 95MHz

POWER DISSIPATION

vs. ANALOG INPUT FREQUENCY

MAX19538 toc18

ANALOG INPUT FREQUENCY (MHz)

POWER DISSIPATION (mW)

35030025020015010050

450

500

550

600

650

700

400

0400

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

CLK

= 95MHz

≈ 5pF

MAX19538

12-Bit, 95Msps, 3.3V ADC

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.

SNR, SINAD

vs. ANALOG INPUT AMPLITUDE

MAX19538 toc19

ANALOG INPUT AMPLITUDE (dBFS)

SNR, SINAD (dB)

-5-10-20 -15-30 -25-35

-40 0

SNR SINAD

CLK

= 95MHz

= 175MHz

SFDR, -THD

vs. ANALOG INPUT AMPLITUDE

MAX19538 toc20

ANALOG INPUT AMPLITUDE (dBFS)

SFDR, -THD (dBc)

-5-10-20 -15-30 -25-35

-40 0

CLK

= 95MHz

= 175MHz

SFDR

-THD

POWER DISSIPATION

vs. ANALOG INPUT AMPLITUDE

MAX19538 toc21

ANALOG INPUT AMPLITUDE (dBFS)

POWER DISSIPATION (mW)

-5-10-15-20-25-30-35

450

500

550

600

650

700

400

-40 0

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

CLK

= 96MHz

= 175MHz

≈ 5pF

SNR, SINAD

vs. ANALOG SUPPLY VOLTAGE

MAX19538 toc22

VDD (V)

SNR, SINAD (dB)

3.43.23.02.8

2.6 3.6

SNR SINAD

CLK

= 95MHz

= 175MHz

SFDR, -THD

vs. ANALOG SUPPLY VOLTAGE

MAX19538 toc23

VDD (V)

SFDR, -THD (dBc)

100

3.43.23.02.82.6 3.6

SFDR

-THD

CLK

= 95MHz

= 175MHz

POWER DISSIPATION

vs. ANALOG SUPPLY VOLTAGE

MAX19538 toc24

VDD (V)

POWER DISSIPATION (mW)

3.43.23.02.8

350

400

450

500

550

600

300

2.6 3.6

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

CLK

= 95MHz

= 175MHz

≈ 5pF

SNR, SINAD

vs. DIGITAL SUPPLY VOLTAGE

MAX19538 toc25

OVDD (V)

3.4

3.02.62.21.81.4 3.8

SNR, SINAD (dB)

SNR SINAD

fIN = 174.8953247MHz f

CLK

= 95MHz

SFDR, -THD

vs. DIGITAL SUPPLY VOLTAGE

MAX19538 toc26

SFDR, -THD (dBc)

100

OVDD (V)

3.43.02.62.21.81.4 3.8

SFDR

-THD

fIN = 174.8953247MHz f

CLK

= 95MHz

POWER DISSIPATION

vs. DIGITAL SUPPLY VOLTAGE

MAX19538 toc27

OVDD (V)

POWER DISSIPATION (mW)

3.43.02.62.21.8

450

500

550

600

650

700

400

1.4 3.8

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

= 175.8953247MHz

= 95MHz

≈ 5pF

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.

MAX19538

12-Bit, 95Msps, 3.3V ADC

10 ______________________________________________________________________________________

SNR, SINAD

vs. TEMPERATURE

MAX19538 toc28

TEMPERATURE (°C)

SNR, SINAD (dB)

603510-15

-40 85

SNR SINAD

CLK

= 95MHz

= 175MHz

SFDR, -THD

vs. TEMPERATURE

MAX19538 toc29

TEMPERATURE (°C)

SFDR, -THD (dBc)

6035-15 10

100

-40 85

SFDR

-THD

CLK

= 95MHz

= 175MHz

POWER DISSIPATION

vs. TEMPERATURE

MAX19538 toc30

TEMPERATURE (°C)

ANALOG POWER DISSIPATION (mW)

603510-15

450

500

550

600

650

700

400

-40 85

ANALOG + DIGITAL POWER ANALOG POWER

DIFFERENTIAL CLOCK f

CLK

= 95MHz

= 175MHz

≈ 5pF

OFFSET ERROR

vs. TEMPERATURE

MAX19538 toc31

TEMPERATURE (°C)

OFFSET ERROR (%FS)

603510-15

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

-40 85

REFIN

= 2.048V

GAIN ERROR

vs. TEMPERATURE

MAX19538 toc32

TEMPERATURE (°C)

GAIN ERROR (%FS)

603510-15

-2.0

-1.0

-0.5

0.5

1.0

1.5

2.0

-3.0

-40 85

REFIN

= 2.048V

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 11

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.

REFERENCE OUTPUT VOLTAGE

LOAD REGULATION

MAX19538 toc33

REFOUT

SINK CURRENT (mA)

REFOUT

(V)

0-0.5-1.0-1.5

1.96

1.97

1.98

1.99

2.00

2.01

2.02

2.03

2.04

2.05

1.95

-2.0 0.5

+85°C

+25°C

-40°C

REFERENCE OUTPUT VOLTAGE

SHORT-CIRCUIT PERFORMANCE

MAX19538 toc34

REFOUT

SINK CURRENT (mA)

REFOUT

(V)

0-1.0-2.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-3.0 1.0

+85°C

+25°C

-40°C

REFERENCE OUTPUT VOLTAGE

vs. TEMPERATURE

MAX19538 toc35

TEMPERATURE (°C)

REFOUT

(V)

603510-15

2.031

2.033

2.035

2.037

2.039

2.029

-40 85

REFP, COM, REFN

LOAD REGULATION

MAX19538 toc36

SINK CURRENT (mA)

VOLTAGE (V)

10-1

0.5

1.0

1.5

2.0

2.5

3.0

-2

INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE.

REFP

REFN

COM

REFP, COM, REFN

SHORT-CIRCUIT PERFORMANCE

MAX19538 toc37

SINK CURRENT (mA)

VOLTAGE (V)

840-4

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-8 12

INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE.

REFP

REFN

COM

MAX19538

12-Bit, 95Msps, 3.3V ADC

12 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 REFP

Positive Reference I/O. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3. Bypass REFP to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP-to-REFN capacitor as close to the device as possible on the

same side of the PC board.

2 REFN

Negative Reference I/O. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3. Bypass REFN to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP-to-REFN capacitor as close to the device as possible on the

same side of the PC board.

3 COM

Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM-to- GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the opposite side of the PC board and connected to the MAX19538 through a via.

4, 7, 16, 35

GND Ground. Connect all ground pins and EP together.

5 INP Positive Analog Input

6 INN Negative Analog Input

8 DCE

Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OV

or VDD) to enable the internal duty-cycle equalizer.

9 CLKN

Negative Clock Input. In differential clock input mode (CLKTYP = OV

or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND.

10 CLKP

Positive Clock Input. In differential clock input mode (CLKTYP = OV

or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND.

11 CLKTYP

Clock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OV

or VDD to define the differential clock input.

12–15, 36

Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of

≥2.2µF and 0.1µF. Connect all V

pins to the same potential.

17, 34 OV

Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of

≥2.2µF and 0.1µF.

18 DOR

Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6).

19 D11 CMOS Digital Output, Bit 11 (MSB)

20 D10 CMOS Digital Output, Bit 10

21 D9 CMOS Digital Output, Bit 9

22 D8 CMOS Digital Output, Bit 8

23 D7 CMOS Digital Output, Bit 7

24 D6 CMOS Digital Output, Bit 6

25 D5 CMOS Digital Output, Bit 5

26 D4 CMOS Digital Output, Bit 4

27 D3 CMOS Digital Output, Bit 3

28 D2 CMOS Digital Output, Bit 2

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 13

Figure 1. Pipeline Architecture—Stage Blocks

MAX19538

−

DIGITAL ERROR CORRECTION

FLASH

ADC

T/H

DAC

STAGE 2

D11–D0

INP

INN

STAGE 1

T/H

STAGE 9

STAGE 10

END OF PIPE

OUTPUT

DRIVERS

D11–D0

Figure 2. Simplified Functional Diagram

MAX19538

INP

INN

12-BIT

PIPELINE

ADC

DEC

REFERENCE

SYSTEM

COM

REFOUT

REFN

REFP

DAV

OUTPUT DRIVERS

D11–D0

DOR

REFIN

T/H

POWER CONTROL

AND

BIAS CIRCUITS

CLKP

CLOCK

GENERATOR

AND

DUTY-CYCLE

EQUALIZER

CLKN

CLKTYP

GND

DCE

G/T

Pin Description (continued)

PIN NAME FUNCTION

29 D1 CMOS Digital Output, Bit 1

30 D0 CMOS Digital Output, Bit 0 (LSB)

31, 32 I.C. Internally Connected. Leave I.C. unconnected.

33 DAV

Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the MAX19538 output data into an external back-end digital circuit.

37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.

38 REFOUT

Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a

≥0.1µF capacitor.

39 REFIN

Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a

≥0.1µF capacitor. In these modes V

REFP

- V

REFN

= V

REFIN

x 3/4. For unbuffered external

reference mode operation, connect REFIN to GND.

40 G/ T

Output-Format-Select Input. Connect G/ T to GND for the two’s-complement digital output format. Connect G/ T to OV

or VDD for the Gray-code digital output format.

—EP

Exposed Paddle. The MAX19538 relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane.

Detailed Description

The MAX19538 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles.

Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX19538 functional diagram.

MAX19538

12-Bit, 95Msps, 3.3V ADC

14 ______________________________________________________________________________________

Input Track-and-Hold (T/H) Circuit

Figure 3 displays a simplified functional diagram of the

input track-and-hold (T/H) circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a V

/ 2 ±0.5V common-

mode input voltage.

The MAX19538 sampling clock controls the ADC’s switched-capacitor T/H architecture (Figure 3), allowing the analog input signal to be stored as charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and they are open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of provid-

ing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these capacitors must be charged to 1/2 LSB accuracy within one half of a clock cycle.

The analog input of the MAX19538 supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (V

/ 2). The MAX19538 provides the optimum

common-mode voltage of V

/ 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 10, 11, and 12.

Reference Output (REFOUT)

An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX19538. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires 10ms to power up and settle when power is applied to the MAX19538 or when PD transitions from high to low. REFOUT has approximately 17kΩ to GND when the MAX19538 is in power-down.

The internal bandgap reference and its buffer generate V

REFOUT

to be 2.048V. The reference temperature coeffi-

cient is typically +50ppm/°C. Connect an external ≥0.1µF bypass capacitor from REFOUT to GND for stability.

REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I

REFOUT

to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to V

Figure 3. Simplified Input Track-and-Hold Circuit

MAX19538

PAR

2pF

BOND WIRE

INDUCTANCE

1.5nH

INP

SAMPLING

CLOCK

*THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS:

SAMPLE

4.5pF

PAR

2pF

BOND WIRE

INDUCTANCE

1.5nH

INN

SAMPLE

4.5pF

SAMPLE

CLK

x C

SAMPLE

Figure 4. T/H Aperture Timing

T/H

CLKN

CLKP

TRACK HOLDTRACK HOLDTRACK HOLDTRACKHOLD

ANALOG

INPUT

SAMPLED

DATA

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 15

Analog Inputs and Reference

Configurations

The MAX19538 full-scale analog input range is adjustable from ±0.35V to ±1.10V with a commonmode input range of V

/ 2 ±0.5V. The MAX19538 provides three modes of reference operation. The voltage at REFIN (V

REFIN

) sets the reference operation

mode (Table 1).

To operate the MAX19538 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with V

COM

/ 2, V

REFP

= V

/ 2 + V

REFIN

x 3/8, and V

REFN

/ 2 - V

REFIN

x 3/8. The REFIN input impedance is

very large (>50MΩ). When driving REFIN through a resistive divider, use resistances ≥10kΩ to avoid loading REFOUT.

Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX19538 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.2V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance

outputs with V

COM

= V

/ 2, V

REFP

= V

/ 2 + V

REFIN

x 3/8, and V

REFN

= VDD/2 - V

REFIN

x 3/8.

To operate the MAX19538 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive V

COM

to V

/ 2

±5%, and drive REFP and REFN such that V

COM

REFP

+ V

REFN

) / 2. The full-scale analog input range

is ±(V

REFP

- V

REFN

) x 2/3.

All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2µF capacitor to GND. Bypass REFP and REFN each with a 0.1µF capacitor to GND. Bypass REFP to REFN with a 1µF capacitor in parallel with a 10µF capacitor. Place the 1µF capacitor as close to

the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a

0.1µF capacitor.

For detailed circuit suggestions, see Figures 13 and 14.

REFIN

REFERENCE MODE

35% V

REFOUT

to 100% V

REFOUT

Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is ±V

REFIN

/ 2:

COM

= V

/ 2

REFP

= V

/ 2 + V

REFIN

x 3/8

REFN

= V

/ 2 - V

REFIN

x 3/8

0.7V to 2.2V

Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN. The full-scale analog input range is ±V

REFIN

/ 2:

COM

= V

/ 2

REFP

= V

/ 2 + V

REFIN

x 3/8

REFN

= V

/ 2 - V

REFIN

x 3/8

<0.4V

Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3.

Table 1. Reference Modes

MAX19538

12-Bit, 95Msps, 3.3V ADC

16 ______________________________________________________________________________________

Clock Input and Clock Control Lines

(CLKP, CLKN, CLKTYP)

The MAX19538 accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock input operation, connect CLKTYP to OVDDor VDD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines.

CLKP and CLKN are high impedance when the MAX19538 is powered down (Figure 5).

Low clock jitter is required for the specified SNR performance of the MAX19538. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship:

where fINrepresents the analog input frequency and t

is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 68.4dB of SNR with an input frequency of 175MHz, the system must have less than

0.35ps of clock jitter. In actuality, there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.23ps to obtain the specified

68.4dB of SNR at 175MHz.

Clock Duty-Cycle Equalizer (DCE)

Connect DCE high to enable the clock duty-cycle equalizer (DCE = OVDDor VDD). Connect DCE low to disable the clock duty-cycle equalizer (DCE = GND). With the clock duty-cycle equalizer enabled, the MAX19538 is insensitive to the duty cycle of the signal applied to CLKP and CLKN. Duty cycles from 35% to 65% are acceptable with the clock duty-cycle equalizer enabled.

The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX19538 requires approximately 100 clock cycles to acquire and lock to new clock frequencies.

Although not recommended, disabling the clock dutycycle equalizer reduces the analog supply current by

1.5mA. With the clock duty-cycle equalizer disabled, the MAX19538’s dynamic performance varies depending on the duty cycle of the signal applied to CLKP and CLKN.

SNR

IN J

=×

×× ×

⎛ ⎝

⎜

⎞ ⎠

⎟

log20

2 π

Figure 5. Simplified Clock Input Circuit

MAX19538

CLKP

CLKN

GND

10kΩ

DUTY-CYCLE

EQUALIZER

SWITCHES S

AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S

ARE OPEN IN

SINGLE-ENDED CLOCK MODE.

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 17

System Timing Requirements

Figure 6 shows the relationship between the clock, ana-

log inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later.

The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN).

Data-Valid Output (DAV)

DAV is a single-ended version of the input clock (CLKP). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6).

The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is the inverse of the signal at CLKP delayed by 6.8ns. With the dutycycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D11–D0 and DOR are valid from 5.7ns (t

SETUP

) before the rising

edge of DAV to 4.2ns (t

HOLD

) after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.8ns (t

DAV

) delay from the falling edge of CLKP.

DAV is high impedance when the MAX19538 is in powerdown (PD = high). DAV is capable of sinking and sourc-

ing 600µA and has three times the drive strength of D11–D0 and DOR. DAV is typically used to latch the MAX19538 output data into an external back-end digital circuit.

Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX19538 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX1211 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer.

Data Out-of-Range Indicator (DOR)

The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (V

REFP

- V

REFN

) x 2/3 to (V

REFN

- V

REFP

) x 2/3. Signals outside this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6.

DOR is synchronized with DAV and transitions along with the output data D11–D0. There is an 8.5 clockcycle latency in the DOR function, as is with the output data (Figure 6).

DOR is high impedance when the MAX19538 is in power-down (PD = high). DOR enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD’s falling edge.

Figure 6. System Timing Diagram

DAV

D0–D11

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

DAV

SETUP

N - 1

N - 2

N - 3

HOLD

DOR

8.5 CLOCK-CYCLE DATA LATENCY

DIFFERENTIAL ANALOG INPUT (INP–INN)

SETUP

HOLD

N N + 1 N + 2 N + 3 N + 5 N + 6 N + 7N - 1N - 2N - 3 N + 9N + 4 N + 8

CLKN

CLKP

REFP

- V

REFN

) x 2/3

REFN

- V

REFP

) x 2/3

MAX19538

12-Bit, 95Msps, 3.3V ADC

18 ______________________________________________________________________________________

Digital Output Data (D11–D0), Output Format (G/ T)

The MAX19538 provides a 12-bit, parallel, tri-state output bus. D11–D0 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV.

The MAX19538 output data format is either Gray code or two’s complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two’s complement. See Figure 9 for a binary-to-Gray and Gray-to-

binary code conversion example.

The following equations, Table 2, Figure 7, and Figure 8 define the relationship between the digital output and the analog input:

for Gray code (G/T = 1).

for two’s complement (G/T = 0).

where CODE10is the decimal equivalent of the digital output code as shown in Table 2.

Digital outputs D11–D0 are high impedance when the MAX19538 is in power-down (PD = high). D11–D0 transition high 10ns after the rising edge of PD and become active 10ns after PD’s falling edge.

Keep the capacitive load on the MAX19538 digital outputs D11–D0 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX19538 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the MAX19538 from heavy capacitive loading. To improve the dynamic performance of the MAX19538, add 220Ω resistors in series with the digital outputs close to the MAX19538. Refer to the MAX1211 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220Ω series resistors.

VV V V

CODE

INP INN REFP REFN

−−=

()

××

4 3 4096

VV V V

CODE

INP INN REFP REFN

−−

−

()

××

4 3

2048

4096

Figure 7. Two’s-Complement Transfer Function (G/T= 0)

DIFFERENTIAL INPUT VOLTAGE (LSB)

TWO'S-COMPLEMENT OUTPUT CODE (LSB)

-2045 +2047+2045-1 0 +1-2047

0x800

0x801

0x802

0x803

0x7FF 0x7FE

0x7FD

0xFFF

0x000

0x001

REFP

- V

REFN

) x 2/3 (V

REFP

- V

REFN

) x 2/3

Figure 8. Gray-Code Transfer Function (G/T= 1)

DIFFERENTIAL INPUT VOLTAGE (LSB)

GRAY OUTPUT CODE (LSB)

+1 +2047+2045-1

-2047 -2045

0x000

0x001

0x003

0x002

0x800 0x801 0x803

0x400

0xC00

0xC01

REFP

- V

REFN

) x 2/3 (V

REFP

- V

REFN

) x 2/3

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 19

Table 2. Output Codes vs. Input Voltage

GRAY-CODE

OUTPUT CODE

(G/TT

= 1)

TWO’S-COMPLEMENT

OUTPUT CODE

(G/TT

= 0)

BINARY

D11  D0

EQUIVALENT

D11  D0

D EC IM A L

D11  D0

(CODE

)

BINARY

D11  D0

DECIM AL

D11  D0

(CODE

)

INP

- V

INN

REFP

= 2.418V

REFN

= 0.882V

1000 0000 0000

0x800 +4095 0111 1111 1111 1 0x7FF +2047

>+1.0235V

(DATA OUT OF

RANGE)

1000 0000 0000

0x800 +4095 0111 1111 1111 0 0x7FF +2047 +1.0235V

1000 0000 0001

0x801 +4094 0111 1111 1110 0 0x7FE +2046 +1.0230V

1100 0000 0011

0xC03 +2050 0000 0000 0010 0 0x002 +2 +0.0010V

1100 0000 0001

0xC01 +2049 0000 0000 0001 0 0x001 +1 +0.0005V

1100 0000 0000

0xC00 +2048 0000 0000 0000 0 0x000 0 +0.0000V

0100 0000 0000

0x400 +2047 1111 1111 1111 0 0xFFF -1 -0.0005V

0100 0000 0001

0x401 +2046 1111 1111 1110 0 0xFFE -2 -0.0010V

0000 0000 0001

0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235V

0000 0000 0000

0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V

0000 0000 0000

0x000 0 1000 0000 0000 1 0x800 -2048

<-1.0240V

(DATA OUT OF

RANGE)

EQUIVALENT OF

H EXA D EC IM A L

EQ U IVA L EN T O F

DOR

EQ U IVA L EN T O F

HEXADECIMAL

DOR

MAX19538

12-Bit, 95Msps, 3.3V ADC

20 ______________________________________________________________________________________

Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion

BINARY-TO-GRAY-CODE CONVERSION

1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT.

0111 0100 1100 BINARY

GRAY CODE0

2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

D11 D7 D3 D0

GRAYX = BINARYX +BINARY

X + 1

BIT POSITION

0 111 0100 1100 BINARY

GRAY CODE0

D11 D7 D3 D0

BIT POSITION

GRAY

= BINARY10BINARY

GRAY10 = 1 0

GRAY

= 1

3) REPEAT STEP 2 UNTIL COMPLETE:

01 11 0100 1100 BINARY

GRAY CODE0

D11 D7 D3 D0

BIT POSITION

GRAY

= BINARY9BINARY

GRAY9 = 1 1

GRAY

= 0

4) THE FINAL GRAY-CODE CONVERSION IS:

0111 0100 1100 BINARY

GRAY CODE0

D11 D7 D3 D0

BIT POSITION

1001101 1010

GRAY-TO-BINARY-CODE CONVERSION

1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT.

2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

D11 D7 D3 D0

BINARYX = BINARY

X+1

BIT POSITION

BINARY

= BINARY11GRAY

BINARY10 = 0 1

BINARY

= 1

3) REPEAT STEP 2 UNTIL COMPLETE:

4) THE FINAL BINARY CONVERSION IS:

0100 1110 1010

BINARY

GRAY CODE

D11 D7 D3 D0

BIT POSITION

0 BINARY

GRAY CODE0100 11 011010

BINARY

= BINARY10GRAY

BINARY9 = 1 0

BINARY

= 1

GRAY

0 100 1110 1010

BINARY

GRAY CODE

D11 D7 D3 D0

BIT POSITION

01 00 1110 1010

BINARY

GRAY CODE

D11 D7 D3 D0

BIT POSITION

0111 0100 1100

AB Y=AB

00 01 10 11

0 1 1 0

EXCLUSIVE OR TRUTH TABLE

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION:

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 21

Power-Down Input (PD)

The MAX19538 has two power modes that are controlled with the power-down digital input (PD). With PD low, the MAX19538 is in normal operating mode. With PD high, the MAX19538 is in power-down mode.

The power-down mode allows the MAX19538 to efficiently use power by transitioning to a low-power state when conversion is not required. Additionally, the MAX19538 parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed.

In power-down mode, all internal circuits are off, the analog supply current reduces to 0.02mA, and the digital supply current reduces to 1µA. The following list shows the state of the analog inputs and digital outputs in power-down mode:

• INP, INN analog inputs are disconnected from the

internal input amplifier (Figure 3).

• REFOUT has approximately 17kΩ to GND.

• REFP, COM, REFN go high impedance with respect

to V

and GND, but there is an internal 4kΩ resistor

between REFP and COM, as well as an internal 4kΩ resistor between REFN and COM.

Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist

MAX19538

N.C. N.C.

MINI-CIRCUITS

ADT1-1WT

N.C.

0.1μF

MINI-CIRCUITS

ADT1-1WT

0Ω*

5.6pF**

2.2μF

INP

COM

INN

110

0.1%

110

0.1%

0.5%

*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE BANDWIDTH.

**TUNE THESE CAPACITORS FROM 5.6pF TO 18pF IN ORDER TO OPTIMIZE DYNAMIC PERFORMANCE VARIATIONS DUE TO: PRINTED CIRCUIT BOARD (PCB) LAYOUT ANALOG INPUT SIGNAL POWER ANALOG INPUT CARRIER FREQUENCY

Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist

MAX19538

N.C.

0.1μF

MINI-CIRCUITS TT1-6 OR T1-1T

24.9

12pF

2.2μF

INP

COM

INN

Figure 12. Single-Ended, AC-Coupled Input Drive

MAX19538

5.6pF

2.2μF

INP

COM

INN

24.9

100

0.1μF

MAX4108

MAX19538

12-Bit, 95Msps, 3.3V ADC

22 ______________________________________________________________________________________

Figure 13. External Buffered Reference Driving Multiple ADCs

MAX19538

NOTE:

ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT.

*PLACE THE 1μF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.

16.2k

0.1μF

1μF

2.048V

+3.3V

1.47k

+3.3V

10μF 6V

330μF 6V

+3.3V

2.2μF

0.1μF

1μF* 10μF

0.1μF

REFP

REFN

COM

GND

REFIN

REFOUT

MAX19538

+3.3V

2.2μF

0.1μF

1μF* 10μF

0.1μF

REFP

REFN

COM

GND

REFIN

REFOUT

MAX6029EUK21

MAX4230

• D11–D0, DOR, and DAV go high impedance.

• CLKP, CLKN go high impedance (Figure 5).

The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode the wake-up time is typically 10ms with the recommended capacitor array (Figure 13). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers.

Applications Information

Using Transformer Coupling

In general, the MAX19538 provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to singleended input mode.

An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX19538 for optimum performance. Connecting the center tap of the transformer to COM provides a V

/ 2 DC level

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 23

shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 10 is good for frequencies up to Nyquist (f

CLK

/ 2).

The circuit of Figure 11 converts a single-ended input signal to fully differential just as Figure 10. However Figure 11 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent 50Ω termi-

nation to the signal source, as the ADT1-1WT transformer has a 1:1.5 impedance ratio. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input frequencies. These 0Ω resistors can be replaced with lowvalue resistors to limit the input bandwidth.

Single-Ended AC-Coupled Input Signal

Figure 12 shows an AC-coupled, single-ended input application. The MAX4108 operational amplifier provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.

Figure 14. External Unbuffered Reference Driving Multiple ADCs

MAX19538

*PLACE THE 1μF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.

0.1μF

2.413V

+3.3V

47Ω

1.47kΩ

+3.3V

10μF 6V

330μF 6V

+3.3V

2.2μF

0.1μF

1μF*

10μF

0.1μF

REFOUT

REFN

REFIN

GND

COM

REFP

MAX6029EUK30

MAX4230

0.1μF

0.47μF

1.647V

47Ω

1.47kΩ

+3.3V

10μF 6V

330μF 6V

MAX4230

0.1μF

0.880V

47Ω

1.47kΩ

+3.3V

10μF 6V

330μF 6V

MAX4230

MAX19538

+3.3V

2.2μF

0.1μF

1μF*

10μF

0.1μF

REFOUT

REFN

REFIN

GND

COM

REFP

3.000V

20kΩ 1%

52.3kΩ 1%

20kΩ 1%

0.1μF

2.2μF

MAX19538

12-Bit, 95Msps, 3.3V ADC

24 ______________________________________________________________________________________

Buffered External Reference Drives

Multiple ADCs

The buffered external reference mode allows for more control over the MAX19538 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ.

Figure 13 uses the MAX6029EUK21 precision 2.048V reference as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a one-pole, 10Hz lowpass filter to the MAX4230. The MAX4230 buffers the 2.048V reference and provides additional 10Hz lowpass filtering before its output is applied to the REFIN input of the MAX19538.

Unbuffered External Reference Drives

Multiple ADCs

The unbuffered external reference mode allows for precise control over the MAX19538 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources.

Figure 14 uses the MAX6029EUK30 precision 3.000V reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47µF capacitor along this chain creates a 10Hz lowpass filter. Three MAX4230 operational amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and

0.880V to the MAX19538’s REFP, COM, and REFN reference inputs, respectively. The feedback around the MAX4230 op amps provides additional 10Hz lowpass filtering. The 2.413V and 0.880V reference voltages set the full-scale analog input range to ±1.022V = ±(V

REFP

- V

REFN

) x 2/3.

A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down

Grounding, Bypassing,

and Board Layout

The MAX19538 requires high-speed board layout design techniques. Refer to the MAX1211 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass VDDto GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass OV

to GND with a 0.1µF ceramic capacitor in parallel with a

2.2µF ceramic capacitor.

Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX19538 GNDs and the exposed backside paddle must be connected to the same ground plane. The MAX19538 relies on the exposed backside paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground.

Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns.

Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1211 evaluation kit data sheet for an example of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX19538, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX19538, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX19538 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally the positive full-scale MAX19538 transition occurs at 1.5

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 25

LSB below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.

Small-Signal Noise Floor (SSNF)

Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to www.maxim-ic.com for application notes on thermal + quantization noise floor.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):

SNR

[max]

= 6.02 × N + 1.76

In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 to HD7), and the DC offset:

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. RMS distortion includes the first six harmonics (HD2–HD7):

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from:

Single-Tone Spurious-Free

Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V7are the amplitudes of the 2nd- through 7th-order harmonics (HD2–HD7).

Intermodulation Distortion (IMD)

IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as:

The fundamental input tone amplitudes (V1and V2) are at -7dBFS. Fourteen intermodulation products (VIM_) are used in the MAX19538 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where f

IN1

and

IN2

are the fundamental input tone frequencies:

• Second-order intermodulation products: f

IN1

+ f

IN2

, f

IN2

- f

IN1

• Third-order intermodulation products: 2 x f

IN1

- f

IN2

, 2 x f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

• Fourth-order intermodulation products: 3 x f

IN1

- f

IN2

, 3 x f

IN2

- f

IN1

, 3 x f

IN1

+ f

IN2

, 3 x f

IN2

+ f

IN1

IMD

VV V V

IM IM IM IM

log

...........

=×

++++

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

THD

VVVVVV

log=×

+++++

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

22324

2526272

ENOB

SINAD

⎛ ⎝

⎜

⎞ ⎠

⎟

−

..176

602

SINAD

SIGNAL

NOISE DISTORTION

RMS

RMS RMS

=×

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

log20

SNR

SIGNAL

NOISE

RMS

=×

⎛ ⎝

⎜

⎞ ⎠

⎟

log20

MAX19538

12-Bit, 95Msps, 3.3V ADC

26 ______________________________________________________________________________________

• Fifth-order intermodulation products: 3 x f

IN1

- 2 x f

IN2

, 3 x f

IN2

- 2 x f

IN1

, 3 x f

IN1

+ 2 x f

IN2

3 x f

IN2

+ 2 x f

IN1

Third-Order Intermodulation (IM3)

IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f

IN1

and f

IN2

. The

individual input tone levels are at -7dBFS. The thirdorder intermodulation products are 2 × f

IN1

- f

IN2

, 2 ×

IN2

- f

IN1

, 2 × f

IN1

+ f

IN2

, 2 × f

IN2

+ f

IN1

Two-Tone Spurious-Free

Dynamic Range (SFDR

)

SFDRTTrepresents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic.

Aperture Delay

The MAX19538 samples data on the falling edge of its sampling clock. In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (t

) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 4).

Aperture Jitter

Figure 4 depicts the aperture jitter (tAJ), which is the

sample-to-sample variation in the aperture delay.

Output Noise (n

OUT

)

The output noise (n

OUT

) parameter is similar to the thermal + quantization noise parameter and is an indication of the ADC’s overall noise performance.

No fundamental input tone is used to test for n

OUT

; INP, INN, and COM are connected together and 1024k data points collected. n

OUT

is computed by taking the RMS value of the collected data points after the mean is removed.

Overdrive Recovery Time

Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX19538 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%.

REFP 1

REFN 2

COM 3

GND 4

INP 5

INN 6

GND 7

DCE 8

CLKN 9

CLKP 10

D030

D129

D228

D327

D426

D525

D624

D723

D822

D921

REFIN39REFOUT38PD37V

GND35OV

DAV33I.C.32I.C.

CLKTYP

GND

DOR

D1119D10

G/T

TOP VIEW

MAX19538

EXPOSED PADDLE (GND)

THIN QFN

6mm x 6mm x 0.8mm

Pin Configuration

MAX19538

12-Bit, 95Msps, 3.3V ADC

______________________________________________________________________________________ 27

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages

QFN THIN.EPS

MAX19538

12-Bit, 95Msps, 3.3V ADC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages

MAXIM MAX19538 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual