MAXIM MAX19527 Technical data

19-5309; Rev 0; 6/10

EVALUATION KIT

AVAILABLE

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

General Description

The MAX19527 is an octal, 12-bit analog-to-digital converter (ADC), optimized for the low-power and high-dynamic performance requirements of medical imaging instrumentation and digital communications applications. The device operates from a single 1.8V supply and consumes 440mW (55mW per channel), while providing a 69dBFS signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the device features programmable power management for idle states and reduced-channel operation.

An internal 1.25V precision bandgap reference sets the full-scale range of the ADC to 1.5V ence structure allows the use of an external reference for applications requiring greater gain accuracy or a different input voltage range. A programmable commonmode voltage reference output is provided to enable DC-coupled input applications.

Various adjustments and feature selections are available through programmable registers that are accessed through the 3-wire serial peripheral interface (SPIK).

A flexible clock input circuit allows for a single-ended, logic-level clock or a differential clock signal. An on-chip PLL generates the multiplied (6x) clock required for the serial LVDS digital outputs. The serial LVDS output provides programmable test patterns for data timing alignment and output drivers with programmable current drive and programmable internal termination.

The device is available in a small, 10mm x 10mm x

1.2mm, 144-lead thin chip ball grid array (CTBGA) package and is specified for the extended industrial (-40NC to +85NC) temperature range.

. A flexible refer-

P-P

MAX19527

Features

S Ultra-Low-Power Operation

55mW per Channel at 50Msps

S Single 1.8V Power Supply

S Excellent Dynamic Performance

69dBFS SNR at 5.3MHz 140dBc/Hz Near-Carrier SNR at 1kHz Offset from a 5.3MHz Tone 84dBc SFDR at 5.3MHz 90dB Channel Isolation at 5.3MHz

S User-Programmable Adjustment and Feature

Selection through an SPI Interface

S Serial LVDS Outputs with Programmable Current

Drive and Internal Termination

S Programmable Power Management

S Internal or External Reference Operation

S Single-Ended or Differential Clock Input

S Programmable Output Data Format

S Built-In Output Data Test Patterns

S Small, 10mm x 10mm, 144-Lead CTBGA Package

S Evaluation Kit Available (Order MAX19527EVKIT+)

Applications

Ultrasound and Medical Imaging

Instrumentation

Multichannel Communications

ZIF GSM and TD-SCDMA Transceivers

SPI is a trademark of Motorola, Inc.

_______________________________________________________________ Maxim Integrated Products 1

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX19527EXE+

+Denotes a lead(Pb)-free/RoHS-compliant package.

-40NC to +85NC

144 CTBGA

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

ABSOLUTE MAXIMUM RATINGS

AVDD, OVDD to GND ......................................... -0.3V to +2.1V

OGND to GND ......................................................-0.3V to +0.3V

IN_+, IN_-, CMOUT, REFIO, REFH,

REFL, CLKIN+, CLKIN- to GND ..............-0.3V to the lower of

(V

+ 0.3V) and +2.1V

OUT_+, OUT_-, FRAME+,

FRAME-, CLKOUT+, CLKOUT-,

SHDN, CS, SCLK, SDIO to GND .............-0.3V to the lower of

MAX19527

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD

(V

+ 0.3V) and +2.1V

OVDD

ELECTRICAL CHARACTERISTICS

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution 12 Bits Integral Nonlinearity INL fIN = 5.3MHz Differential Nonlinearity DNL fIN = 5.3MHz, no missing codes Offset Error OE Internal reference Gain Error GE External reference = 1.25V

ANALOG INPUTS (IN_+, IN_-) (Figure 2)

Input Differential Range V

Common-Mode Input Voltage Range

Input Resistance R

Input Current I

Input Capacitance

CONVERSION RATE

Maximum Clock Frequency f Minimum Clock Frequency f

Data Latency Figure 5 8.5

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

DIFF

V

C

SAMPLE

CLK

IN_+ - IN_- 1.5 V

Q50mV tolerance

CM

Fixed resistance to GND > 100

Differential input resistance, common

IN

mode connected to inputs

Switched capacitance input current,

IN

each input, V

Fixed capacitance to GND, each input 1

INS

Fixed differential capacitance 0.2

IND

Switched capacitance, each input 1.5

CM

Continuous Power Dissipation (TA = +70NC)

144-Lead CTBGA (derate 37mW/NC above +70NC)

Multilayer Board ...................................................... 2963mW

Operating Temperature Range ......................... -40NC to +85NC

Junction Temperature ....................................................+150NC

Storage Temperature Range .......................... -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

= 1.050V

CLKD

= 1.5V

, f

P-P

50 MHz

= 50MHz, programmable

CLK

Q0.5 Q1.7 Q0.3 Q1.0

Q0.07 Q0.7

Q0.2 Q3.0

1050 mV

4

36

25 MHz

LSB

LSB %FS %FS

P-P

kI

FA

pFC

Clock

Cycles

2

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DYNAMIC PERFORMANCE

Small-Signal Noise Floor SSNF Analog input < -35dBFS, fIN = 5.3MHz -69.5 dBFS

Near-Carrier Signal-to-Noise Ratio

Signal-to-Noise Ratio SNR

Signal-to-Noise and Distortion Ratio

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Intermodulation Distortion IMD

Full-Power Bandwidth FPBW

Overdrive Recovery Time

INTERCHANNEL CHARACTERISTICS

Crosstalk fIN = 5.3MHz at -0.5dBFS -90 dB Gain Matching fIN = 5.3MHz Phase Matching fIN = 5.3MHz

ANALOG OUTPUT (CMOUT)

CMOUT Output Voltage V

INTERNAL REFERENCE

REFIO Output Voltage V REFIO Temperature Coefficient TC REFH Voltage V REFL Voltage V

EXTERNAL REFERENCE

REFIO Input Voltage Range V REFIO Input Resistance R

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

1kHz offset from 5.3MHz full-scale tone, C

NCSNR

SINAD

CMOUT

REFIO

REF

REFH

REFL

REFIN

= C

REFIO

(Figure 3)

8-channel coherent sum 147 fIN = 5.3MHz at -0.5dBFS 67.0 68.5 fIN = 19.3MHz at -0.5dBFS 68.5 fIN = 5.3MHz at -0.5dBFS 66.6 68.2 fIN = 19.3MHz at -0.5dBFS 68.2 fIN = 5.3MHz at -0.5dBFS 70.0 84 fIN = 19.3MHz at -0.5dBFS 84 fIN = 5.3MHz at -0.5dBFS -81 -72 fIN = 19.3MHz at -0.5dBFS -81

f

= 5.15MHz at -6.5dBFS,

IN1

f

= 5.45MHz at -6.5dBFS

IN2

R

SOURCE

6dB beyond full scale (recover accuracy to < 1% of full scale)

Default programming state 1.05 1.10 1.15 V

Bypass only, no DC load 1.22 1.25 1.28 V

Bypass only, no DC load 1.61 V Bypass only, no DC load 0.86 V

+5%/-15% tolerance 1.25 V

REFH/REFL

= 50I differential

= 0.1FF

CLKD

= 1.5V

, f

P-P

= 50MHz, programmable

CLK

140

-83 dB

> 500 MHz

< 1

Q0.1

Q0.25

< Q60 ppm/NC

10 Q 20% kI

dBc/Hz

dB

dBc

Clock

Cycles

dB

Degrees

MAX19527

3

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLOCK INPUTS (CLKIN+, CLKIN-)—DIFFERENTIAL MODE (Figure 4)

Differential Clock Input Voltage V

Common-Mode Voltage V

MAX19527

Input Resistance R

Input Capacitance C

CLOCK INPUTS (CLKIN+, CLKIN-)—SINGLE-ENDED MODE (CLKIN- < 0.1V) (Figure 4)

Single-Ended Mode Selection Threshold (CLKIN-)

Single-Ended Clock Input High Threshold (CLKIN+)

Single-Ended Clock Input Low Threshold (CLKIN+)

Input Leakage (CLKIN+)

Input Leakage (CLKIN-) I Input Capacitance (CLKIN+) 3 pF

DIGITAL INPUTS (SHDN, SCLK, SDIN, CS)

Input High Threshold V Input Low Threshold V

Input Leakage

Input Capacitance C

DIGITAL OUTPUTS (SDIO)

Output Voltage Low V

Output Voltage High V

LVDS DIGITAL OUTPUTS (OUT_+/OUT_-, CLKOUT+/CLKOUT-, FRAME+/FRAME-)

Differential Output Voltage |VOD| Output Offset Voltage V

POWER-MANAGEMENT CHARACTERISTICS (Figure 3)

Wake-Up Time from Sleep Mode t

Wake-Up Time from Nap Mode t

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

CLKD

CLKCM

V

I

SWAKE

NWAKE

Self-biased 1.2 DC-coupled clock signal 1.0 to 1.4 Differential, default setting 10

Differential, programmable internal

CLK

termination selected

Common mode to GND 9 Capacitance to GND, each input 3 pF

CLK

IL

IH

IL

VIH = 1.8V +5

IH

I

VIH = 0V -5

IL

VIH = 0V -150 -50

IL

IH

IL

VIH = 1.8V +5

IH

I

VIL = 0V -5

IL

DIN

I

OL

OH

OS

= 200FA

SINK

I

SOURCE

External R External R

Internal reference, C C with respect to steady-state gain

= 200FA

REFH/REFL

= 100I

LOAD

= 100I

LOAD

REFIO

= 0.1FF; Q1% gain error,

REFIO

= 0.1FF; Q1% gain error,

= 0.1FF,

= 1.5V

CLKD

OVDD -

250 450 mV

1.125 1.375 V

, f

P-P

1.5 V

0.2

= 50MHz, programmable

CLK

0.4 to 2.0 V

0.1

3 pF

10 ms

2

0.1 V

0.3 V

0.2 V

P-P

V

kI

FA

V

Fs

4

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9, Note 2)

SCLK Period t SCLK to CS Setup Time SCLK to CS Hold Time

SDIO to SCLK Setup Time t SDIO to SCLK Hold Time t SCLK to SDIO Output Data Delay t

TIMING CHARACTERISTICS (Figures 6 and 7, Note 2)

Data Valid to CLKOUT Rise/Fall t

CLKOUT Output-Width High t CLKOUT Output-Width Low t

FRAME Rise to CLKOUT Rise t

Sample CLK Rise to Frame Rise t

POWER REQUIREMENTS

Analog Supply Voltage V Digital Output Supply Voltage V

Analog Supply Current I

Digital Output Supply Current I

Total Power Dissipation P

Note 1: Specifications are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and

characterization.

Note 2: Specifications guaranteed by design and characterization.

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

SCLK

t

CSS

t

CSH

SDS

SDH

SDD

AVDD

OVDD

AVDD

OVDD

Serial-data write 10 ns Serial-data write 0 ns Serial-data read 10 ns

OD

CH

CL

DF

SF

8 channels active 158 180 Incremental channel power-down -18 Nap mode 13 15 Sleep mode 0.35 0.5 8 channels active, external R Incremental channel power-down -7.4 Nap mode 28 Sleep mode < 0.1 8 channels active 440 Incremental channel power-down -46

TD

Nap mode 74 Sleep mode 0.8

LOAD

CLKD

= 100I

= 1.5V

t

SAMPLE

24 - 0.10

t

SAMPLE

24 - 0.10

t

SAMPLE

2 + 1.6

, f

P-P

50 ns 10 ns 10 ns

/

1.7 1.8 1.9 V

= 50MHz, programmable

CLK

t

24 + 0.05

t

SAMPLE

t

SAMPLE

t

SAMPLE

24 + 0.05

t

SAMPLE

/

SAMPLE

2 + 2.3

t

24 + 0.20

/12 ns /12 ns

/

t

24 + 0.20

/

t

87

SAMPLE

2 + 3.3

/

ns

/

ns

/

ns

mA

mW

MAX19527

5

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

Typical Operating Characteristics

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted. Specifications are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization.)

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

CLKD

= 1.5V

P-P

, f

= 50MHz, programmable

CLK

0

-10

-20

MAX19527

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110 0 25

FREQUENCY (MHz)

TWO-TONE INTERMODULATION

DISTORTION

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110 0 25

FREQUENCY (MHz)

5.3MHz INPUT FFT PLOT

fIN = 5.301324MHz

AIN = -0.49dBFS

SNR = 68.58dB SINAD = 68.35dB THD = -81.19dBc

SFDR = 85.17dB

2015105

f

= 5.154828MHz

IN1

f

= 5.423404MHz

IN2

A

= -6.95dBFS

IN1

A

= -7.02dBFS

IN2

IM3 = -83dBc

2015105

MAX19527 toc01

AMPLITUDE (dBFS)

-100

-110

MAX19527 toc04

AMPLITUDE (dBFS)

-100

-110

-120

19.3MHz INPUT FFT PLOT

0

fIN = 19.303900MHz

-10 AIN = -0.51dBFS

-20

SNR = 68.49dB SINAD = 68.24dB

-30 THD = -80.90dBc

-40 SFDR = 85.73dB

-50

-60

-70

-80

-90

0 25

FREQUENCY (MHz)

5.3MHz INPUT FFT PLOT

8-CHANNEL COHERENT SUM

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0 25

FREQUENCY (MHz)

fIN = 5.301324MHz

A

= -0.50dBFS

IN

SNR = 77.20dB SINAD = 76.84dB THD = -87.80dBc

SFDR = 89.31dB

0

-10

-20

MAX19527 toc02

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

2015105

0 25

MEASURED ON CHANNEL 1,

WITH INTERFERING SIGNAL

FREQUENCY (MHz)

ON CHANNEL 2

f

= 5.301324MHz

IN(IN1)

f

= 19.303900MHz

IN(IN2)

= -0.5dBFS

A

IN(IN1)

A

= -0.5dBFS

IN(IN2)

CROSSTALK = -92dB

f

= 19.3039MHz

IN(IN2)

MAX19527 toc03

2015105

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

0.8

CROSSTALK FFT PLOT

MAX19527 toc05

0.6

0.4

0.2

0

INL (LSB)

-0.2

-0.4

-0.6

-0.8

2015105

-1.0 0 4096

DIGITAL OUTPUT CODE

MAX19527 toc06

358430722048 25601024 1536512

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0 0 4096

DIGITAL OUTPUT CODE

6

DYNAMIC PERFORMANCE

vs. INPUT FREQUENCY

90

85

MAX19527 toc07

80

75

70

DYNAMIC PERFORMANCE (dB)

65

358430722048 25601024 1536512

60

0 200

SFDR

-THD

SNR

SINAD

15010050

INPUT FREQUENCY (MHz)

90

80

MAX195027 toc08

70

60

50

40

30

DYNAMIC PERFORMANCE (dB)

20

10

DYNAMIC PERFORMANCE vs. ANALOG INPUT POWER

SFDR

-THD

SNR

SINAD

-50 0 ANALOG INPUT POWER (dBFS)

-5-10-45 -40 -35 -25 -20-30 -15

MAX19527 toc09

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

Typical Operating Characteristics (continued)

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted. Specifications are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization.)

DYNAMIC PERFORMANCE

90

85

80

75

70

DYNAMIC PERFORMANCE (dB)

65

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

DYNAMIC PERFORMANCE

vs. SAMPLING RATE

SFDR

MAX19527 toc10

-THD

SNR

SINAD

vs. INPUT COMMON-MODE VOLTAGE

90

85

80

75

70

DYNAMIC PERFORMANCE (dB)

65

SFDR

-THD

SNR

SINAD

= 1.5V

CLKD

MAX19527 toc11

P-P

90

85

80

75

70

DYNAMIC PERFORMANCE (dB)

65

, f

= 50MHz, programmable

CLK

DYNAMIC PERFORMANCE

vs. ANALOG SUPPLY VOLTAGE

SFDR

-THD

SNR

SINAD

MAX19527

MAX19527 toc12

60

25 50

SAMPLING RATE (MHz)

DYNAMIC PERFORMANCE

vs. CLOCK DUTY CYCLE

90

85

80

75

70

DYNAMIC PERFORMANCE (dB)

65

60

SFDR

-THD

SNR

SINAD

SINGLE-ENDED CLOCK MODE

CLOCK DUTY CYCLE (%)

+6dB OVERDRIVE

OUTPUT CODE vs. SIGNAL PHASE

4096

3584

3072

2560

2048

1536

1024

+6dB OVERDRIVE OUTPUT CODE

512

CLIPPED AT

4095

CLIPPED AT

0

0 360

SIGNAL PHASE (DEGREES)

240 30018060 120

45403530

60555045403530 70

65

fIN = 5.3MHz

AIN = +6dBFS

0

60

INPUT COMMON-MODE VOLTAGE (V)

90

85

MAX19527 toc13

80

75

70

DYNAMIC PERFORMANCE (dB)

65

60

-40 85

1.00

0.75

MAX19527 toc16

0.50

0.25

0

-0.25

-0.50

+6dB OVERDRIVE ERROR (LSB)

-0.75

-1.00 0 360

1.051.000.95 1.15

1.10

DYNAMIC PERFORMANCE

vs. TEMPERATURE

SFDR

-THD

SNR

SINAD

TEMPERATURE (°C)

+6dB OVERDRIVE

ERROR vs. SIGNAL PHASE

fIN = 5.3MHz

AIN = +6dBFS

CLIPPED AT

4095

SIGNAL PHASE (DEGREES)

CLIPPED AT

240 30018060 120

60

V

AVDD

(V)

1.851.801.751.701.65 1.95

1.90

NEAR-CARRIER NOISE SPECTRUM

vs. FREQUENCY OFFSET

-120

MAX19527 toc14

-130

-140

-150

NEAR-CARRIER NOISE SPECTRUM (dBC/Hz)

603510-15

-160

-5 5

8-CHANNEL

COHERENT SUM

FREQUENCY OFFSET (kHz)

SINGLE

CHANNEL

31-1-3

MAX19527 toc15

ANALOG SUPPLY CURRENT

vs. SAMPLING RATE (AVDD)

180

160

MAX19527 toc17

140

120

100

80

60

0

ANALOG SUPPLY CURRENT (mA)

1 CHANNEL

40

20

0

25 50

8 CHANNELS

MAX19527 toc18

7 CHANNELS

4 CHANNELS

NAP MODE

45403530

SAMPLING RATE (MHz)

7

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

CMOUT VOLTAGE (V)

1.8V ADC with Serial LVDS Outputs

Typical Operating Characteristics (continued)

(V

= 1.8V, V

AVDD

registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted. Specifications are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization.)

ANALOG SUPPLY CURRENT vs. TEMPERATURE (AVDD)

180

175

170

MAX19527

165

160

155

150

ANALOG SUPPLY CURRENT (mA)

145

140

-40 85

DIGITAL SUPPLY CURRENT vs. TEMPERATURE (OVDD)

95

= 1.8V, internal reference, AIN = -0.5dBFS, differential clock, V

OVDD

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE (AVDD)

170

165

MAX19527 toc19

160

155

150

ANALOG SUPPLY CURRENT (mA)

145

140

6035-15 10

TEMPERATURE (°C)

1.65 1.95 SUPPLY VOLTAGE (V)

DIGITAL SUPPLY CURRENT

vs. SUPPLY VOLTAGE (OVDD)

100

CLKD

= 1.5V

P-P

, f

= 50MHz, programmable

CLK

DIGITAL SUPPLY CURRENT

vs. SAMPLING RATE (OVDD)

100

90

MAX19527 toc20

80

70

60

50

40

30

DIGITAL SUPPLY CURRENT (mA)

20

10

0

1.901.851.801.751.70

25 50

8 CHANNELS

7 CHANNELS

4 CHANNELS

1 CHANNEL

NAP MODE

SAMPLING RATE (MHz)

REFERENCE VOLTAGE

vs. TEMPERATURE

1.260

MAX19527 toc21

45403530

90

85

80

DIGITAL SUPPLY CURRENT (mA)

75

-40 85 TEMPERATURE (°C)

CMOUT VOLTAGE

vs. TEMPERATURE

1.18

1.16

1.14

1.12

1.10

1.08

1.06

CMOUT VOLTAGE (V)

1.04

1.02

1.00

111

110

101

100

011

010

001

000

-40 80

TEMPERATURE (°C)

8

603510-15

CMI_ADJ[2:0]

6040200-20

95

MAX19527 toc22

90

85

80

DIGITAL SUPPLY CURRENT (mA)

75

70

1.65 1.95

1.12

MAX19527 toc25

1.11

1.10

1.09

1.08

1.07 0 1000

1.901.851.801.751.70

SUPPLY VOLTAGE (V)

CMOUT VOLTAGE

vs. CMOUT LOAD CURRENT

800600400200

CMOUT LOAD CURRENT (µA)

MAX19527 toc23

1.255

1.250

1.245

REFERENCE VOLTAGE (V)

1.240

1.230

-40 85

50

45

MAX19527 toc26

40

35

30

ANALOG INPUT CURRENT (µA)

25

20

0.95 1.15

MAX19527 toc24

603510-15

TEMPERATURE (°C)

ANALOG INPUT CURRENT

vs. INPUT COMMON-MODE

VOLTAGE (AVDD)

MAX19527 toc27

1.101.051.00

INPUT COMMON-MODE VOLTAGE (V)

Ultra-Low-Power, Octal, 12-Bit, 50Msps,

1.8V ADC with Serial LVDS Outputs

Pin Configuration

TOP VIEW

REFLN.C. N.C.N.C. OGNDN.C.N.C. N.C. REFH REFIO OVDDAVDD

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

SHDNN.C. N.C. N.C. N.C. N.C. N.C. OUT1+AVDD I.C. OUT1-N.C.

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

IN1- GNDGND GNDIN1+ GND GND GND GND OGND OUT2+ OUT2-

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

GND OGND OUT3+ OUT3-IN2- GND GND GND GND GND GNDIN2+

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12

GND OGND OUT4+ OUT4-IN3- GND GND GND GND GND GNDIN3+

E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12

GND OVDD CLKOUT+ CLKOUT-IN4- CMOUT GND GND GND AVDD GNDIN4+

F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12

GND OVDD FRAME+ FRAME-IN5- CMOUT GND GND GND AVDD GNDIN5+

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12

GND OGND OUT5+ OUT5-IN6- GND GND GND GND GND GNDIN6+

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12

GND OGND OUT6+ OUT6-IN7- GND GND GND GND GND GNDIN7+

J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12

GND OGND OUT7+ OUT7-IN8- GND GND GND GND GND GNDIN8+

K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12

SDION.C. N.C.N.C. OUT8+N.C. N.C.N.C. GND OUT8-AVDD CLKIN+

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

SCLKN.C. N.C.N.C. CSN.C. N.C.N.C. GND OVDDAVDD CLKIN-

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

MAX19527

Pin Description

PIN NAME FUNCTION

ANALOG INPUTS

C1 IN1- Channel 1 Negative (Inverting) Analog Input C2 IN1+ Channel 1 Positive (Noninverting) Analog Input D1 IN2- Channel 2 Negative (Inverting) Analog Input D2 IN2+ Channel 2 Positive (Noninverting) Analog Input E1 IN3- Channel 3 Negative (Inverting) Analog Input E2 IN3+ Channel 3 Positive (Noninverting) Analog Input

F1 IN4- Channel 4 Negative (Inverting) Analog Input F2 IN4+ Channel 4 Positive (Noninverting) Analog Input

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