General Description
The MAX19515 dual-channel, analog-to-digital converter (ADC) provides 10-bit resolution and a maximum
sample rate of 65Msps.
The MAX19515 analog input accepts a wide 0.4V to
1.4V input common-mode voltage range, allowing DCcoupled inputs for a wide range of RF, IF, and baseband front-end components. The MAX19515 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and highintermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is
60.1dBFS and typical spurious-free dynamic range
(SFDR) is 82dBc at fIN= 70MHz and f
CLK
= 65MHz.
The MAX19515 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 43mW per channel at V
AVDD
= 1.8V. In addition to low operating
power, the MAX19515 consumes only 1mW in powerdown mode and 15mW in standby mode.
Various adjustments and feature selections are available through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three pins available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible output data bus that can also be configured as a single
multiplexed parallel CMOS bus.
The MAX19515 is available in a small 7mm x 7mm 48pin thin QFN package and is specified over the -40°C
to +85°C extended temperature range.
Refer to the MAX19505, MAX19506, and MAX19507
data sheets for pin- and feature-compatible 8-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19516 and MAX19517 data sheets for
pin- and feature-compatible 10-bit, 100Msps and
130Msps versions, respectively.
Applications
IF and Baseband Communications, Including
Cellular Base Stations and Point-to-Point
Microwave Receivers
Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data
Acquisition
Digital Set-Top Boxes
Features
o Very-Low-Power Operation (43mW/Channel at
65Msps)
o 1.8V or 2.5V to 3.3V Analog Supply
o Excellent Dynamic Performance
60.1dBFS SNR at 70MHz
82dBc SFDR at 70MHz
o User-Programmable Adjustments and Feature
Selection through an SPI™ Interface
o Selectable Data Bus (Dual CMOS or Single
Multiplexed CMOS)
o DCLK Output and Programmable Data Output
Timing Simplifies High-Speed Digital Interface
o Very Wide Input Common-Mode Voltage Range
(0.4V to 1.4V)
o Very High Analog Input Bandwidth (> 850MHz)
o Single-Ended or Differential Analog Inputs
o Single-Ended or Differential Clock Input
o Divide-by-One (DIV1), Divide-by-Two (DIV2), and
Divide-by-Four (DIV4) Clock Modes
o Two’s Complement, Gray Code, and Offset Binary
Output Data Format
o Out-of-Range Indicator (DOR)
o CMOS Output Internal Termination Options
(Programmable)
o Reversible Bit Order (Programmable)
o Data Output Test Patterns
o Small 7mm x 7mm 48-Pin Thin QFN Package with
Exposed Pad
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4195; Rev 3; 1/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX19515ETM+ -40°C to +85°C 48 TQFN-EP*
-40°C to +85°C 48 TQFN-EP*
/
V denotes an automotive qualified part.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc.
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OVDD, AVDD to GND............................................-0.3V to +3.6V
CMA, CMB, REFIO, INA+, INA-, INB+,
INB- to GND ......................................................-0.3V to +2.1V
CLK+, CLK-, SYNC, SPEN, CS , SCLK, SDIN
to GND ..........-0.3V to the lower of (V
AVDD
+ 0.3V) and +3.6V
DCLKA, DCLKB, D9A–D0A, D9B–D0B, DORA, DORB
to GND..........-0.3V to the lower of (V
OVDD
+ 0.3V) and +3.6V
Continuous Power Dissipation (T
A
= +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C
above +70°C).............................................................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL fIN = 3MHz -0.8 ±0.25 +0.8 LSB
Differential Nonlinearity DNL fIN = 3MHz -0.7 ±0.2 +0.7 LSB
Offset Error OE Internal reference -0.4 ±0.1 +0.4 %FS
Gain Error GE External reference = 1.25V -1.5 ±0.3 +1.5 %FS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)
Differential Input-Voltage Range V
Common-Mode Input-Voltage
Range
Input Resistance R
Input Current I
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency f
Minimum Clock Frequency f
Data Latency Figures 9, 10 9 Cycles
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIFF
V
CM
IN
C
PAR
C
SAMPLE
CLK
CLK
Differential or single-ended inputs 1.5 V
(Note 2) 0.4 1.4 V
Fixed resistance > 100
IN
Differential input resistance, common mode
connected to inputs
Switched capacitance input current, each
input
Fixed capacitance to ground, each input 0.7
Switched capacitance, each input 1.2
4
35 µA
65 MHz
30 MHz
P-P
kΩ
pF
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
DYNAMIC PERFORMANCE
Small-Signal Noise Floor SSNF fIN = 70MHz, < -35dBFS -60.4 dBFS
Signal-to-Noise Plus Distortion
Ratio
Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)
Spurious-Free Dynamic Range
(4th and Higher Harmonics)
Second Harmonic HD2
Third Harmonic HD3
Third-Order Intermodulation IM3
Full-Power Bandwidth FPBW 850 MHz
Aperture Delay t
Aperture Jitter t
Overdrive Recovery Time ±10% beyond full scale 1 Cycles
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 3MHz 60.2
fIN = 70MHz 59.3 60.1 Signal-to-Noise Ratio SNR
= 175MHz 59.8
f
IN
fIN = 3MHz 59.7
SINAD
SFDR1
SFDR2
AD
AJ
fIN = 70MHz 58.8 59.6
= 175MHz 59.3
f
IN
fIN = 3MHz 85
fIN = 70MHz 73 84
f
= 175MHz 81
IN
fIN = 3MHz 82
fIN = 70MHz 74.4 82
= 175MHz 82
f
IN
fIN = 3MHz -86
fIN = 70MHz -86 -73
f
= 175MHz -82
IN
fIN = 3MHz -86
fIN = 70MHz -86 -74
= 175MHz -82
f
IN
fIN = 3MHz -80
fIN = 70MHz -79 -71.8 Total Harmonic Distortion THD
= 175MHz -77
f
IN
fIN = 70MHz ±1.5MHz, -7dBFS -90
= 175MHz ±2.5MHz, -7dBFS -80
f
IN
850 ps
0.3 ps
dBFS
dB
dBc
dBc
dBc
dBc
dBc
dBc
RMS
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
INTERCHANNEL CHARACTERISTICS
Crosstalk
Gain Match fIN = 70MHz ±0.05 dB
Offset Match fIN = 70MHz ±0.1 %FSR
Phase Match fIN = 70MHz ±0.5 D eg r ees
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage V
INTERNAL REFERENCE
REFIO Output Voltage V
REFIO Temperature Coefficient TC
EXTERNAL REFERENCE
REFIO Input-Voltage Range V
REFIO Input Resistance R
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage 0.4 to 2.0 V
Differential Input Common-Mode
Voltage
Input Capacitance C
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V
Single-Ended Mode Selection
Threshold (V
Allowable Logic Swing (V
Single-Ended Clock Input High
Threshold (V
Single-Ended Clock Input Low
Threshold (V
Input Leakage (CLK+)
Input Leakage (CLK-) V
Input Capacitance (CLK+) 3p F
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
f
or f
= 70MHz at -1dBFS 95
INB
or f
= 175MHz at -1dBFS 85
INB
dBc
1.23 1.25 1.27 V
< ±60 ppm/°C
1.25 +5/
-10%
10
±20%
V
kΩ
P-P
V
COM
REFOUT
REF
REFIN
REFIN
INA
f
INA
Default programmable setting 0.85 0.9 0.95 V
Self-biased 1.2
DC-coupled clock signal 1.0 to 1.4
Differential, default 10 kΩ
CLK
Differential, internal termination selected 100 Ω Input Resistance R
Common mode 9 kΩ
To ground, each input 3 pF
< 0.1V)
CLK-
0.1 V
AVDD
1.5 V
0.3 V
V
= V
CLK+
V
= 0V -0.5
CLK+
= 0V -150 -50 µA
CLK-
= 1.8V or 3.3V +0.5
AVDD
µA
V
CLK-
CLK+
CLK+
CLK
)
) 0 - V
CLK+
)
)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
CLOCK INPUT (SYNC)
Allowable Logic Swing 0 - V
Sync Clock Input High Threshold 1.5 V
Sync Clock Input Low Threshold 0.3 V
Input Leakage
Input Capacitance 4.5 pF
DIGITAL INPUTS (SHDN, CS)
Allowable Logic Swing 0 - V
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
Input Leakage
Input Capacitance C
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE
Allowable Logic Swing 0 - V
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
Input Leakage
Input Capacitance C
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = V
Input Pullup Current
Input Pulldown Current
Open-Circuit Voltage V
DIGITAL OUTPUTS (75Ω , D0–D9 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low V
Output-Voltage High V
Three-State Leakage Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AVDD
V
DIN
DIN
OC
OL
OH
LEAK
= V
SYNC
= 0V -0.5
V
SYNC
V
SHDN/VSPEN
V
SHDN/VSPEN
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
= 1.8V 1.35 1.45 1.55
AVDD
V
= 3.3V 2.58 2.68 2.78
AVDD
I
= 200µA 0.2 V
SINK
I
SOURCE
V
applied +0.5
OVDD
GND applied -0.5
= 1.8V or 3.3V +0.5
AVDD
= V
= 1.8V or 3.3V +0.5
AVDD
= 0V -0.5
= V
= 1.8V or 3.3V +0.5
AVDD
= 0V -0.5
)—PARALLEL CONTROL MODE (Figure 5)
AVDD
= V
= V
= 0V, V
= 0V, V
= 200µA
= 1.8V 7 12 17
AVDD
= 3.3V 16 21 26
AVDD
= 1.8V -65 -50 -35
AVDD
= 3.3V -105 -90 -75
AVDD
V
OVDD
- 0.2
AVDD
3p F
AVDD
3p F
V
µA
V
µA
V
µA
µA
µA
V
V
µA
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
POWER-MANAGEMENT CHARACTERISTICS
Wake-Up Time from Shutdown t
Wake-Up Time from Standby t
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
SCLK Period t
SCLK to CS Setup Time t
SCLK to CS Hold Time t
SDIN to SCLK Setup Time t
SDIN to SCLK Hold Time t
SCLK to SDIN Output Data Delay t
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)
Clock Pulse-Width High t
Clock Pulse-Width Low t
Clock Duty Cycle tCH/t
Data Delay After Rising Edge of
CLK+
Data to DCLK Setup Time t
Data to DCLK Hold Time t
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)
Clock Pulse-Width High t
Clock Pulse-Width Low t
Clock Duty Cycle tCH/t
Data Delay After Rising Edge of
CLK+
Data to DCLK Setup Time t
Data to DCLK Hold Time t
DCLK Duty Cycle t
MUX Data Duty Cycle t
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)
Setup Time for Valid Clock Edge t
Hold-Off Time for Invalid Clock
Edge
Minimum Synchronization Pulse
Width
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WAKE
WAKE
SCLK
CSS
CSH
SDS
SDH
SDD
CH
CL
t
DD
SETUP
HOLD
CH
CL
t
DD
SETUP
HOLD
DCH/tCLKCL
CHA/tCLKCL
SUV
t
SDH
Internal reference, C
Internal reference 15 µs
Serial-data write 10 ns
Serial-data write 0 ns
Serial-data read 10 ns
CLK
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
CLK
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
Edge mode (Note 2) 0.7 ns
Edge mode (Note 2) 0.5 ns
= 10pF, V
= 10pF, V
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
= 0.1µF (10τ)5m s
REFIO
50 ns
10 ns
10 ns
= 1.8V (Note 2) 3.4 5.3 7.1
= 3.3V 4.1
= 1.8V (Note 2) 12.8 13.4 ns
= 1.8V (Note 2) 1.4 2.0 ns
= 1.8V (Note 2) 3.3 5.2 7.0
= 3.3V 4.0
= 1.8V (Note 2) 5.0 5.9 ns
= 1.8V (Note 2) 1.2 1.8 ns
= 1.8V (Note 2) 44 50 56 %
= 1.8V (Note 2) 44 50 56 %
Relative to input clock period 2 Cycles
7.69 ns
7.69 ns
30 to 70 %
ns
7.69 ns
7.69 ns
30 to 70 %
ns
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Note 1: Specifications ≥ +25°C guaranteed by production test, specifications < +25°C guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
POWER REQUIREMENTS
Analog Supply Voltage V
Digital Output Supply Voltage V
Analog Supply Current I
Analog Power Dissipation P
Digital Output Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-level V
AVDD
OVDD
AVDD
DA
OVDD
High-level V
automatically)
Dual channel 47 55
Single channel active 28
Standby mode 8.5 12
Power-down mode 0.65 0.9
Power-down mode, V
Dual channel 85 99
Dual channel, V
Single channel active 50
Standby mode 15 22
Power-down mode 1.2 1.6
Power-down mode, V
Dual-channel mode, CL = 10pF 13
Power-down mode < 0.1
AVDD
(regulator mode, invoked
AVDD
AVDD
= 3.3V 1.6
AVDD
= 3.3V 155
= 3.3V 2.9
AVDD
1.7 1.9
2.3 3.5
1.7 3.5 V
V
mA
mW
mA
175MHz TWO-TONE IMD
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19515 toc06
-120
-100
-80
-60
-40
-20
0
f
IN1
= 172.49286MHz
f
IN2
= 177.50202MHz
0 5 10 15 25 30 20
70MHz TWO-TONE IMD PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19515 toc05
-120
-100
-80
-60
-40
-20
0
f
IN1
= 71.496925MHz
f
IN2
= 68.504600MHz
0 5 10 15 25 30 20
175MHz INPUT FFT PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19515 toc04
-120
-100
-80
-60
-40
-20
0
0 5 10 15 25 30 20
fIN = 175.096626MHz
A
IN
= -0.512dBFS
SNR = 59.073dB
SINAD = 59.022dB
THD = -78.338dBc
SFDR1 = 81.806dBc
SFDR2 = 84.255dBc
70MHz INPUT FFT PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19515 toc03
-120
-100
-80
-60
-40
-20
0
0 5 10 15 25 30 20
fIN = 70.1014328MHz
A
IN
= -0.532dBFS
SNR = 59.432dB
SINAD = 58.388dB
THD = -79.349dBc
SFDR1 = 84.227dBc
SFDR2 = 81.877dBc
3MHz SINGLE-ENDED INPUT FFT PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19515 toc02
-120
-100
-80
-60
-40
-20
0
0 5 10 15 25 30 20
fIN = 2.99877166748047MHz
A
IN
= -0.546dBFS
SNR = 59.675dB
SINAD = 59.632dB
THD = -79.673dBc
SFDR1 = 88.737dBc
SFDR2 = 82.290dBc
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
8 _______________________________________________________________________________________
Typical Operating Characteristics
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= +25°C, unless otherwise noted.)
3MHz INPUT FFT PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19515 toc01
0 5 10 15 25 30 20
-120
-100
-80
-60
-40
-20
0
fIN = 2.99877166MHz
A
IN
= -0.532dBFS
SNR = 59.682dB
SINAD = 59.641dB
THD = -79.826dBc
SFDR1 = 83.946dBc
SFDR2 = 82.852dBc
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
INL (LSB)
MAX19515 toc07
0 256 512 768 1024
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DNL (LSB)
MAX19515 toc08
0 256 512 768 1024
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
PERFORMANCE vs. INPUT FREQUENCY
INPUT FREQUENCY (MHz)
PERFORMANCE (dBFS)
MAX19515 toc09
0 50 100 150 200 250 300 350 400
50
55
60
65
70
75
80
85
90
95
-THD
SINAD
SFDR1
SNR
SFDR2
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
MAX19515 toc18
1.65 1.70 1.75 1.80 1.85 1.90 1.95
40
41
42
43
44
45
46
47
48
49
50
PERFORMANCE
vs. ANALOG INPUT AMPLITUDE
ANALOG INPUT AMPLITUDE (dBFS)
PERFORMANCE (dBFS)
MAX19515 toc11
-80 -70 -60 -50 -40 -30 -20 -10 0
50
60
70
80
90
100
110
SFDR2
SFDR1
-THD
SINAD
SNR
SINGLE-ENDED PERFORMANCE
vs. INPUT FREQUENCY
INPUT FREQUENCY (MHz)
SINGLE-ENDED PERFORMANCE (dBFS)
MAX19515 toc10
0 1 02 03 04 05 06 07 0
50
55
60
65
70
75
80
85
90
95
SFDR2
SFDR1
-THD
SINAD
SNR
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= +25°C, unless otherwise noted.)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
_______________________________________________________________________________________
9
PERFORMANCE
vs. COMMON-MODE VOLTAGE
95
90
SFDR2
85
80
75
70
SNR
65
PERFORMANCE (dBFS)
60
55
50
0.35 0.55 0.75 0.95 1.15 1.35
COMMON-MODE VOLTAGE (V)
SFDR1
-THD
SINAD
90
85
MAX19515 toc13
80
75
70
65
PERFORMANCE (dBFS)
60
55
50
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
SFDR2
-THD
SNR
SINAD
1.65 1.70 1.75 1.80 1.85 1.90 1.95
ANALOG SUPPLY VOLTAGE (V)
PERFORMANCE
vs. SAMPLING FREQUENCY
95
90
85
80
75
70
65
PERFORMANCE (dBFS)
60
55
50
20 25 30 35 40 45 50 55 60 65 70
SFDR2
-THD
SNR
SINAD
SAMPLING FREQUENCY (Msps)
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
SFDR1
90
85
MAX19515 toc14
80
75
70
65
PERFORMANCE (dBFS)
60
55
50
2.3 2.5 2.7 2.9 3.1 3.3 3.5
ANALOG SUPPLY VOLTAGE (V)
SFDR2
SFDR1
-THD
SNR
SINAD
SFDR1
MAX19515 toc12
MAX19515 toc15
ANALOG SUPPLY CURRENT
vs. SAMPLING FREQUENCY
50
48
46
44
42
40
38
36
34
ANALOG SUPPLY CURRENT (mA)
32
30
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (MHz)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
50
49
MAX19515 toc17
48
MAX19515 toc16
47
46
45
44
43
42
ANALOG SUPPLY CURRENT (mA)
41
40
-40 -20 0 20 40 60 80
TEMPERATURE (° C)
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
MAX19515 toc19
2.3 2.5 2.7 2.9 3.1 3.3 3.5
40
41
42
43
44
45
46
47
48
49
50
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
DIGITAL SUPPLY CURRENT
25
23
21
19
17
15
13
11
SUPPLY CURRENT (mA)
9
7
5
- 4 0- 2 00 2 04 06 08 0
vs. TEMPERATURE
V
= 3.6V
OVDD
V
= 1.8V
OVDD
TEMPERATURE (° C)
12
V
OVDD
10
8
6
4
DIGITAL SUPPLY CURRENT (mA)
2
0
20 25 30 35 40 45 50 55 60 65 70
25
DUAL BUS
MAX19515 toc22
20
15
10
5
DIGITAL SUPPLY CURRENT (mA)
0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
= 1.8V
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
25
V
OVDD
MAX19515 toc20
20
15
10
5
DIGITAL SUPPLY CURRENT (mA)
0
20 25 30 35 40 45 50 55 60 65 70
30
MULTIPLEXED BUS
25
MAX19515 toc23
20
15
10
DIGITAL SUPPLY CURRENT (mA)
5
0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
= 3.6V
MAX19515 toc21
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX19515 toc24
SUPPLY VOLTAGE (V)
90
vs. CLOCK DUTY CYCLE
85
80
75
70
PERFORMANCE (dBFS)
65
60
SINAD
55
30 35 40 45 50 55 60 65
CLOCK DUTY CYCLE (%)
PERFORMANCE
SFDR1
-THD
SNR
SFDR2
95
90
MAX19515 toc25
85
80
75
70
65
PERFORMANCE (dBFS)
60
55
50
PERFORMANCE vs. TEMPERATURE
SFDR1
SFDR2
SNR
SINAD
-40 -20 0 20 40 60 80
TEMPERATURE (° C)
-THD
MAX19515 toc26
GAIN ERROR vs. TEMPERATURE
0.05
0.04
0.03
0.02
0.01
0
-0.01
GAIN ERROR (%)
-0.02
-0.03
-0.04
-0.05
- 4 0- 2 00 2 04 06 08 0
TEMPERATURE (° C)
MAX19515 toc27
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 65MHz, AIN= -0.5dBFS, data output termination
= 50Ω , T
A
= +25°C, unless otherwise noted.)
COMMON-MODE REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (° C)
COMMON-MODE REFERENCE VOLTAGE (V)
MAX19515 toc30
- 4 0- 2 00 2 04 06 08 0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VCM = 1.2V
VCM = 1.05V
VCM = 0.9V
VCM = 0.75V
VCM = 0.6V
VCM = 0.45V
VCM = 1.35V
OFFSET ERROR vs. TEMPERATURE
TEMPERATURE (° C)
OFFSET ERROR (mV)
MAX19515 toc28
- 4 0- 2 00 2 04 06 08 0
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
______________________________________________________________________________________
11
GAIN ERROR vs. SUPPLY VOLTAGE
0.08
0.06
0.04
0.02
0
-0.02
GAIN ERROR (%)
-0.04
-0.06
-0.08
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
1.2516
1.2495
1.2474
REFERENCE VOLTAGE (V)
1.2453
1.2432
REGULATOR MODE
REFERENCE VOLTAGE
vs. TEMPERATURE
- 4 0- 2 00 2 04 06 08 0
TEMPERATURE (° C)
INPUT CURRENT
vs. COMMON-MODE VOLTAGE
60
MAX19515 toc31
55
50
45
40
35
INPUT CURRENT (µ A)
30
25
20
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
COMMON-MODE VOLTAGE (V)
MAX19515 toc29
MAX19515 toc32