MAXIM MAX19507 Technical data
General Description
The MAX19507 dual-channel, analog-to-digital converter
(ADC) provides 8-bit resolution and a maximum sample
rate of 130Msps.
The MAX19507 analog input accepts a wide 0.4V to
1.4V input common-mode voltage range, allowing DCcoupled inputs for a wide range of RF, IF, and baseband front-end components. The MAX19507 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and highintermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is
49.8dBFS and typical spurious-free dynamic range
(SFDR) is 69dBc at fIN= 70MHz and f
CLK
= 130MHz.
The MAX19507 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 74mW per channel at V
AVDD
= 1.8V. In addition to low operating
power, the MAX19507 consumes only 1mW in powerdown mode and 21mW in standby mode.
Various adjustments and feature selections are available through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three inputs available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible output data bus that can also be configured as a single
multiplexed parallel CMOS bus.
The MAX19507 is available in a small 7mm x 7mm, 48pin thin QFN package and is specified over the -40°C
to +85°C extended temperature range.
Refer to the MAX19515, MAX19516, and MAX19517
data sheets for pin- and feature-compatible 10-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19505 and MAX19506 data sheets for
pin- and feature-compatible 8-bit, 65Msps and 100Msps
versions, respectively.
Applications
IF and Baseband Communications, Including
Cellular Base Stations and Point-to-Point
Microwave Receivers
Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data
Acquisition
Digital Set-Top Boxes
Features
o Very-Low-Power Operation (74mW/Channel at
130Msps)
o 1.8V or 2.5V to 3.3V Analog Supply
o Excellent Dynamic Performance
49.8dBFS SNR at 70MHz
69dBc SFDR at 70MHz
o User-Programmable Adjustments and Feature
Selection through an SPI™ Interface
o Selectable Data Bus (Dual CMOS or Single
Multiplexed CMOS)
o DCLK Output and Programmable Data Output
Timing Simplifies High-Speed Digital Interface
o Very Wide Input Common-Mode Voltage Range
(0.4V to 1.4V)
o Very High Analog Input Bandwidth (> 850MHz)
o Single-Ended or Differential Analog Inputs
o Single-Ended or Differential Clock Input
o Divide-by-One (DIV1), Divide-by-Two (DIV2), and
Divide-by-Four (DIV4) Clock Modes
o Two’s Complement, Gray Code, and Offset Binary
Output Data Format
o Out-of-Range Indicator (DOR)
o CMOS Output Internal Termination Options
(Programmable)
o Reversible Bit Order (Programmable)
o Data Output Test Patterns
o Small 7mm x 7mm, 48-Pin Thin QFN Package with
Exposed Pad
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4311; Rev 1; 9/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX19507ETM+ -40°C to +85°C 48 TQFN-EP*
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc.
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OVDD, AVDD to GND............................................-0.3V to +3.6V
CMA, CMB, REFIO, INA+, INA-, INB+,
INB- to GND ......................................................-0.3V to +2.1V
CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN
to GND ..........-0.3V to the lower of (V
AVDD
+ 0.3V) and +3.6V
DCLKA, DCLKB, D7A–D0A, D7B–D0B, DORA, DORB
to GND..........-0.3V to the lower of (V
OVDD
+ 0.3V) and +3.6V
Continuous Power Dissipation (T
A
= +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C
above +70°C).............................................................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity INL fIN = 3MHz -0.3 ±0.1 +0.3 LSB
Differential Nonlinearity DNL fIN = 3MHz -0.3 ±0.1 +0.3 LSB
Offset Error OE Internal reference -0.4 ±0.1 +0.4 %FS
Gain Error GE External reference = 1.25V -1.5 ±0.3 +1.5 %FS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)
Differential Input-Voltage Range V
Common-Mode Input-Voltage
Range
Input Resistance R
Input Current I
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency f
Minimum Clock Frequency f
Data Latency Figures 9, 10 9 Cycles
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIFF
V
CM
IN
C
PAR
C
SAMPLE
CLK
CLK
Differential or single-ended inputs 1.5 V
(Note 2) 0.4 1.4 V
Fixed resistance, common mode, and
differential mode
IN
Differential input resistance, common mode
connected to inputs
Switched capacitance common-mode input
current, each input
Fixed capacitance to ground, each input 0.7
Switched capacitance, each input 1.2
> 100
4
74 µA
130 MHz
65 MHz
P-P
kΩ
pF
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
DYNAMIC PERFORMANCE
Small-Signal Noise Floor SSNF fIN = 70MHz, < -35dBFS -49.8 dBFS
Signal-to-Noise Plus Distortion
Ratio
Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)
Spurious-Free Dynamic Range
(4th and Higher Harmonics)
Third Harmonic HD3
Third-Order Intermodulation IM3
Full-Power Bandwidth FPBW R
Aperture Delay t
Aperture Jitter t
Overdrive Recovery Time ±10% beyond full scale 1 Cycles
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 3MHz 49.8
fIN = 70MHz 49.0 49.8Signal-to-Noise Ratio SNR
f
= 175MHz 49.8
IN
fIN = 3MHz 49.3
SINAD
SFDR1
SFDR2
AD
AJ
fIN = 70MHz 48.5 49.3
f
= 175MHz 49.3
IN
fIN = 3MHz 77.0
fIN = 70MHz 65.0 77.0
= 175MHz 77.0
f
IN
fIN = 3MHz 69.0
fIN = 70MHz 64.0 69.0
f
= 175MHz 69.0
IN
fIN = 3MHz -78.0
fIN = 70MHz -78.0 -65.0Second Harmonic HD2
= 175MHz -78.0
f
IN
fIN = 3MHz -82.0
fIN = 70MHz -82.0 -65.0
= 175MHz -80.0
f
IN
fIN = 3MHz -72.0
fIN = 70MHz -72.0 -63.0Total Harmonic Distortion THD
= 175MHz -72.0
f
IN
fIN = 70MHz ±1.5MHz, -7dBFS -80
= 175MHz ±2.5MHz, -7dBFS -75
f
IN
= 50Ω differential, -3dB rolloff 850 MHz
SOURCE
850 ps
0.3 ps
dBFS
dB
dBc
dBc
dBc
dBc
dBc
dBc
RMS
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERCHANNEL CHARACTERISTICS
f
or f
Crosstalk
f
INA
INA
= 70MHz at -1dBFS 95
INB
or f
= 175MHz at -1dBFS 85
INB
dBc
Gain Match fIN = 70MHz ±0.05 dB
Offset Match fIN = 70MHz ±0.2 %FSR
Phase Match fIN = 70MHz ±0.5 D eg r ees
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage V
COM
Default programmable setting 0.85 0.9 0.95 V
INTERNAL REFERENCE
REFIO Output Voltage V
REFOUT
REFIO Temperature Coefficient TC
REF
1.23 1.25 1.27 V
< ±60 ppm/°C
EXTERNAL REFERENCE
REFIO Input-Voltage Range V
REFIO Input Resistance R
REFIN
REFIN
1.25 +5/
-10%
10
±20%
V
kΩ
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage 0.4 to 2.0 V
Differential Input Common-Mode
Voltage
Self-biased 1.2
DC-coupled clock signal 1.0 to 1.4
P-P
V
Differential, default 10 kΩ
Input Resistance R
CLK
Differential, programmable internal
termination selected
100 Ω
Common mode 9 kΩ
Input Capacitance C
CLK
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V
Single-Ended Mode Selection
Threshold (V
Allowable Logic Swing (V
CLK-
)
) 0 - V
CLK+
Single-Ended Clock Input High
Threshold (V
CLK+
)
Single-Ended Clock Input Low
Threshold (V
CLK+
)
Input Leakage (CLK+)
Input Leakage (CLK-) V
To ground, each input 3 pF
< 0.1V)
CLK-
0.1 V
AVDD
1.5 V
0.3 V
V
= V
CLK+
= 0V -0.5
V
CLK+
= 0V -150 -50 µA
CLK-
= 1.8V or 3.3V +0.5
AVDD
µA
V
Input Capacitance (CLK+) 3pF
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUT (SYNC)
Allowable Logic Swing 0 - V
AVDD
Sync Clock Input High Threshold 1.5 V
Sync Clock Input Low Threshold 0.3 V
Input Leakage
= V
SYNC
= 0V -0.5
V
SYNC
= 1.8V or 3.3V +0.5
AVDD
V
Input Capacitance 4.5 pF
DIGITAL INPUTS (SHDN, SPEN)
Allowable Logic Swing 0 - V
AVDD
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
Input Leakage
Input Capacitance C
DIN
V
SHDN/VSPEN
V
SHDN/VSPEN
= V
= 1.8V or 3.3V +0.5
AVDD
= 0V -0.5
3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE
Allowable Logic Swing 0 - V
AVDD
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
V
Input Leakage
Input Capacitance C
DIN
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = V
V
Input Pullup Current
Input Pulldown Current
Open-Circuit Voltage V
OC
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
SCLK/VSDIN/VCS
V
= 1.8V 1.35 1.45 1.55
AVDD
V
= 3.3V 2.58 2.68 2.78
AVDD
= V
= 1.8V or 3.3V +0.5
AVDD
= 0V -0.5
)—PARALLEL CONTROL MODE (Figure 5)
AVDD
= V
= V
= 0V, V
= 0V, V
= 1.8V 7 12 17
AVDD
= 3.3V 16 21 26
AVDD
= 1.8V -65 -50 -35
AVDD
= 3.3V -105 -90 -75
AVDD
3pF
DIGITAL OUTPUTS (CMOS MODE 75Ω, D0–D7 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low V
Output-Voltage High V
Three-State Leakage Current I
OL
OH
LEAK
I
= 200µA 0.2 V
SINK
V
I
SOURCE
V
= 200µA
applied +0.5
OVDD
OVDD
- 0.2
GND applied -0.5
V
µA
V
µA
V
µA
µA
µA
V
V
µA
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER-MANAGEMENT CHARACTERISTICS
Wake-Up Time from Shutdown t
Wake-Up Time from Standby t
WAKE
WAKE
Internal reference, C
= 0.1µF (10τ)5ms
REFIO
Internal reference 15 µs
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
SCLK Period t
SCLK to CS Setup Time t
SCLK to CS Hold Time t
SDIN to SCLK Setup Time t
SDIN to SCLK Hold Time t
SCLK to SDIN Output Data Delay t
SCLK
CSS
CSH
SDS
SDH
SDD
Serial-data write 10 ns
Serial-data write 0 ns
Serial-data read 10 ns
50 ns
10 ns
10 ns
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9), (Default Timing see Table 5)
Clock Pulse-Width High t
Clock Pulse-Width Low t
Clock Duty Cycle tCH/t
Data Delay After Rising Edge of
CLK+
Data to DCLK Setup Time t
Data to DCLK Hold Time t
CH
CL
CLK
t
DD
SETUP
HOLD
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
= 1.8V (Note 2) 10.3 12.6 14.9
OVDD
= 3.3V 11.4
OVDD
= 1.8V (Note 2) 6.0 6.7 ns
OVDD
= 1.8V (Note 2) 0.4 1.0 ns
OVDD
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10), (Default Timing see Table 5)
Clock Pulse-Width High t
Clock Pulse-Width Low t
Clock Duty Cycle tCH/t
Data Delay After Rising Edge of
CLK+
Data to DCLK Setup Time t
Data to DCLK Hold Time t
DCLK Duty Cycle t
MUX Data Duty Cycle t
CH
CL
CLK
t
DD
SETUP
HOLD
DCH/tCLKCL
CHA/tCLKCL
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
CL = 10pF, V
= 10pF, V
= 10pF, V
= 1.8V (Note 2) 6.9 9.2 11.5
OVDD
= 3.3V 8.5
OVDD
= 1.8V (Note 2) 1.3 2.3 ns
OVDD
= 1.8V (Note 2) 0.7 1.5 ns
OVDD
= 1.8V (Note 2) 38 50 64 %
OVDD
= 1.8V (Note 2) 38 50 62 %
OVDD
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)
Setup Time for Valid Clock Edge t
Hold-Off Time for Invalid Clock
Edge
Minimum Synchronization Pulse
Width
SUV
t
HO
Edge mode (Note 2) 0.7 ns
Edge mode (Note 2) 0.5 ns
Relative to input clock period 2 Cycles
3.85 ns
3.85 ns
30 to 70 %
ns
3.85 ns
3.85 ns
30 to 70 %
ns
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Note 1: Specifications TA≥ +25°C guaranteed by production test, specifications TA< +25°C guaranteed by design and
characterization.
Note 2: Guaranteed by design and characterization.
POWER REQUIREMENTS
Analog Supply Voltage V
Digital Output Supply Voltage V
Analog Supply Current I
Analog Power Dissipation P
Digital Output Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-level V
AVDD
OVDD
AVDD
DA
OVDD
High-level V
automatically)
Dual channel 82 95
Single channel active 48
Standby mode 11.5 15
Power-down mode 0.65 0.9
Power-down mode, V
Dual channel 148 171
Dual channel, V
Single channel active 86
Standby mode 21 27
Power-down mode 1.2 1.6
Power-down mode, V
Dual-channel mode, CL = 10pF 22
Power-down mode < 0.1
AVDD
(regulator mode, invoked
AVDD
AVDD
= 3.3V 1.6
AVDD
= 3.3V 271
= 3.3V 2.9
AVDD
1.7 1.9
2.3 3.5
1.7 3.5 V
V
mA
mW
mA
175MHz TWO-TONE IMD PLOT
MAX19507 toc06
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0204060
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
f
IN1
= 172.50053MHz
f
IN2
= 177.48741MHz
70MHz TWO-TONE FFT PLOT
MAX19507 toc05
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0 204060
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
f
IN1
= 71.49905MHz
f
IN2
= 68.502129MHz
175MHz INPUT FFT PLOT
MAX19507 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0204060
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
fIN = 175.105057MHz
A
IN
= -0.508dBFS
SNR = 49.225dB
SINAD = 49.204dB
THD = -72.411dBc
SFDR1 = 80.172dBc
SFDR2 = 69.998dBc
70MHz INPUT FFT PLOT
MAX19507 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0 204060
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
fIN = 70.1088714MHz
A
IN
= -0.531dBFS
SNR = 49.187dB
SINAD = 49.172dB
THD = -73.779dBc
SFDR1 = 76.498dBc
SFDR2 = 71.834dBc
3MHz SINGLE-ENDED INPUT FFT PLOT
MAX19507 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0204060
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
fIN = 3.05381775MHz
A
IN
= -0.496dBFS
SNR = 49.281dB
SINAD = 49.232dB
THD = -68.700dBc
SFDR1 = 69.821dBc
SFDR2 = 68.781dBc
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
8 _______________________________________________________________________________________
Typical Operating Characteristics
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= +25°C, unless otherwise noted.)
3MHz INPUT FFT PLOT
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19507 toc01
0204060
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
fIN = 2.99827576MHz
A
IN
= -0.543dBFS
SNR = 49.135dB
SINAD = 49.120dB
THD = -73.810dBc
SFDR1 = 79.951dBc
SFDR2 = 68.821dBc
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
INL (LSB)
MAX19507 toc07
0 64 128 192 256
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
MAX19507 toc08
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DNL (LSB)
0 64 128 192 256
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
PERFORMANCE
vs. INPUT FREQUENCY
MAX19507 toc09
INPUT FREQUENCY (MHz)
PERFORMANCE (dBFS)
300 400200100
55
60
65
70
75
80
85
45
50
0
SFDR1
SFDR2
-THD
SINAD
SNR
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX19507 toc18
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
1.901.851.801.751.70
78
80
82
84
86
88
90
76
1.65 1.95
PERFORMANCE
vs. ANALOG INPUT AMPLITUDE
MAX19507 toc11
ANALOG INPUT AMPLITUDE (dBFS)
PERFORMANCE (dBFS)
-10-20-30-40-50-60 0
SFDR2
SFDR1
-THD
SINAD
SNR
55
60
65
70
75
80
85
45
50
SINGLE-ENDED PERFORMANCE
vs. INPUT FREQUENCY
MAX19507 toc10
INPUT FREQUENCY (MHz)
60
20 400
SFDR2
SFDR1
-THD
SINAD
SNR
SINGLE-ENDED PERFORMANCE (dBFS)
55
60
65
70
75
80
85
45
50
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= +25°C, unless otherwise noted.)
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
_______________________________________________________________________________________
9
85
80
75
70
65
60
PERFORMANCE (dBFS)
55
50
45
PERFORMANCE
vs. COMMON-MODE VOLTAGE
-THD
SFDR2
SINAD
COMMON-MODE VOLTAGE (V)
SFDR1
MAX19507 toc13
SNR
1.351.150.950.750.550.35
vs. ANALOG SUPPLY VOLTAGE
85
SFDR1
80
75
70
65
60
PERFORMANCE (dBFS)
55
50
45
SNR
ANALOG SUPPLY VOLTAGE (V)
PERFORMANCE
SFDR2
SINAD
1.851.751.65 1.95
PERFORMANCE
vs. SAMPLING FREQUENCY
85
SFDR1
80
75
70
65
60
PERFORMANCE (dBFS)
55
50
45
-THD
SFDR2
SNR
SAMPLING FREQUENCY (Msps)
SINAD
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
-THD
MAX19517 toc14
PERFORMANCE (dBFS)
85
80
75
70
65
60
55
50
45
SFDR1
-THD
SFDR2
SNR
ANALOG SUPPLY VOLTAGE (V)
SINAD
130120100 11090 140
3.32.82.3
MAX19507 toc12
MAX19507 toc15
ANALOG SUPPLY CURRENT
vs. SAMPLING FREQUENCY
90
85
80
75
70
ANALOG SUPPLY CURRENT (mA)
65
60
90 95 140
SAMPLING FREQUENCY (MHz)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
95
MAX19507 toc16
90
85
80
ANALOG SUPPLY CURRENT (mA)
75
70
130120110100 135125115105
-40
TEMPERATURE (°C)
MAX19507 toc17
806040200-20
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX19507 toc19
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
3.53.33.12.92.72.5
78
80
82
84
86
88
90
76
2.3
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
DIGITAL SUPPLY CURRENT
50
45
40
35
30
DIGITAL SUPPLY CURRENT (mA)
25
20
-40
vs. TEMPERATURE
V
OVDD
V
= 1.8V
OVDD
TEMPERATURE (°C)
= 3.6V
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
25
V
= 1.8V
OVDD
20
15
10
DIGITAL SUPPLY CURRENT (mA)
5
0
90 130
SAMPLING FREQUENCY (Msps)
120110100
MAX19507 toc20
DIGITAL SUPPLY CURRENT (mA)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
45
DUAL BUS
40
MAAX19507 toc22
35
30
25
20
15
10
DIGITAL SUPPLY CURRENT (mA)
5
6010
0
1.8 2.3 2.8 3.3
SUPPLY VOLTAGE (V)
50
45
MAX19507 toc23
40
35
30
25
20
15
10
DIGITAL SUPPLY CURRENT (mA)
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
50
V
= 3.6V
OVDD
45
40
35
30
25
20
15
10
5
0
90 130
SAMPLING FREQUENCY (Msps)
120110100
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MULTIPLEXED BUS
5
0
1.7 2.2 2.7 3.2
SUPPLY VOLTAGE (V)
MAX19507 toc21
MAX19507 toc24
85
80
75
70
65
60
PERFORMANCE (dBFS)
55
50
45
30
PERFORMANCE
vs. CLOCK DUTY CYCLE
-THD
SFDR1
SFDR2
SNR
SINAD
CLOCK DUTY CYCLE (%)
PERFORMANCE
vs. TEMPERATURE
MAX19507 toc26
0.05
0.04
0.03
0.02
0.01
0
-0.01
GAIN ERROR (%)
-0.02
-0.03
-0.04
-0.05
-40
85
80
MAX19507 toc25
75
70
65
60
PERFORMANCE (dBFS)
55
50
6040 50
45
SNR
SINAD
TEMPERATURE (°C)
SFDR1
-THD
SFDR2
6010-40
GAIN ERROR
vs. TEMPERATURE
MAX19517 toc27
6010
TEMPERATURE (°C)
Typical Operating Characteristics (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= +25°C, unless otherwise noted.)
COMMON-MODE VOLTAGE
vs. TEMPERATURE
MAX19507 toc30
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
6010
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
-40
VCM = 1.35V
VCM = 1.2V
VCM = 1.05V
VCM = 0.9V
VCM = 0.75V
VCM = 0.6V
VCM = 0.45V
OFFSET ERROR
vs. TEMPERATURE
MAX19507 toc28
TEMPERATURE (°C)
OFFSET ERROR (mV)
6010
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
-0.7
-40
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
______________________________________________________________________________________
11
1.2516
1.2495
1.2474
REFERENCE VOLTAGE (V)
1.2453
1.2432
GAIN ERROR vs. SUPPLY VOLTAGE
0.08
0.06
0.04
0.02
0
-0.02
GAIN ERROR (%)
-0.04
-0.06
-0.08
1.6 2.1 2.6 3.1 3.6
REGULATOR MODE
SUPPLY VOLTAGE (V)
-40
REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
MAX19507 toc31
MAX19507 toc29
6010
INPUT CURRENT
vs. COMMON-MODE VOLTAGE
110
100
90
80
70
INPUT CURRENT (µA)
60
50
40
0.4 0.6 0.8 1.0 1.2 1.4
COMMON-MODE VOLTAGE (V)
MAX19507 toc32
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