MAXIM MAX1932 Technical data

General Description

The MAX1932 generates a low-noise, high-voltage output
to bias avalanche photodiodes (APDs) in optical
receivers. Very low output ripple and noise is achieved by
a constant-frequency, pulse-width modulated (PWM)
boost topology combined with a unique architecture that
maintains regulation with an optional RC or LC post filter
inside its feedback loop. A precision reference and error
amplifier maintain 0.5% output voltage accuracy.

The MAX1932 protects expensive APDs against adverse
operating conditions while providing optimal bias.
Traditional boost converters measure switch current for
protection, whereas the MAX1932 integrates accurate
high-side current limiting to protect APDs under
avalanche conditions. A current-limit flag allows easy cali­bration of the APD operating point by indicating the pre­cise point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to
provide safe APD operation without data loss.

The output voltage can be accurately set with either
external resistors, an internal 8-bit DAC, an external
DAC, or other voltage source. Output span and offset
are independently settable with external resistors. This
optimizes the utilization of DAC resolution for applica­tions that may require limited output voltage range, such
as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V.

Applications

Optical Receivers and Modules
Fiber Optic Network Equipment
Telecom Equipment
Laser Range Finders
PIN Diode Bias Supply

Features

♦ Small Circuit Footprint

♦ Circuit Height < 2mm

♦ 2.7V to 5.5V Input

♦ 4.5V to 90V Output

♦ No Overshoot

♦ Accurate High-Side Current Limit

♦ Avalanche Indicator Flag

♦ 8-Bit SPI-Compatible DAC

♦ Compatible with External DAC

♦ 0.5% Accurate Output

♦ Low Ripple Output (< 1mV)

♦ Small 12-Pin, 4mm ✕ 4mm Thin QFN Package

MAX1932

Digitally Controlled, 0.5% Accurate, Safest APD

Bias Supply

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2555; Rev 1; 12/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

TEMP RANGE

PIN-PACKAGE

MAX1932ETC

12 Thin QFN

MAX1932

INPUT

2.7V TO 5.5V

APD BIAS OUTPUT

4.5V TO 90V

DAC INPUTS

AVALANCHE

INDICATOR

FLAG

VIN

COMP

SCLK

GND

FB

CS-

CS+

GATE

DACOUT

DIN

CS

CL

Typical Application Circuit

MAX1932

12

1

2

3

9

8

7

11 10

4 5 6

SCLK GND

COMP

FB

CS+

CS-

DACOUT GATE

VIN

DIN

CL

CS

Pin Configuration

查询MAX1932供应商

-40°C to +85°C

MAX1932

Digitally Controlled, 0.5% Accurate, Safest APD
Bias Supply

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VIN= 3.3V, CS = SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= 0°C to +85°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VIN to GND...............................................................-0.3V to +6V

DIN, SCLK, CS, FB to GND ......................................-0.3V to +6V

COMP, DACOUT, GATE, CL to GND ...........-0.3V to (V

IN

+0.3V)

CS+, CS- to GND .................................................-0.3V to +110V

Continuous Power Dissipation (T

A

= +70°C)

12-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering 10s) ..................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

GENERAL

Input Supply Range V

IN

2.7 5.5 V

VIN Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V

Operating Supply Current I

IN

0.5 1 mA

VIN Shutdown Supply Current I

SHDN

00 hex loaded to DAC 25 65 µA

Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 1 2.0 MΩ

Current-Limit Threshold
for CS+/CS-

V

Common-Mode Rejection
of Current Threshold

CS+ = 3V to 100V

%/V

Gate-Driver Resistance Gate high or low, I

GATE

= ±50mA 5 10 Ω

FB Input Bias Current -25

nA

TA = +25°C

FB Voltage V

FB

TA = 0°C to +85°C

V

FB Voltage
Temperature Coefficient

TCV

FB

%/°C

FB to COMP Transconductance COMP = 1.5V 50

200 µS

COMP Pulldown Resistance
in Shutdown

DAC code = 00 hex 100 Ω

D AC OU T to FB V ol tag e D i ffer ence

DAC code = FF hex -3 +3 mV

D AC OU T Differential Nonlinearity
(Note 1)

DAC Code = 01 to FF hex,
DAC guaranteed monotonic

-1 +1 LSB

D AC OU T Voltage Temperature
Coefficient

%/°C

DACOUT Load Regulation

DAC code = 0F to FF hex, source or sink
50µA

-1 +1 mV

Switching Frequency f

OSC

340 kHz

GATE Maximum On-Time t

ON

3µs

TCV

DACOUT

1.80 2.00 2.20

±0.005

1.24375 1.2500 1.25625

1.24250 1.2500 1.25750

0.0007

110

0.0007

250 300

+25

MAX1932

Digitally Controlled, 0.5% Accurate, Safest APD

Bias Supply

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.3V, CS = SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= 0°C to +85°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS (DIN, SCLK, CS)

Input Low Voltage 0.6 V

Input High Voltage 1.4 V

Input Hysteresis

mV

TA = +25°C-1+1µA

Input Leakage Current

T

A

= 0°C to +85°C10nA

Input Capacitance 5pF

DIGITAL OUTPUT (CL)

Output Low Voltage I

SINK

= 1mA 0.1 V

Output High Voltage I

SOURCE

= 0.5mA V

IN

- 0.5 V

SPI TIMING (FIGURE 5)

SCLK Clock Frequency f

SCLK

2

MHz

SCLK Low Period t

CL

ns

SCLK High Period t

CH

ns

Data Hold Time t

DH

0ns

Data Setup Time t

DS

ns

CS Assertion to SCLK
Rising Edge Setup Time

t

CSS0

ns

CS Deassertion to SCLK
Rising Edge Setup Time

t

CSS1

ns

SCLK Rising Edge
to CS Deassertion

t

CSH1

ns

SCLK Rising Edge
to CS Assertion

t

CSH0

ns

CS High Period t

CSW

ns

ELECTRICAL CHARACTERISTICS

(VIN= 3.3V, CS = SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER

CONDITIONS

UNITS

GENERAL

Input Supply Range V

IN

2.7 5.5 V

VIN Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V

Operating Supply Current I

IN

1mA

VIN Shutdown Supply Current I

SHDN

00 hex loaded to DAC 65 µA

Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 2 MΩ

Current-Limit Threshold
for CS+/CS-

V

Gate-Driver Resistance Gate high or low, I

GATE

= ±50mA 10 Ω

FB Input Bias Current -30

nA

200

125

125

125

200

200

SYMBOL

200

200

300

MIN TYP MAX

1.80 2.20

+30

MAX1932

Digitally Controlled, 0.5% Accurate, Safest APD
Bias Supply

4 _______________________________________________________________________________________

Note 1: DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2: Specifications to -40°C are guaranteed by design and not production tested.

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.3V, CS = SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER

CONDITIONS

UNITS

FB Voltage V

FB

V

FB to COMP Transconductance COMP = 1.5V 50 200 µS

COMP Pulldown Resistance
in Shutdown

DAC code = 00 hex 100 Ω

DAC code = FF hex -4 +4 mV

D AC OU T Differential Nonlinearity
(Note 1)

DAC Code = 01 to FF hex, DAC
guaranteed monotonic

-1 +1 LSB

D AC OU T Load Regulation

DAC code = 0F to FF hex, source or sink
50µA

-1 +1 mV

Switching Frequency f

OSC

360 kHz

DIGITAL INPUTS (DIN, SCLK, CS)

Input Low Voltage 0.6 V

Input High Voltage 1.4 V

DIGITAL OUTPUT (CL)

Output Low Voltage I

SINK

= 1mA 0.1 V

Output High Voltage I

SOURCE

= 0.5mA

V

SPI TIMING (FIGURE 5)

SCLK Clock Frequency f

SCLK

2

MHz

SCLK Low Period t

CL

125 ns

SCLK High Period t

CH

125 ns

Data Hold Time t

DH

0ns

Data Setup Time t

DS

125 ns

CS Assertion to SCLK
Rising Edge Setup Time

t

CSS0

200 ns

CS Deassertion to SCLK
Rising Edge Setup Time

t

CSS1

200 ns

SCLK Rising Edge
to CS Deassertion

t

CSH1

200 ns

SCLK Rising Edge
to CS Assertion

t

CSH0

200 ns

CS High Period t

CSW

300 ns

SYMBOL

MIN TYP MAX

1.23875 1.26125

D AC OU T to FB V ol tag e D i ffer ence

240

V

- 0.5

IN

MAX1932

Digitally Controlled, 0.5% Accurate, Safest APD

Bias Supply

_______________________________________________________________________________________ 5

SWITCHING WAVEFORMS

MAX1932 toc01

1µs/div

0.05A/div

50V/div

0.002V/div

V

LX

I

L

V

OUT

RIPPLE (AC-COUPLED)

V

OUT

= 90V

SWITCHING WAVEFORM WITH LC FILTER

MAX1932 toc02

1µs/div

0.05A/div

50V/div

0.002V/div

V

LX

I

L

V

OUT

RIPPLE (AC-COUPLED)

V

OUT

= 90V, L = 300µH, C = 1µF, FIGURE 7

STARTUP AND SHUTDOWN WAVEFORMS

MAX1932 toc03

20ms/div

50mA/div

50V/div

INPUT

CURRENT

OUTPUT

VOLTAGE

OUTPUT VOLTAGE vs. INPUT VOLTAGE

MAX1932 toc04

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

4.53.5

89

90

91

92

88

2.5 5.5

VFB vs. TEMPERATURE

MAX1932 toc05

TEMPERATURE (°C)

VFB (V)

8060-40 -20 0 20 40

1.2485

1.2490

1.2495

1.2500

1.2505

1.2510

1.2515

1.2520

1.2480

-60 100

OUTPUT VOLTAGE vs. LOAD CURRENT

MAX1932 toc06

LOAD CURRENT (mA)

OUTPUT VOLTAGE (V)

2.52.01.51.00.5

55

60

65

70

75

80

85

90

95

50

0 3.0

CURRENT LIMIT
ACTIVATED

VCC = 5V, INDUCTOR = 100µH,
R1 = 806Ω
FEEDBACK DIVIDER CURRENT AND CS­CURRENT INCLUDED

OUTPUT VOLTAGE STEP-DOWN

DUE TO DAC CHANGE

MAX1932 toc07

10ms/div

1V/div

V

OUT

AT

64.233V

OFFSET = 62.962V = 88 hex
STEP DOWN FROM 80 hex TO 88 hex

OUTPUT VOLTAGE STEP-UP

DUE TO DAC CHANGE

MAX1932 toc08

10ms/div

1V/div

V

OUT

AT

62.692V
OFFSET

OFFSET = 62.962V = 88 hex
STEP VALUE = 64.233 = 80 hex

OUTPUT VOLTAGE STEP

DUE TO DACOUT CHANGE

MAX1932 toc09

20ms/div

20V/div

0.5V/div

DACOUT EXTERNAL SOURCE

Typical Operating Characteristics

(VIN= 5V, Circuit of Figure 2, TA=+25°C, unless otherwise noted)

MAX1932

Detailed Description

Fixed Frequency PWM

The MAX1932 uses a constant frequency, PWM, con­troller architecture. This controller sets the switch on­time and drives an external N-channel MOSFET (see
Figure 1). As the load varies, the error amplifier sets the
inductor peak current necessary to supply the load and
regulate the output voltage.

Output Current Limit

The MAX1932 uses an external resistor at CS+ and CS­to sense the output current (see Figure 2). The typical
current-limit threshold is 2V. CL is designed to help find
the optimum APD bias point by going low to indicate
when the APD reaches avalanche and that current limit
has been activated. To minimize noise, CL only
changes state on an internal oscillator edge.

Output Control DAC

An internal digital-to-analog converter can be used to
control the output voltage of the DC-DC converter
(Figure 2). The DAC output is changed through an SPI™
serial interface using an 8-bit control byte. On power-up,
the DAC defaults to FF hex (1.25V), which corresponds
to a minimum boost converter output voltage.

Alternately, the output voltage can be set with external
resistors, an external DAC, or a voltage source. Output
span and offset are independently settable with exter-

nal resistors. See the Applications Information section

for output control equations.

SPI Interface/Shutdown

Use an SPI-compatible 3-wire serial interface with the
MAX1932 to control the DAC output voltage and to shut
down the MAX1932. Figures 4 and 5 show timing diagrams
for the SPI protocol. The MAX1932 is a write-only device
and uses CS along with SCLK and DIN to communicate.
The serial port is always operational when the device is
powered. To shut down the DC-DC converter portion only,
update the DAC registers to 00 hex.

Applications Information

Voltage Feedback Sense Point

Feedback can be taken from in front of, or after, the cur­rent-limit sense resistor. The current-limit sense resistor
forms a lowpass filter with the output capacitor. Taking
feedback after the current-limit sense resistor (see Figure

2), optimizes the output voltage accuracy, but requires
overcompensation, which slows down the control loop
response. For faster response, the feedback can be
taken from in front of the current-sense resistor (see
Figure 3). This configuration however, makes the output
voltage more sensitive to load variation and degrades
output accuracy by an amount equal to the load current
times the current-sense resistor value.

Digitally Controlled, 0.5% Accurate, Safest APD
Bias Supply

6 _______________________________________________________________________________________

Pin Description

PIN

FUNCTION

1 SCLK DAC Serial Clock Input

2 DIN DAC Serial Data Input
3 CL Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN.

4 CS+

Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential
threshold is 2V. CS+ has typically 1MΩ resistance to ground.

5 CS- Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground.

6

Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or
sink 50µA.

7FB

Feedback input. Connect to a resistive voltage-divider between the output voltage (V

OUT

) and FB to set the

output voltage. The feedback set point is 1.25V.

8

Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is
actively discharged to ground during shutdown or undervoltage conditions.

9 GND Ground

10 GATE Gate-Driver Output for External N-FET

11 VIN IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor.
12 CS DAC Chip-Select Input

SPI is a trademark of Motorola, Inc.

NAME

DACOUT

COMP