Maxim MAX192BMJP, MAX192BCWP, MAX192BCPP, MAX192BCAP, MAX192AMJP Datasheet

________________General Description

The MAX192 is a low-cost, 10-bit data-acquisition system
that combines an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and ultra-low power consumption. The device
operates with a single +5V supply. The analog inputs are
software configurable for single-ended and differential
(unipolar/bipolar) operation.

The 4-wire serial interface connects directly to SPI™,
QSPI™, and Microwire™ devices, without using external
logic. A serial strobe output allows direct connection to
TMS320 family digital signal processors. The MAX192
uses either the internal clock or an external serial­interface clock to perform successive approximation A/D
conversions. The serial interface can operate beyond
4MHz when the internal clock is used. The MAX192 has
an internal 4.096V reference with a drift of ±30ppm typi­cal. A reference-buffer amplifier simplifies gain trim and
two sub-LSBs reduce quantization errors.

The MAX192 provides a hardwired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the device, and
the quick turn-on time allows the MAX192 to be shut
down between conversions. By powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.

The MAX192 is available in 20-pin DIP and SO pack­ages, and in a shrink-small-outline package (SSOP)
that occupies 30% less area than an 8-pin DIP. The
data format provides hardware and software compati­bility with the MAX186/MAX188. For anti-aliasing filters,
consult the data sheets for the MAX291–MAX297.

________________________Applications

Automotive
Pen-Entry Systems
Consumer Electronics
Portable Data Logging
Robotics
Battery-Powered Instruments, Battery

Management

Medical Instruments

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel Differential

Inputs

♦ Single +5V Operation
♦ Low Power: 1.5mA (operating)

2µA (power-down)

♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference
♦ 4-Wire Serial Interface is Compatible

with SPI, QSPI, Microwire, and TMS320

♦ 20-Pin DIP, SO, SSOP Packages
♦ Pin-Compatible 12-Bit Upgrade (MAX186/MAX188)

_______________Ordering Information

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

________________________________________________________________ Maxim Integrated Products

1

20
19
18
17
16
15
14
13
12
11

1
2
3
4
5
6
7
8
9

10

TOP VIEW

DIP/SO/SSOP

V

DD

SCLK
CS

DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREFSHDN

AGND

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

MAX192

___________________Pin Configuration

SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Corp.

19-0247; Rev. 1; 4/97

PART TEMP. RANGE

MAX192ACPP 0°C to +70°C
MAX192BCPP 0°C to +70°C
MAX192ACWP 0°C to +70°C 20 Wide SO

20 Plastic DIP

20 Plastic DIP

PIN-PACKAGE

MAX192BCWP 0°C to +70°C 20 Wide SO
MAX192ACAP 0°C to +70°C 20 SSOP
MAX192BCAP 0°C to +70°C 20 SSOP

±1/2

±1

±1/2

INL (LSB)

±1
±1/2

±1
MAX192AEPP -40°C to +85°C 20 Plastic DIP ±1/2
MAX192BEPP -40°C to +85°C 20 Plastic DIP ±1
MAX192AEWP -40°C to +85°C 20 Wide SO ±1/2
MAX192BEWP -40°C to +85°C 20 Wide SO ±1
MAX192AEAP -40°C to +85°C 20 SSOP ±1/2
MAX192BEAP -40°C to +85°C 20 SSOP ±1
MAX192AMJP -55°C to +125°C 20 CERDIP ±1/2
MAX192BMJP -55°C to +125°C 20 CERDIP ±1

See last page for Typical Operating Circuit.

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone] ext. 3468.

MAX192

Low-Power, 8-Channel,
Serial 10-Bit ADC

2 _______________________________________________________________________________________

VDDto AGND........................................................... -0.3V to +6V

AGND to DGND.................................................... -0.3V to +0.3V

CH0–CH7 to AGND, DGND ...................... -0.3V to (VDD+ 0.3V)

CH0–CH7 Total Input Current.......................................... ±20mA

VREF to AGND .......................................... -0.3V to (VDD+ 0.3V)

REFADJ to AGND...................................... -0.3V to (VDD+ 0.3V)

Digital Inputs to DGND.............................. -0.3V to (VDD+ 0.3V)

Digital Outputs to DGND........................... -0.3V to (VDD+ 0.3V)

Digital Output Sink Current.................................................25mA

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW

SO (derate 10.00mW/°C above +70°C)...................... 800mW

SSOP (derate 8.00mW/°C above +70°C) ................... 640mW

CERDIP (derate 11.11mW/°C above +70°C).............. 889mW

Operating Temperature Ranges

MAX192_C_P..................................................... 0°C to +70°C

MAX192_E_P ..................................................-40°C to +85°C

MAX192_MJP ............................................... -55°C to +125°C

Storage Temperature Range............................ -60°C to +150°C

Lead Temperature (soldering, 10sec)............................ +300°C

ELECTRICAL CHARACTERISTICS

(VDD= 5V ±5%, f

CLK

= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,

T

A

= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

MAX192A

-3dB rolloff

65kHz, VIN= 4.096Vp-p (Note 3)

External reference, 4.096V

MAX192B
No missing codes over temperature

External reference, 4.096V

CONDITIONS

kHz800Full-Power Bandwidth

MHz4.5Small-Signal Bandwidth

dB-75Channel-to-Channel Crosstalk

dB70SFDRSpurious-Free Dynamic Range

dB-70THD

Total Harmonic Distortion
(up to the 5th harmonic)

dB66SINADSignal-to-Noise + Distortion Ratio

±1/2

Bits10Resolution

LSB±0.1

Channel-to-Channel
Offset Matching

ppm/°C±0.8Gain Temperature Coefficient

LSB

±1

Relative Accuracy (Note 2)

LSB±1DNLDifferential Nonlinearity
LSB±2Offset Error
LSB±2Gain Error

UNITSMIN TYP MAXSYMBOLPARAMETER

Internal clock 5.5 10

Conversion Time (Note 4) t

CONV

External clock, 2MHz, 12 clocks/conversion 6

µs

Track/Hold Acquisition Time t

AZ

1.5 µs
Aperture Delay 10 ns
Aperture Jitter <50 ps
Internal Clock Frequency 1.7 MHz

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock)

CONVERSION RATE

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%, f

CLK

= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,

T

A

= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

Internal compensation

0mA to 0.5mA output load

TA= +25°C (Note 7)

(Note 5)

On/off leakage current; VIN= 0V, 5V

Bipolar

Used for data transfer only

Internal compensation (Note 5)

External compensation, 4.7µF

Single-ended range (unipolar only)

Common-mode range (any input)

CONDITIONS

0

mV2.5Load Regulation (Note 8)

ppm/°C±30VREF Tempco

mA30VREF Short-Circuit Current

V4.066 4.096 4.126VREF Output Voltage

pF16Input Capacitance

µA±0.01 ±1Multiplexer Leakage Current

V

-V

REF

+V

REF

-2 2

Analog Input Voltage
(Note 6)

0 V

REF

0 V

REF

0 V

DD

MHz

10

External Clock Frequency

0.1 0.4

0.1 2.0

UNITSMIN TYP MAXSYMBOLPARAMETER

Capacitive Bypass at VREF

External compensation 4.7

µF

Internal compensation 0.01

Capacitive Bypass at REFADJ

External compensation 0.01

µF

REFADJ Adjustment Range ±1.5 %

Input Voltage Range

2.5

V

DD

+

50mV

V

Input Current 200 350 µA
Input Resistance 12 20 kΩ
Shutdown VREF Input Current 1.5 10 µA

Buffer Disable Threshold
REFADJ

V

DD

-

50mV

V

Unipolar

Differential range

Internal compensation mode 0

Capacitive Bypass at VREF

External compensation mode 4.7

µF

Reference-Buffer Gain 1.678 V/V
REFADJ Input Current ±50 µA

ANALOG INPUT

INTERNAL REFERENCE (reference buffer enabled)

EXTERNAL REFERENCE AT VREF (buffer disabled, VREF = 4.096V)

EXTERNAL REFERENCE AT REFADJ

Note 1: Tested at VDD= 5.0V; single-ended, unipolar.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to V

DD

.

Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at V

SUPPLY

+ 5% and V

SUPPLY

- 5% only.

MAX192

Low-Power, 8-Channel,
Serial 10-Bit ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%, f

CLK

= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,

T

A

= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

I

SINK

= 16mA

I

SINK

= 5mA

SHDN = open

SHDN = open

SHDN = 0V

SHDN = V

DD

(Note 5)

VIN= 0V or V

DD

CONDITIONS

V

0.3

V

OL

Output Voltage Low

0.4

nA-100 100

SHDN Max Allowed Leakage,
Mid Input

V2.75V

FLT

SHDN Voltage, Floating

V1.5 V

DD

- 1.5V

IM

SHDN Input Mid Voltage

µA-4.0I

INL

SHDN Input Current, Low

µA4.0I

INH

SHDN Input Current, High

V0.5V

INL

SHDN Input Low Voltage

VV

DD

- 0.5V

INH

SHDN Input High Voltage

pF15C

IN

DIN,SCLK, CS Input Capacitance

µA±1I

IN

DIN, SCLK, CS Input Leakage

V0.15V

HYST

DIN, SCLK, CS Input Hysteresis

V0.8V

INL

DIN,SCLK, CS Input Low Voltage

V2.4V

INH

DIN,SCLK, CS Input High Voltage

UNITSMIN TYP MAXSYMBOLPARAMETER

Output Voltage High V

OH

I

SOURCE

= 1mA 4 V

Three-State Leakage Current I

L

CS = 5V

±10 µA

Three-State Leakage Capacitance C

OUT

CS = 5V (Note 5)

15 pF

Positive Supply Voltage V

DD

5 ±5% V
Operating mode 1.5 2.5 mA
Fast power-down 30 70Positive Supply Current I

DD

Full power-down 2 10

µA

Positive Supply Rejection
(Note 9)

PSR

VDD= 5V ±5%; external reference, 4.096V;
full-scale input

±0.06 ±0.5 mV

EXTERNAL REFERENCE AT REFADJDIGITAL INPUTS (DIN, SCLK, –C—S–, –S—H—D—N–)

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER REQUIREMENTS

Note 5: Guaranteed by design. Not subject to production testing.

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

_______________________________________________________________________________________ 5

TIMING CHARACTERISTICS

(VDD= 5V ±5%, TA= T

MIN

to T

MAX

, unless otherwise noted.)

C

LOAD

= 100pF

External clock mode only, C

LOAD

= 100pF

C

LOAD

= 100pF

C

LOAD

= 100pF

C

LOAD

= 100pF

External clock mode only, C

LOAD

= 100pF

CONDITIONS

ns200t

STR

CS Rise to SSTRB Output
Disable (Note 5)

CS Fall to SSTRB Output Enable
(Note 5)

ns200t

SDV

ns0t

DH

DIN to SCLK Hold

ns100t

DS

µs1.5t

AZ

Acquisition Time
DIN to SCLK Setup

ns200t

SSTRB

SCLK Fall to SSTRB

ns200t

CL

SCLK Pulse Width Low

ns200t

CH

SCLK Pulse Width High

ns0t

CSH

CS to SCLK Rise Hold

ns20 150t

DO

ns100t

DV

ns100t

TR

SCLK Fall to Output Data Valid

ns100t

CSS

CS to SCLK Rise Setup

UNITSMIN TYP MAXSYMBOLPARAMETER

SSTRB Rise to SCLK Rise
(Note 5)

t

SCK

Internal clock mode only 0 ns

CS Rise to Output Disable

CS Fall to Output Enable

__________________________________________Typical Operating Characteristics

0.16

0

-60 -20 60 140

CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE

0.02

0.12

TEMPERATURE (°C)

OFFSET MATCHING (LSBs)

20 100

0.10

0.04

-40 0 40 80 120

0.14

0.08

0.06

0.30

-0.05

-60 140

POWER-SUPPLY REJECTION

vs. TEMPERATURE

0

0.25

TEMPERATURE (°C)

PSR (LSBs)

60

0.10

0.05

-40 20 100

0.15

0.20

-20 0 40 80 120

VDD = +5V ±5%

2.456

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.452

2.455

TEMPERATURE (°C)

VREFADJ (V)

2.454

2.453

-40 -20 0 20 40 60 80 100 120

-60 140

MAX192

Low-Power, 8-Channel,
Serial 10-Bit ADCs

6

________________________________________________________________________________________________

+5V

3k

C

LOAD

DGND

DOUT

C

LOAD

DGND

3k

DOUT

a) High-Z to V

OH

and VOL to V

OH

b) High-Z to VOL and VOH to V

OL

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disabled Time

Pin Description

PIN NAME FUNCTION

1–8 CH0–CH7 Sampling Analog Inputs

9, 13 AGND

Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
analog ground.

10

SHDN

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur­rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi­er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.

11 VREF

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.

12 REFADJ Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to VDD.
14 DGND Digital Ground

15 DOUT

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is
high.

16 SSTRB

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. SSTRB is high impedance when CS is high
(external mode).

17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.
18

CS

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.

19 SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

20 V

DD

Positive Supply Voltage, +5V ±5%

+3V

DOUT

DOUT

3k

DGND

to High-Z b) VOL to High-Z

a) V

OH

C

LOAD

3k

C

LOAD

DGND

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

_______________________________________________________________________________________ 7

INPUT
SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

OUTPUT

SHIFT

REGISTER

+2.46V

REFERENCE

T/H

ANALOG

INPUT

MUX

SAR
ADC

IN

DOUT
SSTRB

V

DD

DGND

SCLK

DIN

CH0
CH1

CH3

CH2

CH7

CH6

CH5

CH4

AGND

REFADJ

VREF

OUT

REF

CLOCK

+4.096V

20k

≈ 1.65

1
2
3

4
5

6
7

8

10

11

12

13

15
16

17

18
19

CS

SHDN

A

20

14

AGND

9

MAX192

Figure 3. Block Diagram

Detailed Description

The MAX192 uses a successive-approximation conver­sion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX192.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com­parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer
to Tables 1 and 2 to configure the channels.

In differential mode, IN- and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta­ble within ±0.5LSB (±0.1LSB for best results) with

respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select­ed analog input, respectively) to AGND.

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C

HOLD

. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui­sition interval, the T/H switch opens, retaining charge
on C

HOLD

as a sample of the signal at IN+.

The conversion interval begins with the input multiplex­er switching C

HOLD

from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is
simply AGND. This unbalances node ZERO at the input
of the comparator. The capacitive DAC adjusts during
the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
action is equivalent to transferring a charge of
16pF x (VIN+ - VIN-) from C

HOLD

to the binary-weighted
capacitive DAC, which in turn forms a digital represen­tation of the analog input signal.

CH0
CH1

CH2
CH3
CH4
CH5
CH6
CH7

AGND

C

SWITCH

TRACK

T/H

SWITCH

10k
R

S

C

HOLD

HOLD

CAPACITIVE DAC

VREF

ZERO

COMPARATOR

–

+

16pF

SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit

MAX192

Track/Hold

The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for single-ended
inputs, IN- is connected to AGND, and the converter
samples the “+” input. If the converter is set up for differ­ential inputs, IN- connects to the “-” input, and the differ­ence of IN+ - IN- is sampled. At the end of the conver­sion, the positive input connects back to IN+, and
C

HOLD

charges to the input signal.

The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acquisi­tion time lengthens and more time must be allowed
between conversions. Acquisition time is calculated by:

tAZ= 9 (RS+ RIN) 16pF

where RIN= 5kΩ, RS= the source impedance of the
input signal, and tAZ is never less than 1.5µs. Note that
source impedances below 5kW do not significantly affect
the AC performance of the ADC. Higher source imped­ances can be used if an input capacitor is connected to
the analog inputs, as shown in Figure 5. Note that the
input capacitor forms an RC filter with the input source
impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig­nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.
See the data sheets for the MAX291–MAX297 filters.

Analog Input Range and Input Protection

Internal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD+ 0.3V without dam­age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV, or
be lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the sup­plies, do not forward bias the protection diodes of
off channels over 2mA.

The MAX192 can be configured for differential (unipolar
or bipolar) or single-ended (unipolar only) inputs, as
selected by bits 2 and 3 of the control byte (Table 3).

In the single-ended mode, set the UNI/BIP bit to unipolar.
In this mode, analog inputs are internally referenced to
AGND, with a full-scale input range from 0V to V

REF

.

In differential mode, both unipolar and bipolar settings
can be used. Choosing unipolar mode sets the differen­tial input range at 0V to V

REF

. The output code is invalid
(code zero) when a negative differential input voltage is
applied. Bipolar mode sets the differential input range to
±V

REF

/ 2. Note that in this differential mode, the com­mon-mode input range includes both supply rails. Refer
to Tables 4a and 4b for input voltage ranges.

Quick Look

To evaluate the analog performance of the MAX192
quickly, use Figure 5’s circuit. The MAX192 requires a
control byte to be written to DIN before each
conversion. Tying DIN to +5V feeds in control bytes of

Low-Power, 8-Channel,
Serial 10-Bit ADC

8 _______________________________________________________________________________________

Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND

0 0 0 + –
1 0 0 + –
0 0 1 + –
1 0 1 + –
0 1 0 + –
1 1 0 + –
0 1 1 + –
1 1 1 + –