Maxim MAX188CMJP, MAX188CEWP, MAX188CEPP, MAX188CEAP, MAX188CCWP Datasheet

...

_______________General Description

The MAX186/MAX188 are 12-bit data-acquisition systems that combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface together with high conversion speed and ultra-low power consumption. The devices operate with a single +5V supply or dual ±5V supplies. The analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation.

The 4-wire serial interface directly connects to SPI™, QSPI™ and Microwire™ devices without external logic. A serial strobe output allows direct connection to TMS320 family digital signal processors. The MAX186/MAX188 use either the internal clock or an external serial-interface clock to perform successive-approximation A/D conversions. The serial interface can operate beyond 4MHz when the internal clock is used.

The MAX186 has an internal 4.096V reference while the MAX188 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim .

The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10µA at reduced sampling rates.

The MAX186/MAX188 are available in 20-pin DIP and SO packages, and in a shrink small-outline package (SSOP), that occupies 30% less area than an 8-pin DIP. For applications that call for a parallel interface, see the MAX180/MAX181 data sheet. For anti-aliasing filters, consult the MAX274/MAX275 data sheet.

________________________Applications

Portable Data Logging Data-Acquisition High-Accuracy Process Control Automatic Testing Robotics Battery-Powered Instruments Medical Instruments

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Single +5V or ±5V Operation ♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate ♦ Internal 4.096V Reference (MAX186) ♦ SPI-, QSPI-, Microwire-, TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs ♦ 20-Pin DIP, SO, SSOP Packages ♦ Evaluation Kit Available

______________Ordering Information

Ordering Information continued on last page.

†

NOTE: Parts are offered in grades A, B, C and D (grades defined in Electrical Characteristics). When ordering, please specify grade. Contact factory for availability of A-grade in SSOP package. * Dice are specified at +25°C, DC parameters only. * * Contact factory for availability and processing to MIL-STD-883.

TEMP. RANGE

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

________________________________________________________________ Maxim Integrated Products

PART

†

PIN-PACKAGE

MAX186_CPP 20 Plastic DIP MAX186_CWP 20 SO

20 SSOP MAX186DC/D Dice* MAX186_EPP 20 Plastic DIP

MAX186_CAP

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9

TOP VIEW

DIP/SO/SSOP



SCLK CS

DIN SSTRB DOUT DGND AGND REFADJ VREFSHDN

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

MAX186 MAX188

____________________Pin Configuration

0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C

MAX186_EWP 20 SO MAX186_EAP -40°C to +85°C 20 SSOP MAX186_MJP -55°C to +125°C 20 CERDIP**

SPI and QSPI are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor.

-40°C to +85°C

19-0123; Rev. 4; 8/96

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

EVALUATION KIT

AVAILABLE

Relative Accuracy (Note 2)

MAX186/MAX188

Low-Power, 8-Channel, Serial 12-Bit ADCs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 5V ±5%; VSS= 0V or -5V; f

CLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T

= T

MIN

to T

MAX

, unless otherwise

noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PARAMETER SYMBOL MIN TYP MAX UNITS

±1.0

LSB

±0.75

±1.0

±0.5

Differential Nonlinearity DNL ±1 LSB

±2.0 ±3.0 ±3.0

Resolution 12 Bits

±0.5

Offset Error

±3.0

LSB

±3.0 ±1.5 ±2.0 ±2.0

Gain Error (Note 3)

±3.0

LSB

Gain Temperature Coefficient ±0.8 ppm/°C

±0.1 LSB

SINAD 70 dB

THD -80 dB

Spurious-Free Dynamic Range SFDR 80 dB Channel-to-Channel Crosstalk -85 dB

CONDITIONS

MAX186D/MAX188D

MAX186 (all grades)

MAX188C

MAX186C

MAX186B/MAX188B

No missing codes over temperature MAX186A/MAX188A MAX186B/MAX188B MAX186C/MAX188C

External reference

4.096V (MAX188)

External reference, 4.096V

MAX186A/MAX188A

65kHz, VIN= 4.096V

P-P

(Note 4)

VDDto AGND............................................................-0.3V to +6V

VSSto AGND............................................................+0.3V to -6V

VDDto VSS..............................................................-0.3V to +12V

AGND to DGND.....................................................-0.3V to +0.3V

CH0–CH7 to AGND, DGND.............(VSS- 0.3V) to (VDD+ 0.3V)

CH0–CH7 Total Input Current ..........................................±20mA

VREF to AGND ...........................................-0.3V to (VDD+ 0.3V)

REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)

Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)

Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)

Digital Output Sink Current.................................................25mA

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW

SO (derate 10.00mW/°C above +70°C)........................800mW

SSOP (derate 8.00mW/°C above +70°C) .....................640mW

CERDIP (derate 11.11mW/°C above +70°C)................889mW

Operating Temperature Ranges:

MAX186_C/MAX188_C........................................0°C to +70°C

MAX186_E/MAX188_E......................................-40°C to +85°C

MAX186_M/MAX188_M..................................-55°C to +125°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

MAX188A MAX188B MAX188C MAX188D

Channel-to-Channel Offset Matching

Signal-to-Noise + Distortion Ratio Total Harmonic Distortion

(up to the 5th harmonic)

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096V

P-P

, 133ksps, 2.0MHz external clock, bipolar input mode)

External Clock Frequency Range

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________ 3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Small-Signal Bandwidth -3dB rolloff 4.5 MHz Full-Power Bandwidth 800 kHz

Internal clock 5.5 10

Conversion Time (Note 5) t

CONV

External clock, 2MHz, 12 clocks/conversion 6

µs

Track/Hold Acquisition Time t

1.5 µs Aperture Delay 10 ns Aperture Jitter <50 ps Internal Clock Frequency 1.7 MHz

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

CLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T

= T

MIN

to T

MAX

, unless otherwise

noted.)

External compensation, 4.7µF

0.1 2.0 Internal compensation (Note 6) 0.1 0.4 Used for data transfer only 10

MHz

Unipolar, VSS= 0V

Input Voltage Range, Single-Ended and Differential (Note 9)

Bipolar, VSS= -5V

Multiplexer Leakage Current

On/off leakage current, VIN= ±5V

±0.01 ±1 µA

Input Capacitance (Note 6) 16 pF

VREF Output Voltage

TA= +25°C

4.076 4.096 4.116 V

VREF Short-Circuit Current 30 mA

MAX186A, MAX186B, MAX186C

±30 ±50 ±30 ±60 ±30 ±80

VREF Tempco

MAX186D ±30

ppm/°C

Load Regulation (Note 7) 0mA to 0.5mA output load 2.5 mV

Internal compensation 0

Capacitive Bypass at VREF

External compensation 4.7

µF

Internal compensation 0.01

Capacitive Bypass at REFADJ

External compensation 0.01

µF

MAX186_C MAX186_E MAX186_M

REFADJ Adjustment Range ±1.5 %

±VREF/2

0 to

VREF

Input Voltage Range V Input Current 200 350 µA

Input Resistance 12 20 kΩ Shutdown VREF Input Current 1.5 10 µA

Buffer Disable Threshold REFADJ

VDD50mV

2.50

50mV

CONVERSION RATE

ANALOG INPUT

INTERNAL REFERENCE (MAX186 only, reference buffer enabled)

EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V)

MAX186/MAX188

Low-Power, 8-Channel, Serial 12-Bit ADCs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

CLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T

= T

MIN

to T

MAX

, unless otherwise

noted.)

PARAMETER

SYMBOL CONDITIONS MIN TYP MAX

Internal compensation mode 0

µFCapacitive Bypass at VREF

External compensation mode 4.7 MAX186 1.678

V/V

MAX188 1.638 MAX186 ±50

µAREFADJ Input Current

MAX188 ±5

INH

2.4 V

INL

0.8 V

DIN, SCLK, CS Input Hysteresis

HYST

0.15 V

DIN, SCLK, CS Input Leakage

VIN= 0V or V

±1 µA

(Note 6) 15 pF

SHDN Input High Voltage

INH

VDD- 0.5 V

SHDN Input Low Voltage

INL

0.5 V

SHDN Input Current, High

INH

SHDN = V

4.0 µA

SHDN Input Current, Low

INL

SHDN = 0V

-4.0 µA

SHDN Input Mid Voltage

SHDN Voltage, Floating

FLT

SHDN = open

2.75 V

SHDN = open

-100 100 nA

SINK

= 5mA 0.4

Output Voltage Low V

SINK

= 16mA 0.3

Output Voltage High V

SOURCE

= 1mA 4 V

Three-State Leakage Current I

CS = 5V

±10 µA

Three-State Output Capacitance C

OUT

CS = 5V (Note 6)

15 pF

Positive Supply Voltage V

5 ±5% V

DIN, SCLK, CS Input Capacitance

SHDN Max Allowed Leakage, Mid Input

Negative Supply Voltage V

0 or

-5 ±5%

Operating mode 1.5 2.5 Fast power-down 30 70

Positive Supply Current I

Full power-down 210 Operating mode and fast power-down 50

Negative Supply Current I

Full power-down 10

µA

DIN, SCLK, CS Input Low Voltage

DIN, SCLK, CS Input High Voltage

1.5 VDD-1.5

DIGITAL INPUTS (DIN, SCLK, CS,

SHDN

)

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER REQUIREMENTS

UNITS

EXTERNAL REFERENCE AT REFADJ

Reference-Buffer Gain

Note 1: Tested at VDD= 5.0V; VSS= 0V; unipolar input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled. Note 4: Ground on-channel; sine wave applied to all off channels. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Guaranteed by design. Not subject to production testing. Note 7: External load should not change during conversion for specified accuracy. Note 8: Measured at V

SUPPLY

+5% and V

SUPPLY

-5% only.

Note 9: The common-mode range for the analog inputs is from V

to VDD.

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________ 5

PARAMETER SYMBOL CONDITIONS UNITS

Positive Supply Rejection (Note 8)

PSR ±0.06 ±0.5 mV

Negative Supply Rejection (Note 8)

PSR

VSS= -5V ±5%; external reference, 4.096V; full-scale input

±0.01 ±0.5 mV

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

CLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T

= T

MIN

to T

MAX

, unless otherwise

noted.)

TIMING CHARACTERISTICS

(VDD= 5V ±5%; V

=0V or -5V, TA= T

MIN

to T

MAX

, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS UNITS

SCLK Pulse Width Low

200 ns

SCLK Fall to SSTRB

SSTRB

LOAD

= 100pF

200 ns

SDV

External clock mode only, C

LOAD

= 100pF

200 ns

STR

External clock mode only, C

LOAD

= 100pF

200 ns

SCK

Internal clock mode only 0 ns

Acquisition Time

1.5 µs

DIN to SCLK Setup

100 ns

DIN to SCLK Hold

0 ns

LOAD

= 100pF

20 150 ns

SCLK Fall to Output Data Valid

20 200 ns

CS Fall to Output Enable

LOAD

= 100pF

100 ns

CS Rise to Output Disable

LOAD

= 100pF

100 ns

CS to SCLK Rise Setup

CSS

100 ns

CS to SCLK Rise Hold

CSH

0 ns

SCLK Pulse Width High

200 ns

MAX18_ _C/E MAX18_ _M

SSTRB Rise to SCLK Rise (Note 6)

CS Fall to SSTRB Output Enable (Note 6)

VDD= 5V ±5%; external reference, 4.096V; full-scale input

MIN TYP MAX

CS Rise to SSTRB Output Disable (Note 6)

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier (4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an input when used with a precision external reference.

MAX186/MAX188

Low-Power, 8-Channel, Serial 12-Bit ADCs

________________________________________________________________________________________________

__________________________________________Typical Operating Characteristics

0.30

-0.05

-60 140

POWER-SUPPLY REJECTION

vs. TEMPERATURE

0.00

0.25

TEMPERATURE (°C)

PSR (LSBs)

0.10

0.05

-40 20 100

0.15

0.20

-20 0 40 80 120

VDD = +5V ±5% VSS = 0V or -5V

2.456

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.452

2.455

TEMPERATURE (°C)

VREFADJ (V)

2.454

2.453

-40 -20 0 20 40 60 80 100 120

0.16

-60 -20 60 140

CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE

0.02

0.12

TEMPERATURE (°C)

OFFSET MATCHING (LSBs)

20 100

0.10

0.04

-40 0 40 80 120

0.14

0.08

0.06

-140 0

66.5kHz

MAX186/MAX188 FFT PLOT – 133kHz

-120



-80

-100

 

-40

-20

   

-60

ft = 10kHz fs = 133kHz 

33.25kHz

AMPLITUDE (dB)

FREQUENCY

ft = 10kHz f

= 133kHz

= +25°C



PIN NAME FUNCTION

1-8 CH0-CH7 Sampling Analog Inputs

Negative Supply Voltage. Tie to -5V ±5% or AGND

SHDN

11 VREF

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10µA (max) supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

_____________________________________________________________Pin Description

Digital Ground

Positive Supply Voltage, +5V ±5%

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________ 7

PIN NAME FUNCTION

12 REFADJ

13 AGND Analog Ground. Also IN- Input for single-ended conversions. 14 DGND 15 DOUT

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.

16 SSTRB

17 DIN

19 SCLK

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance whenCS is high (external mode).

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance.

Serial Data Input. Data is clocked in at the rising edge of SCLK.

+5V

LOAD

DGND

DOUT

LOAD

DGND

DOUT

a. High-Z to V

and VOL to V

b. High-Z to VOL and VOH to V

+5V

LOAD

DGND

DOUT

LOAD

DGND

DOUT

a VOH to High-Z b VOL to High-Z

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disabled Time



INPUT SHIFT

CONTROL

LOGIC

INT

CLOCK

OUTPUT

SHIFT

+2.46V

REFERENCE

(MAX186)

T/H

ANALOG

INPUT

MUX

12-BIT

SAR ADC

DOUT SSTRB

DGND V

SCLK

DIN

CH0 CH1

CH3

CH2

CH7

CH6

CH5

CH4

AGND

REFADJ

VREF

OUT

REF

CLOCK

+4.096V

20k

≈ 1.65

1 2 3

4 5

6 7

15 16

18 19

MAX186 MAX188

SHDN

20 14

Figure 3. Block Diagram

________________________________________________Pin Description (continued)

MAX186/MAX188

_______________Detailed Description

The MAX186/MAX188 use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX186/MAX188.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog comparator is illustrated in the Equivalent Input Circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0-CH7 and IN- is switched to AGND. In differential mode, IN+ and IN- are selected from pairs of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7. Configure the channels with Table 3 and Table 4.

In differential mode, IN- and IN+ are internally switched to either one of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1µF capacitor from AIN- (the selected analog input, respectively) to AGND.

During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor C

HOLD

. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on C

HOLD

as a sample of the signal at IN+.

The conversion interval begins with the input multiplexer switching C

HOLD

from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply AGND. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x [(V

+) - (VIN-)] from C

HOLD

to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. The T/H enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for

single-ended inputs, IN- is connected to AGND, and the converter samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the difference of

|IN+ - IN-| is sampled. At

the end of the conversion, the positive input connects back to IN+, and C

HOLD

charges to the input signal.

The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by:

= 9 x (RS+ RIN) x 16pF,

where R

= 5kΩ, RS= the source impedance of the

input signal, and t

is never less than 1.5µs. Note that source impedances below 5kΩ do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.

Low-Power, 8-Channel, Serial 12-Bit ADCs

8 _______________________________________________________________________________________

CH0 CH1

CH2 CH3 CH4 CH5 CH6 CH7

AGND

SWITCH

TRACK

T/H

SWITCH

10k R

HOLD

12-BIT CAPACITIVE DAC

VREF

ZERO

COMPARATOR

–

16pF

SINGLE-ENDED MODE: IN+ = CHO-CH7, IN– = AGND. DIFFERENTIAL MODE: IN+ AND IN– SELECTED FROM PAIRS OF  CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES  FROM THE SELECTED IN+  CHANNEL TO THE SELECTED  IN– CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit

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