MAXIM MAX187, MAX189 Technical data

查询MAX187ACPA供应商

19-0196; Rev 0; 10/93

EVALUATION KIT MANUAL

FOLLOWS DATA SHEET

+5V, Low-Power, 12-Bit Serial ADCs

__________________General Description

The MAX187/MAX189 serial 12-bit analog-to-digital
converters (ADCs) operate from a single +5V supply
and accept a 0V to 5V analog input. Both parts feature
an 8.5µs successive-approximation ADC, a fast
track/hold (1.5µs), an on-chip clock, and a high-speed
3-wire serial interface.

The MAX187/MAX189 digitize signals at a 75ksps
throughput rate. An external clock accesses data from
the interface, which communicates without external
hardware to most digital signal processors and micro­controllers. The interface is compatible with SPI™,
QSPI™, and Microwire™.

The MAX187 has an on-chip buffered reference, and
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin DIP and
16-pin SO packages. Power consumption is 7.5mW
and reduces to only 10µW in shutdown.

Excellent AC characteristics and very low power con­sumption combined with ease of use and small pack­age size make these converters ideal for remote DSP
and sensor applications, or for circuits where power
consumption and space are crucial.

___________________________Applications

Portable Data Logging
Remote Digital Signal Processing
Isolated Data Acquisition
High-Accuracy Process Control

________________Functional Diagram

________________________________Features

♦ 12-Bit Resolution

1

⁄2 LSB Integral Nonlinearity (MAX187A/MAX189A)

♦ ±
♦ Internal Track/Hold, 75kHz Sampling Rate
♦ Single +5V Operation
♦ Low Power: 2µA Shutdown Current

1.5mA Operating Current

♦ Internal 4.096V Buffered Reference (MAX187)
♦ 3-Wire Serial Interface, Compatible with SPI,

QSPI, and Microwire

♦ Small-Footprint 8-Pin DIP and 16-Pin SO

_________________Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX187ACPA 0°C to +70°C 8 Plastic DIP ±

MAX187BCPA 0°C to +70°C 8 Plastic DIP ±1
MAX187CCPA 0°C to +70°C 8 Plastic DIP ±2
MAX187ACWE 0°C to +70°C 16 Wide SO ±
MAX187BCWE 0°C to +70°C 16 Wide SO ±1
MAX187CCWE 0°C to +70°C 16 Wide SO ±2
MAX187BC/D 0°C to +70°C Dice* ±1

Ordering Information continued on last page.

* Dice are specified at T
** Contact factory for availability and processing to MIL-STD-883.

= +25°C, DC parameters only.

A

ERROR

(LSB)

1

⁄2

1

⁄2

_________________Pin Configurations

MAX187/MAX189

6

SAR

AND

8

7

3

DOUT
SCLK

CS

SHDN

DAC

OUTPUT

SHIFT

REGISTER

12-BIT

CONTROL

TIMING

5

GND

+2.5V
BANDGAP
REFERENCE

(MAX187 ONLY)

4

REF

2

T/H

AIN

1

V

DD

NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY.

™ SPI and QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.

AV = 1.638

10k

MAX187
MAX189

________________________________________________________________

REF-

(4.096V)

REF+

COMPARATOR

BUFFER ENABLE/DISABLE

TOP VIEW

V

DD

1

AIN

2

SHDN

REF

Pin Configurations continued on last page.

MAX187

3

MAX189

4

DIP

Maxim Integrated Products

Call toll free 1-800-998-8800 for free samples or literature.

8

SCLK
CS

7

DOUT

6
5

GND

1

+5V, Low-Power, 12-Bit Serial ADCs

ABSOLUTE MAXIMUM RATINGS

to GND.............................................................-0.3V to +6V

V

DD

AIN to GND................................................-0.3V to (V

REF to GND...............................................-0.3V to (V

Digital Inputs to GND.................................-0.3V to (V

Digital Outputs to GND..............................-0.3V to (V

SHDN

to GND.............................................-0.3V to (V

REF Load Current (MAX187) .........................4.0mA Continuous

REF Short-Circuit Duration (MAX187)................................20sec

DOUT Current..................................................................±20mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

MAX187/MAX189

(VDD= +5V ±5%; GND = 0V; unipolar input mode; 75ksps, f
reference: V
capacitor at REF pin; T

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 1)

Resolution 12 Bits

Relative Accuracy (Note 2) MAX18_B ±1 LSB

Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Offset Error

Gain Error (Note 3)

Gain Temperature Coefficient External reference, 4.096V ±0.8 ppm/°C

DYNAMIC SPECIFICATIONS

Signal-to-Noise plus
Distortion Ratio

Total Harmonic Distortion
(up to the 5th harmonic)

Spurious-Free Dynamic Range SFDR 80 dB
Small-Signal Bandwidth Rolloff -3dB 4.5 MHz
Full-Power Bandwidth 0.8 MHz

= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V

REF

= T

to T

A

MIN

; unless otherwise noted.)

MAX

MAX18_A ±

MAX18_C ±2

MAX18_A ±1
MAX18_B/C ±3
MAX187 ±3
MAX189A ±1
MAX189B/C ±3

(10kHz sine wave input, 0V to 4.096V

SINAD 70 dB

THD -80 dB

DD
DD
DD
DD
DD

+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)

Continuous Power Dissipation (T

8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)..500mW
16-Pin Wide SO (derate 8.70mW/°C above +70°C)...478mW

8-Pin CERDIP (derate 8.00mW/°C above +70°C) ......440mW

Operating Temperature Ranges:

MAX187_C_ _/MAX189_C_ _.............................0°C to +70°C

MAX187_E_ _/MAX189_E_ _..........................-40°C to +85°C

MAX187_MJA/MAX189_MJA .......................-55°C to +125°C

Storage Temperature Range............................-60°C to +150°C

Lead Temperature (soldering, 10sec)............................+300°C

= 4.0MHz, external clock (50% duty cycle); MAX187—internal

CLK

, 75ksps)

p-p

REF

= +70°C)

A

= 4.096V applied to REF pin, 4.7µF

1

⁄2

1

⁄2

LSB

LSB

2 _______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%; GND = 0V; unipolar input mode; 75ksps, f
reference: V
capacitor at REF pin; T

CONVERSION RATE

Conversion Time t
Track/Hold Acquisition Time t
Throughput Rate External clock, 4MHz, 13 clocks 75 ksps
Aperture Delay t
Aperture Jitter <50 ps

ANALOG INPUT

Input Voltage Range 0 to V
Input Capacitance (Note 4) 16 pF
INTERNAL REFERENCE (MAX187 only, reference buffer enabled)

REF Output Voltage V

REF Short-Circuit Current 30 mA

REF Tempco

Load Regulation (Note 5) 0mA to 0.6mA output load 1 mV
EXTERNAL REFERENCE AT REF (Buffer disabled, V
Input Voltage Range 2.50 V
Input Current 200 350 µA
Input Resistance 12 20 kΩ
Shutdown REF Input Current 1.5 10 µA

= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V

REF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= T

to T

A

MIN

; unless otherwise noted.)

MAX

CONV

ACQ

APR

TA= +25°C 4.076 4.096 4.116

REF

TA= T

MAX187AC/BC ±30 ±50
MAX187AE/BE ±30 ±60
MAX187AM/BM ±30 ±80
MAX187C ±30

MIN

to T

REF

MAX

= 4.0MHz, external clock (50% duty cycle); MAX187—internal

CLK

MAX187_C 4.060 4.132
MAX187_E 4.050 4.140
MAX187_M 4.040 4.150

= 4.096V)

= 4.096V applied to REF pin, 4.7µF

REF

5.5 8.5 µs

1.5 µs

10 ns

DD

REF

ppm/°C

+ 50mV V

MAX187/MAX189

V

V

_______________________________________________________________________________________ 3

+5V, Low-Power, 12-Bit Serial ADCs

SHDN

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%; GND = 0V; unipolar input mode; 75ksps, f
reference: V
capacitor at REF pin; T

= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V

REF

= T

to T

A

MIN

; unless otherwise noted.)

MAX

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SCLK, CS,

SCLK, CSInput High Voltage V
SCLK, CSInput Low Voltage V
SCLK, CSInput Hysteresis V
SCLK, CSInput Leakage I
SCLK, CSInput Capacitance C

SHDN

MAX187/MAX189

Input High Voltage V

SHDN

Input Low Voltage V

SHDN

Input Current I

SHDN

Input Mid Voltage V

SHDN

Voltage, Floating V

SHDN

Maximum Allowed

Leakage, Mid Input

)

INH
INL

HYST

VIN= 0V or V

IN

(Note 4) 15 pF

IN

INSH

INSL

SHDN

INS

IM

FLT

= VDDor 0V ±4.0 µA

SHDN

= open 2.75 V

SHDN

= open -100 100 nA

DIGITAL OUTPUT (DOUT)

I

= 5mA 0.4

Output Voltage Low V

Output Voltage High V
Three-State Leakage Current I
Three-State Output

Capacitance

C

SINK

OL

I

SINK

OHISOURCE

CS

L

OUT

= 5V ±10 µA

CS

= 5V (Note 4) 15 pF

= 16mA 0.3

= 1mA 4 V

POWER REQUIREMENTS

Supply Voltage V

Supply Current

DD

I

DD

Operating mode

Power-down mode 2 10 µA

DD

= 4.0MHz, external clock (50% duty cycle); MAX187—internal

CLK

MAX187 1.5 2.5
MAX189 1.0 2.0

= 4.096V applied to REF pin, 4.7µF

REF

2.4 V

0.8 V

0.15 V
±1 µA

V

- 0.5 V

DD

0.5 V

1.5 VDD-1.5 V

4.75 5.25 V

V

mA

Power-Supply Rejection PSR

VDD= +5V, ±5%; external reference, 4.096V;
full-scale input (Note 6)

±0.06 ±0.5 mV

4 _______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

TIMING CHARACTERISTICS

(VDD= +5.0V ±5%, TA= T

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Track/Hold Acquisition Time t

SCLK Fall to Output Data Valid t

CS

Fall to Output Enable t

CS

Rise to Output Disable t
SCLK Clock Frequency f
SCLK Pulse Width High t
SCLK Pulse Width Low t

CS

SCLK Low to
Setup Time

CS

Pulse Width t

Note 1: Tested at VDD= +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, t

Fall

been calibrated.

time needed for the signal to be acquired.

MIN

to T

, unless otherwise noted.)

MAX

CS

ACQ

C

DO

LOAD

C

DV

LOAD

C

TR

LOAD

SCLK

CH

CL

t

CSO

CS

is the maximum time the device takes to acquire the signal, and is also the minimum

ACQ

= high (Note 7) 1.5 µs

= 100pF

= 100pF 100 ns
= 100pF 100 ns

MAX18_ _C/E 20 150
MAX18_ _M 20 200

5 MHz
100 ns
100 ns

50 ns

500 ns

MAX187/MAX189

ns

_______________________________________________________________________________________ 5

+5V, Low-Power, 12-Bit Serial ADCs

________________________________________________T ypical Operating Characteristics

POWER-SUPPLY REJECTION vs.

0.16

0.14

0.12

0.10

0.08

0.06

0.04

MAX187/MAX189

POWER-SUPPLY REJECTION (mV)

0.02
0

-60 -20 20 60 100 140

SUPPLY CURRENT vs. TEMPERATURE

2.2

1.8

1.4

1.0

SUPPLY CURRENT (mA)

0.6

0.2

-60 -20 20 60 100 140

TEMPERATURE

TEMPERATURE (°C)

MAX187

MAX189

TEMPERATURE (°C)

vs. TEMPERATURE

V

4.090

4.089

4.088

4.087

4.086

4.085

4.084

4.083

4.082

INTERNAL REFERENCE VOLTAGE (V)

4.081

4.080

REF

-60 -20 20 60 140
TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT vs.

TEMPERATURE

7

6
5

4

3

2

SHUTDOWN SUPPLY CURRENT (µA)

1

0

-60 -20 20 60 100 140
TEMPERATURE (°C)



100

6 _______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

_______________________________________________________________________Pin Description

PIN

DIP WIDE SO

11VDDSupply voltage, +5V ±5%
2 3 AIN Sampling analog input, 0V to V

36SHDN

4 8 REF

5 — GND Analog and digital ground
— 10 AGND Analog ground
— 11 DGND Digital ground

6 12 DOUT Serial data output. Data changes state at SCLK’s falling edge.

715

8 16 SCLK Serial clock input. Clocks data out with rates up to 5MHz.
— 2,4,5,7,9,13,14 N.C. Not internally connected. Connect to AGND for best noise performance.

_______________Detailed Description

The MAX187/MAX189 use input track/hold (T/H) and
successive approximation register (SAR) circuitry to
convert an analog input signal to a digital 12-bit output.
No external hold capacitor is needed for the T/H.
Figures 3a and 3b show the MAX187/MAX189 in their
simplest configuration. The MAX187/MAX189 convert
input signals in the 0V to V
T/H acquisition time. The MAX187’s internal reference
is trimmed to 4.096V, while the MAX189 requires an
external reference. Both devices accept external refer­ence voltages from +2.5V to VDD. The serial interface
requires only three digital lines, SCLK,
and provides easy interface to microprocessors (µPs).

Both converters have two modes: normal and shut­down. Pulling
reduces supply current to below 10µA, while pulling

SHDN

high or leaving it floating puts the device into the
operational mode. A conversion is initiated by
falling. The conversion result is available at DOUT in

SHDN

low shuts the device down and

NAME FUNCTION

Three-level shutdown input. Pulling

CS

down to 10µA (max) supply current. Both MAX187 and MAX189 are fully opera­tional with either
enables the internal reference, and letting
reference and allows for the use of an external reference.

Reference voltage—sets analog voltage range and functions as a 4.096V output
for the MAX187 with enabled internal reference. REF also serves as a +2.5V to
V

input for a precision reference for both MAX187 (disabled internal reference)

DD

and MAX189. Bypass with 4.7µF if internal reference is used, and with 0.1µF if an
external reference is applied.

Active-low chip select initiates conversions on the falling edge. When CSis high,
DOUT is high impedance.

SHDN

high or floating. For the MAX187, pulling

unipolar serial format. A high bit, signaling the end of
conversion (EOC), followed by the data bits (MSB first),

Converter Operation

make up the serial data stream.
The MAX187 operates in one of two states: (1) internal

reference and (2) external reference. Select internal
reference operation by forcing
reference operation by floating

range in 10µs, including

REF

Figure 4 illustrates the sampling architecture of the
ADC’s analog comparator. The full-scale input voltage
depends on the voltage at REF.

CS,

and DOUT,

REFERENCE

Internal Reference
(MAX187 only)

External Reference 0V V

For specified accuracy, the external reference voltage
range spans from +2.5V to VDD.

CS

REF

range

SHDN

low shuts the MAX187/MAX189

SHDN

float disables the internal

SHDN
SHDN

ZERO FULL
SCALE SCALE

0V +4.096V

SHDN

high

high, and external

.

Analog Input

REF

MAX187/MAX189

_______________________________________________________________________________________ 7

+5V, Low-Power, 12-Bit Serial ADCs

+5V

3k

DOUT DOUT

3k

DGND

MAX187/MAX189

a. High-Z to VOH and VOL to V

Figure 1. Load Circuits for DOUT Enable Time

DOUT DOUT

3k

DGND

to High-Z

OH

Figure 2. Load Circuits for DOUT Disable Time

C

= 100pF C

LOAD

OH

C

= 100pF C

LOAD

LOAD

DGND

b. High-Z to VOL and VOH to V

+5V

3k

LOAD

DGND

b. VOLto High-Za. V

= 100pF

OL

= 100pF

8 _______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

4.7µF

0.1µF

4.7µF

0.1µF

MAX187/MAX189

8

SCLK

7

CS



6

DOUT

5

GND

SERIAL
INTERFACE

ANALOG INPUT

0V TO +5V

SHUTDOWN

INPUT

OFF

4.7µF

1

+5V

ON

V

DD

2

MAX187

AIN

3

SHDN

4

REF

Figure 3a. MAX187 Operational Diagram

12-BIT CAPACITIVE DAC

REF

AIN

C

PACKAGE

GND

TRACK

HOLD

INPUT

C

SWITCH

C

HOLD

-+
16pF

TRACK

5k

R

COMPARATOR

ZERO

IN

HOLD

AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.

Figure 4. Equivalent Input Circuit

Track/Hold

In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.

During acquisition, the analog input AIN charges
capacitor C

. Bringing CSlow ends the acquisition

HOLD

SCLK

DOUT

GND

8

7

CS

6

5

SERIAL
INTERFACE

ANALOG INPUT

0V TO +5V

SHUTDOWN

INPUT

OFF

REFERENCE

INPUT

0.1µF

1

+5V

ON

V

DD

2

MAX189

AIN

3

SHDN

4

REF

Figure 3b. MAX189 Operational Diagram

interval. At this instant, the T/H switches the input side
of C
resents a sample of the input, unbalancing the node

to GND. The retained charge on C

HOLD

HOLD

rep-

ZERO at the comparator’s input.
In hold mode, the capacitive DAC adjusts during the

remainder of the conversion cycle to restore node
ZERO to 0V within the limits of a 12-bit resolution. This
action is equivalent to transferring a charge from
C

to the binary-weighted capacitive DAC, which in

HOLD

turn forms a digital representation of the analog input
signal. At the conversion’s end, the input side of C
switches back to AIN, and C
signal again.

charges to the input

HOLD

HOLD

The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. Acquisition time
is calculated by:

t

= 9 (RS+ RIN) 16pF,

ACQ

where RIN= 5kΩ, RS= the source impedance of the
input signal, and t
impedances below 5kΩ do not significantly affect the

is never less than 1.5µs. Source

ACQ

AC performance of the ADC.

_______________________________________________________________________________________ 9

+5V, Low-Power, 12-Bit Serial ADCs

The ADCs’ input tracking circuitry has a 4.5MHz small-

Input Bandwidth

signal bandwidth, and an 8V/µs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC's
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is rec­ommended. See the MAX274/MAX275 continuous-time
filters data sheet.

Input Protection

Internal protection diodes that clamp the analog input
allow the input to swing from GND - 0.3V to VDD+ 0.3V
without damage. However, for accurate conversions
near full scale, the input must not exceed VDDby more
than 50mV, or be lower than GND by 50mV.

MAX187/MAX189

If the analog input exceeds the supplies by more than
50mV beyond the supplies, limit the input current to
2mA, since larger currents degrade conversion
accuracy.

Driving the Analog Input

The input lines to AIN and GND should be kept as short
as possible to minimize noise pickup. Shield longer
leads. Also see the

Input Protection

section

.

Because the MAX187/MAX189 incorporate a T/H, the
drive requirements of the op amp driving AIN are less
stringent than those for a successive-approximation
ADC without a T/H. The typical input capacitance is
16pF. The amplifier bandwidth should be sufficient to
handle the frequency of the input signal. The MAX400
and OP07 work well at lower frequencies. For higher­frequency operation, the MAX427 and OP27 are practi­cal choices. The allowed input frequency range is limit-

ed by the 75ksps sample rate of the MAX187/MAX189.
Therefore, the maximum sinusoidal input frequency
allowed is 37.5kHz. Higher-frequency signals cause
aliasing problems unless undersampling techniques
are used.

Reference

The MAX187 can be used with an internal or external ref­erence, while the MAX189 requires an external reference.

Internal Reference

The MAX187 has an on-chip reference with a buffered
temperature-compensated bandgap diode, laser­trimmed to +4.096V ±0.5%. Its output is connected to
REF and also drives the internal DAC. The output can
be used as a reference voltage source for other com­ponents and can source up to 0.6mA. Decouple REF
with a 4.7µF capacitor. The internal reference is
enabled by pulling the

SHDN

pin high. Letting

SHDN

float disables the internal reference, which allows the
use of an external reference, as described in the

External Reference

section.

External Reference

The MAX189 operates with an external reference at the
REF pin. To use the MAX187 with an external reference,
disable the internal reference by letting

SHDN

float. Stay
within the voltage range +2.5V to VDDto achieve speci­fied accuracy. The minimum input impedance is 12kΩ
for DC currents. During conversion, the external refer­ence must be able to deliver up to 350µA DC load cur­rent and have an output impedance of 10Ω or less. The
recommended minimum value for the bypass capacitor
is 0.1µF. If the reference has higher output impedance
or is noisy, bypass it close to the REF pin with a 4.7µF
capacitor.

COMPLETE CONVERSION SEQUENCE

CS

t

SHDN

DOUT

CONVERSION 0 CONVERSION 1

Figure 5. MAX187/MAX189 Shutdown Sequence

10 ______________________________________________________________________________________

WAKE

POWERED UPPOWERED DOWNPOWERED UP

SHDN

10000

+5V, Low-Power, 12-Bit Serial ADCs

MAX187/MAX189

3.0

1000

MAX187

100

10

SUPPLY CURRENT (µA)

1

0.1 1 10 100 1000 10000

Figure 6. Average Supply Current vs. Conversion Rate

*REF CONNECTED TO V

CONVERSIONS PER SECOND

MAX189*

DD

100000

____________________Serial Interface

Initialization After Power-Up and

When power is first applied, it takes the fully dis­charged 4.7µF reference bypass capacitor up to 20ms
to provide adequate charge for specified accuracy.
With

SHDN

not pulled low, the MAX187/MAX189 are

now ready to convert.
To start a conversion, pull CSlow. At

the T/H enters its hold mode and a conversion is initiat­ed. After an internally timed 8.5µs conversion period,
the end of conversion is signaled by DOUT pulling
high. Data can then be shifted out serially with the
external clock.

Using

Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conver­sions. This is shown in Figure 6, a plot of average sup­ply current vs. conversion rate. Because the MAX189
uses an external reference voltage (assumed to be pre­sent continuously), it "wakes up" from shutdown more
quickly, and therefore provides lower average supply
currents. The wakeup-time, t
SHDN deasserted to the time when a conversion may
be initiated. For the MAX187, this time is 2µs. For the
MAX189, this time depends on the time in shutdown
(see Figure 7) because the external 4.7µF reference
bypass capacitor loses charge slowly during shutdown
(see the specifications for shutdown, REF Input Current
= 10µA max).

Starting a Conversion

CS’s

falling edge,

to Reduce Supply Current

is the time from

WAKE,

2.5

2.0

(ms)

1.5

WAKE

t

1.0

0.5

0

0.0001 0.001 0.01 0.1 1 10
TIME IN SHUTDOWN (sec)

Figure 7. t

vs. Time in Shutdown (MAX187 only)

WAKE

External Clock

The actual conversion does not require the external
clock. This frees the µP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the µP’s convenience at any clock
rate from 0MHz to 5MHz. The clock duty cycle is unre­stricted if each clock phase is at least 100ns. Do not
run the clock while a conversion is in progress.

Timing and Control

Conversion-start and data-read operations are con­trolled by the CSand SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline the operation of the
serial interface.

A CSfalling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to con­vert, and DOUT changes from high impedance to logic
low. SCLK must be kept inactive during the conversion.
An internal register stores the data when the conversion
is in progress.

End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing
signal. SCLK shifts the data out of this register any time
after the conversion is complete. DOUT transitions on
SCLK’s falling edge. The next falling clock edge pro­duces the MSB of the conversion at DOUT, followed by
the remaining bits. Since there are 12 data bits and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occur­ring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing 0s at
DOUT and have no effect on converter operation.

______________________________________________________________________________________ 11

+5V, Low-Power, 12-Bit Serial ADCs

CS

SCLK

DOUT

INTERFACE IDLE

A/D 

TRACK

STATE

MAX187/MAX189

MINIMUM
CYCLE TIME

CONVERSION

IN PROGRESS

CONVERSION

0

CONV

EOC

EOC

0µs8.5µs (t

)

Figure 8. MAX187/MAX189 Interface Timing Sequence

CS

t

CS0

SCLK

t

CONV

DOUT

t

DV

t

APR

14 8 12

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CLOCK OUTPUT DATA

TRACK

12 × 0.250µs = 3.25µs

TOTAL = 12.25µs

…

t

CH

…

t

DO

…

t

CL

B2 B1 B0

TRAILING

ZEROS

0µs

IDLE

CONV. 1

0.5µs
(tCS)

t

CS

t

TR

INTERNAL

T/H

(TRACK)

(HOLD) (TRACK)

…

Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing

12 ______________________________________________________________________________________

OUTPUT CODE

11…111
11…110
11…101

+5V, Low-Power, 12-Bit Serial ADCs

20

FULL-SCALE

TRANSITION

0

-20

-40

fS = 75ksps
f

= 10kHz

T

T

= +25°C

A

MAX187/MAX189

FS = +4.096V

FS

1LSB =
4096

00…011
00…010
00…001

00…000

012 FS

Figure 10. MAX187/MAX189 Unipolar Transfer Function,

4.096V = Full Scale

3

FS - 3/2LSBINPUT VOLTAGE (LSBs)

Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
13 clock cycles at full speed. Raise CSafter the conver­sion’s LSB has been read. After the specified minimum
time, t
next conversion.

, CScan be pulled low again to initiate the

ACQ

Output Coding and Transfer Function

The data output from the MAX187/MAX189 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successive
integer LSB values. If V

= +4.096V, then

REF

1 LSB = 1.00mV or 4.096V/4096.

_____________Dynamic Performance

High-speed sampling capability and a 75ksps through­put make the MAX187/MAX189 ideal for wideband sig­nal processing. To support these and other related
applications, Fast Fourier Transform (FFT) test tech­niques are used to guarantee the ADC’s dynamic fre­quency response, distortion, and noise at the rated
throughput. Specifically, this involves applying a low­distortion sine wave to the ADC input and recording the
digital conversion results for a specified time. The data
is then analyzed using an FFT algorithm that deter­mines its spectral content. Conversion errors are then
seen as spectral elements outside of the fundamental

-60

AMPLITUDE (dB)

-80

-100

-120

-140
0 18.75 37.5

Figure 11. MAX187/MAX189 FFT plot

FREQUENCY (kHz)

input frequency. ADCs have traditionally been evaluat­ed by specifications such as Zero and Full-Scale Error,
Integral Nonlinearity (INL), and Differential Nonlinearity
(DNL). Such parameters are widely accepted for speci­fying performance with DC and slowly varying signals,
but are less useful in signal-processing applications,
where the ADC’s impact on the system transfer function
is the main concern. The significance of various DC
errors does not translate well to the dynamic case, so
different tests are required.

Signal-to-Noise Ratio and

Effective Number of Bits

Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS amplitude of all other ADC output signals. The
input bandwidth is limited to frequencies above DC and
below one-half the ADC sample (conversion) rate.

The theoretical minimum ADC noise is caused by quan­tization error and is a direct result of the ADC’s resolu­tion: SINAD = (6.02N + 1.76)dB, where N is the number
of bits of resolution. An ideal 12-bit ADC can, therefore,
do no better than 74dB. An FFT plot of the output
shows the output level in various spectral bands. Figure
11 shows the result of sampling a pure 10kHz sine
wave at a 75ksps rate with the MAX187/MAX189.

______________________________________________________________________________________ 13

+5V, Low-Power, 12-Bit Serial ADCs

12.2

12.0

11.8

11.6

11.4

11.2

11.0

10.8

EFFECTIVE BITS

10.6

10.4

10.2

MAX187/MAX189

1 10 100 1000

INPUT FREQUENCY (kHz)

(UNDERSAMPLED)

Figure 12. Effective Bits vs. Input Frequency

The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
above equation and substituting in the measured
SINAD: N = (SINAD - 1.76)/6.02. Figure 12 shows the
effective number of bits as a function of the input fre­quency for the MAX187/MAX189.

Total Harmonic Distortion

If a pure sine wave is sampled by an ADC at greater
than the Nyquist frequency, the nonlinearities in the
ADC’s transfer function create harmonics of the input
frequency present in the sampled output data.

Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not includ­ing the DC component) to the RMS amplitude of the
fundamental frequency. This is expressed as follows:

THD = 20log

√ V

+ V

2

2

+ V

3

4

V

1

+ … V

2

N

2

2

where V1is the fundamental RMS amplitude, and V
through VNare the amplitudes of the 2nd through Nth
harmonics. The THD specification in the

Characteristics

includes the 2nd through 5th

Electrical

harmonics.

a. SPI

b. QSPI

c. MICROWIRE

Figure 13. Common Serial-Interface Connections to the

2

MAX187/MAX189

SCK

MISO

SCK

MISO

I/O

+5V

CS
SCLK

DOUT

MAX187

SS

CS

+5V

MAX189

CS
SCLK

DOUT

MAX187

SS

I/O
SK

SI

MAX189

CS
SCLK

DOUT

MAX187
MAX189

14 ______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

____________Applications Information

The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and Microwire standard serial
interfaces.

If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser­ial clock. Choose a clock frequency up to 2.5MHz.

1. Use a general-purpose I/O line on the CPU to pull
low. Keep SCLK low.

2. Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a
DOUT rising edge to determine the end of
conversion.

3. Activate SCLK for a minimum of 13 clock cycles. The
first falling clock edge will produce the MSB of the
DOUT conversion. DOUT output data transitions on

SCLK

DOUT

Connection to Standard Interfaces

1ST BYTE READ 2ND BYTE READ

CS

t

CONV

HI-Z

MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB

CS

SCLK’s falling edge and is available in MSB-first for­mat. Observe the SCLK to DOUT valid timing charac­teristic. Data can be clocked into the µP on SCLK’s
rising edge.

CS

4. Pull

high at or after the 13th falling clock edge. If

CS

remains low, trailing zeros are clocked out after

the LSB.

5. With

CS

= high, wait the minimum specified time, tCS,

before launching a new conversion by pulling

CS

low. If a conversion is aborted by pulling CShigh
before the conversions end, wait for the minimum
acquisition time, t

, before starting a new

ACQ

conversion.

Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of
the conversion padded with one leading 1, and trailing
0s if SCLK is still active with CS kept low.

HI-Z

MAX187/MAX189

EOC

Figure 14. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)

SCLK

CS

t

CONV

HI-Z

DOUT

EOC

Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)

______________________________________________________________________________________ 15

MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB

HI-Z

+5V, Low-Power, 12-Bit Serial ADCs

When using SPI or QSPI, set CPOL = 0 and CPHA = 0.

SPI and Microwire

Conversion begins with a CSfalling edge. DOUT goes
low, indicating a conversion in progress. Wait until
DOUT goes high or the maximum specified 8.5µs con­version time. Two consecutive 1-byte reads are
required to get the full 12 bits from the ADC. DOUT out­put data transitions on SCLK’s falling edge and is
clocked into the µP on SCLK’s rising edge.

The first byte contains a leading 1 and 7 bits of conver­sion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections
and Figure 14 for timing.

Set CPOL = CPHA = 0. Unlike SPI, which requires two

MAX187/MAX189

1-byte reads to acquire the 12 bits of data from the
ADC, QSPI allows the minimum number of clock cycles
necessary to clock in the data. The MAX187/MAX189
require 13 clock cycles from the µP to clock out the

+5V ON THIS SIDE OF

BARRIER MUST BE ISOLATED POWER

MAX187

1
2
4

V
AIN
REF
GND

DD

SHDN

SCLK

DOUT

3
7

CS

8
6

3k

470Ω

ANALOG

INPUT

0.1µF

SIGNAL

GROUND

+5V

10µF

4.7µF5

3k

QSPI

12 bits of data with no trailing 0s (Figure 15). The maxi­mum clock frequency to ensure compatibility with QSPI
is 2.77MHz.

Opto-Isolated Interface,

Serial-to-Parallel Conversion

Many industrial applications require electrical isolation
to separate the control electronics from hazardous
electrical conditions, provide noise immunity, or pre­vent excessive current flow where ground disparities
exist between the ADC and the rest of the system.
Isolation amplifiers typically used to accomplish these
tasks are expensive. In cases where the signal is even­tually converted to a digital form, it is cost effective to
isolate the input using opto-couplers in a serial link.

The MAX187 is ideal in this application because it
includes both T/H amplifier and voltage reference,
operates from a single supply, and consumes very little
power (Figure 16).

CS/START

14

SER

11

SCK

12

RCK

10

SCLR

14

SER

11

SCK

12

RCK

10

SCLR

SCLK/INPUT CLOCK

QH
QG

74HC595

QF

QE
QD
QC
QB
QA

13 8

9

QH′

QH
QG

74HC595

QF

QE
QD
QC
QB
QA

13 8

6N136

8
7
6
5

6N136

8
7
6
5

6N136

1
2
3
4

+5V

1

200Ω

2
3
4

74HC04

1

200Ω

2
3
4

8
7
6
5

74HC04

8.2k

+5V

7
6
5
4
3
2
1
15

16

7
6
5
4
3
2
1
15
16

D11 (MSB)
D10
D9
D8
+5V

0.1µF

D7
D6
D5
D4
D3
D2
D1
D0(LSB)
+5V

0.1µF

Figure 16. 12-Bit Isolated ADC

16 ______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

The ADC results are transmitted across a 1500V isola­tion barrier provided by three 6N136 opto-isolators.
Isolated power must be supplied to the converter and
the isolated side of the opto-couplers. 74HC595 three­state shift registers are used to construct a 12-bit paral­lel data output. The timing sequence is identical to the
timing shown in Figure 8. Conversion speed is limited
by the delay through the opto-isolators. With a 140kHz
clock, conversion time is 100µs.

The universal 12-bit parallel data output can also be
used without the isolation stage when a parallel inter­face is required. Clock frequencies up to 2.9MHz are
possible without violating the 20ns shift-register setup
time. Delay or invert the clock signal to the shift regis­ters beyond 2.9MHz.

Layout, Grounding, Bypassing

For best performance, use printed circuit boards. Wire­wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi­tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.

Figure 17 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at GND, separate
from the logic ground. All other analog grounds should
be connected to this ground. The 16-pin versions also
have a dedicated DGND pin available. Connect DGND
to this star ground point for further noise reduction. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped­ance and as short as possible for noise-free operation.

High-frequency noise in the VDDpower supply may
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 4.7µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection. If the +5V
power supply is very noisy, a 10Ω resistor can be con­nected as a lowpass filter to attenuate supply noise
(Figure 17).

SUPPLIES

+5V GND

R* = 10Ω

4.7µF

0.01µF

DD

MAX187
MAX189

*OPTIONAL

Figure 17. Power-Supply Grounding Condition

DGNDAGNDV

DGND+5V

DIGITAL

CIRCUITRY

MAX187/MAX189

______________________________________________________________________________________ 17

+5V, Low-Power, 12-Bit Serial ADCs

__Ordering Information (continued)

PART TEMP. RANGE PIN-PACKAGE

MAX187AEPA -40°C to +85°C 8 Plastic DIP ±
MAX187BEPA -40°C to +85°C 8 Plastic DIP ±1
MAX187CEPA -40°C to +85°C 8 Plastic DIP ±2
MAX187AEWE -40°C to +85°C 16 Wide SO ±
MAX187BEWE -40°C to +85°C 16 Wide SO ±1
MAX187CEWE -40°C to +85°C 16 Wide SO ±2
MAX187AMJA -55°C to +125°C 8 CERDIP** ±
MAX187BMJA -55°C to +125°C 8 CERDIP** ±1
MAX189ACPA 0°C to +70°C 8 Plastic DIP ±

MAX187/MAX189

MAX189BCPA 0°C to +70°C 8 Plastic DIP ±1
MAX189CCPA 0°C to +70°C 8 Plastic DIP ±2
MAX189ACWE 0°C to +70°C 16 Wide SO ±
MAX189BCWE 0°C to +70°C 16 Wide SO ±1
MAX189CCWE 0°C to +70°C 16 Wide SO ±2
MAX189BC/D 0°C to +70°C Dice* ±1
MAX189AEPA -40°C to +85°C 8 Plastic DIP ±
MAX189BEPA -40°C to +85°C 8 Plastic DIP ±1
MAX189CEPA -40°C to +85°C 8 Plastic DIP ±2
MAX189AEWE -40°C to +85°C 16 Wide SO ±
MAX189BEWE -40°C to +85°C 16 Wide SO ±1
MAX189CEWE -40°C to +85°C 16 Wide SO ±2
MAX189AMJA -55°C to +125°C 8 CERDIP** ±
MAX189BMJA -55°C to +125°C 8 CERDIP** ±1

* Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.

ERROR

(LSB)

1

⁄2

1

⁄2

1

⁄2

1

⁄2

1

⁄2

1

⁄2

1

⁄2

1

⁄2

____Pin Configurations (continued)

V

N.C.

AIN
N.C.
N.C.

SHDN

N.C.

REF

DD

1
2
3

MAX187

4

MAX189

5
6
7
8

Wide SO

SCLK

16

CS

15

N.C.

14

N.C.

13

DOUT

12

DGND

11

AGND

10

N.C.

9

18 ______________________________________________________________________________________

+5V, Low-Power, 12-Bit Serial ADCs

___________________Chip Topography

MAX187/MAX189

AIN

SHDN

V

DD

0.117"

(2.97mm)

REF

SCLK

AGND

CS

0.151"

(3.84mm)

DOUT

DGND

AGND

MAX187/MAX189

TRANSISTOR COUNT: 2278;
SUBSTRATE CONNECTED TO VDD.

______________________________________________________________________________________ 19

+5V, Low-Power, 12-Bit Serial ADCs

________________________________________________________________Package Information

INCHES MILLIMETERS

DIM

A2

A

A1

L

D

e

B

MAX187/MAX189

D1

D

A

e

B

A1

0.101mm

0.005in.

B1

A3

DUAL-IN-LINE

C

E

E1

0°-15°

eA
eB

P PACKAGE

PLASTIC

L

0°- 8°



A
A1
A2
A3

B
B1

C

C

D1

E
E1

e
eA
eB

L

DIM

PINS



D

D

D

DIM



A
A1

B

C

E

e

H

L

MAX

MIN

–

0.015

0.125

0.055

0.016

0.045

0.008

0.050

0.600

0.525

0.100

0.600
–

0.120

INCHES MILLIMETERS

MIN

24

1.230

28

1.430

40

2.025

INCHES MILLIMETERS

MIN

0.093

0.004

0.014

0.009

0.291



0.050

0.394

0.016

0.200
–

0.175

0.080

0.020

0.065

0.012

0.090

0.625

0.575
–
–

0.700

0.150

MAX

0.104

0.012

0.019

0.013

0.299



0.419

0.050

MAX

1.270

1.470

2.075

MIN

–

0.38

3.18

1.40

0.41

1.14

0.20

1.27

15.24

13.34

2.54

15.24
–

3.05

31.24

36.32

51.44

MIN

2.35

0.10

0.35

0.23

7.40

10.00

0.40

MIN



1.27

MAX

5.08
–

4.45

2.03

0.51

1.65

0.30

2.29

15.88

14.61
–
–

17.78

3.81

MAX

32.26

37.34

52.71

MAX

2.65

0.30

0.49

0.32

7.60


10.65

1.27

DIM

HE

W PACKAGE

SMALL

OUTLINE

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]



D
D
D
D
D

MIN

MAX

MIN

0.398

0.447

0.496

0.598

0.697

0.413

0.463

0.512

0.614

0.713

16
18
20
24
28

10.10

11.35

12.60

15.20

17.70

MAX

10.50

11.75

13.00

15.60

18.10

21-0042A

INCHES MILLIMETERS

PINS

© 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.