Datasheet MAX17019, MAX17019ATM+ Datasheet (Maxim)

General Description

The MAX17019 is a high-input-voltage quad-output controller (up to 38V). The MAX17019 provides a compact, low-cost controller capable of providing four independent regulators—a main stage, a 3A

P-P

internal step-

down, a 5A

P-P

internal step-down, and a 2A source/sink linear regulator. The input voltage is up to 38V. This makes it an excellent choice for automotive applications.

The internal switching regulators include 5V synchronous MOSFETs that can be powered directly from a single Li+ cell or from the main 3.3V/5V power stages. Finally, the linear regulator is capable of sourcing and sinking 2A to support DDR termination requirements or to generate a fixed output voltage.

The step-down converters use a peak current-mode, fixed-frequency control scheme—an easy to implement architecture that does not sacrifice fast-transient response. This architecture also supports peak currentlimit protection and pulse-skipping operation to maintain high efficiency under light-load conditions.

Separate enable inputs and independent open-drain power-good outputs allow flexible power sequencing. A soft-start function gradually ramps up the output voltage to reduce the inrush current. Disabled regulators enter high-impedance states to avoid negative output voltage created by rapidly discharging the output through the low-side MOSFET. The MAX17019 also includes output undervoltage, output overvoltage, and thermal-fault protection.

The MAX17019 is available in a 48-pin, 6mm x 6mm thin QFN package.

Applications

Automotive Battery-Powered Devices

Embedded Control Systems

Set-Top Boxes

Features

♦ Fixed-Frequency, Current-Mode Controllers ♦ 5.5V to 38V Input Range (Step-Down) ♦ 1x Step-Down Controller ♦ 1x Internal 5A

P-P

Step-Down Regulator

♦ 1x Internal 3A

P-P

Step-Down Regulator

♦ 1x 2A Source/Sink Linear Regulator with Dynamic

REFIN

♦ Internal BST Diodes ♦ Internal 5V 50mA Linear Regulator ♦ Fault Protection—Undervoltage, Overvoltage,

Thermal, Peak Current Limit

♦ Independent Enable Inputs and Power-Good

Outputs

♦ Voltage-Controlled Soft-Start ♦ High-Impedance Shutdown ♦ 10µA (typ) Shutdown Current

MAX17019

High-Input-Voltage Quad-Output Controller

________________________________________________________________

Maxim Integrated Products

MAX17019

36 35 34 33 32 31 30 29 28 27 26 25

CSPA

CSNA

AGND

REF

FREQ

UP/DN

INA

BYP

LDO5

INLDO

SHDN

ONB

SYNC

ONA

INBC

POKD

OND

ONC

FBC

POKC

BSTC

LXC

OUTD

IND

FBD

VTTR

REFIND

FBB

POKB

BSTB

LXB

DLA

BSTA

LXA

DHA

POKA

FBA

2 3 4 5 6 7 8 9 10 11 12

EXPOSED PAD = PGND

THIN QFN

TOP VIEW

Pin Configuration

19-4225; Rev 0; 8/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

Denotes a lead-free/RoHS-compliant package.

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX17019ATM+ -40°C to +125°C 48 TQFN-EP*

MAX17019

High-Input-Voltage Quad-Output Controller

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

INLDO, SHDN to GND............................................-0.3V to +43V

LDO5, INA, V

, VCCto GND..................................-0.3V to +6V

DHA to LXA .............................................-0.3V to (V

BSTA

+ 0.3V)

ONA, ONB, ONC, OND to GND ...............................-0.3V to +6V

POKA, POKB, POKC, POKD to GND.........-0.3V to (V

+ 0.3V) REF, REFIND, FREQ, UP/DN,

SYNC to GND ........................................-0.3V to (V

+ 0.3V)

FBA, FBB, FBC, FBD to GND.....................-0.3V to (V

+ 0.3V)

BYP to GND ............................................-0.3V to (V

LDO5

+ 0.3V)

CSPA, CSNA to GND .................................-0.3V to (V

+ 0.3V)

DLA to GND................................................-0.3V to (V

+ 0.3V)

INBC, IND to GND....................................................-0.3V to +6V

OUTD to GND............................................-0.3V to (V

IND

+ 0.3V)

VTTR to GND.............................................-0.3V to (V

BYP

+ 0.3V)

LXB, LXC to GND ....................................-1.0V to (V

INBC

+ 0.3V)

BSTB to GND ....................................(V

- 0.3V) to (V

LXB

+ 6V)

BSTC to GND....................................(V

- 0.3V) to (V

LXC

+ 6V)

BSTA to GND ....................................(V

- 0.3V) to (V

LXA

+ 6V)

REF Short-Circuit Current......................................................1mA

Continuous Power Dissipation (T

= +70°C)

Multilayer PCB: 48-Pin 6mm x 6mm

TQFN

(T4866-2 derated 37mW/°C above +70°C) ....................2.9W

Operating Temperature Range .........................-40°C to +105°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Voltage Range UP/DN = LDO5, INLDO, INA = LDO5 5.5 38 V

INA Undervoltage Threshold V

INA(UVLO)

UP/DN = LDO5, INA = VCC, rising edge, hysteresis = 160mV

4.0 4.2 4.4 V

INBC Input Voltage Range 2.3 5.5 V

SUPPLY CURRENTS

INLDO

Shutdown Supply Current I

IN(SHDN)VINLDO

= 5.5V to 38V, SHDN = GND 10 15 μA

INLDO

Suspend Supply Current I

IN(SUS)

INLDO

= 5.5V to 38V, ON_ = GND,

SHDN = INLDO

50 80 μA

VCC Shutdown Supply Current

SHDN = ONA = ONB = ONC = OND = GND, T

= +25°C

0.1 1 μA

VDD Shutdown Supply Current

SHDN = ONA = ONB = ONC = OND = GND, T

= +25°C

0.1 1 μA

INA Shutdown Current I

INA

SHDN = ONA = ONB = ONC = OND = GND, UP/DN = V

7 10 μA

VCC Supply Current Main Step-Down Only

ONA = V

, ONB = ONC = OND = GND; does not include switching losses, measured from V

210 300 μA

VCC Supply Current Main Step-Down and Reg ulator B

ONA = ONB = V

, ONC = OND = GND; does not include switching losses, measured from V

280 350 μA

VCC Supply Current Main Step-Down and Reg ulator C

ONA = ONC = V

, ONB = OND = GND; does not include switching losses, measured from V

280 350 μA

VCC Supply Current Main Step-Down and Reg ulator D

ONA = OND = V

, ONB = ONC = GND; does not include switching losses, measured from V

2.2 3 mA

INA Supply Current I

INA

ONA = VCC, UP/DN = VCC 40 60 μA

MAX17019

High-Input-Voltage Quad-Output Controller

_______________________________________________________________________________________ 3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

5V LINEAR REGULATOR (LDO5)

LDO5 Output Voltage V

LDO5

INLDO

= 5.5V to 38V, I

LDO5

= 0 to 50mA,

BYP = GND

4.75 5.0 5.2 V

LDO5 Short-Circuit Current Limit LDO5 = BYP = GND, V

INLDO

= 5.5V 70 160 250 mA

BYP Switchover Threshold V

BYP

Rising edge 4.65 V

LDO5-to-BYP Switch Resistance R

BYP

LDO5 to BYP, V

BYP

= 5V, I

LDO5

= 50mA 1.5 4 

1.25V REFERENCE

Reference Output Voltage V

REF

No load 1.237 1.25 1.263 V

Reference Load Regulation V

REF

= -1μA to +50μA 3 10 mV

Reference Undervoltage Lockout V

REF(UVLO)

1.0 V

OSCILLATOR

FREQ = VCC 500

FREQ = REF 750

kHz

Oscillator Frequency f

OSC

FREQ = GND 0.9 1.0 1.1 MHz

SWA

Regulator A 1/2 f

OSC

SWB

Regulator B f

OSC

Switching Frequency

SWC

Regulator C 1/2 f

OSC

MHz

Maximum Duty Cycle (All Switching Regulator s)

MAX

90 93.5 %

FREQ = VCC or GND 90

Minimum On-Time (All Switching Regulator s)

ON(MIN)

FREQ = REF 75

REGULATOR A (Main Step-Down)

Output Voltage-Adjust Range Step-down configuration (UP/DN = VCC) 1.0

0.3

FBA Regulation Voltage V

FBA

Step-down configuration (UP/DN = VCC), V

CSPA

- V

CSNA

= 0 to 20mV, 90% duty cycle

0.968 0.97 1.003 V

FBA Regulation Voltage (Overload)

FBA

Step-down configuration (UP/DN = VCC), V

CSPA

- V

CSNA

= 0 to 20mV, 90% duty cycle

0.930 1.003 V

FBA Load Regulation V

FBA

Step-down configuration (UP/DN = VCC), V

CSPA

- V

CSNA

= 0 to 20mV

16 mV

FBA Line Regulation

UP/DN = V

0 to 100% duty cycle

Step-down (UP/DN = V

)

10 16 22 mV

FBA Input Current I

FBA

UP/DN = GND or VCC, TA = +25°C -100 -5 +100 nA

Current-Sense Input CommonMode Range

CSA

0.3V

Current-Sense Input Bias Current I

CSA

TA = +25°C 40 60 μA

Idle Mode™ Threshold V

IDLEA

4 mV

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.) (Note 1)

Idle Mode is a trademark of Maxim Integrated Products, Inc.

MAX17019

High-Input-Voltage Quad-Output Controller

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Zero-Crossing Threshold V

IZX

1 mV

DHA Gate Driver On-Resistance R

DHA forced high and low 2.5 5 

DLA forced high 2.5 5

DLA Gate Driver On-Resistance R

DLA forced low 1.5 3



DHA Gate Driver Source/Sink Current

DHA forced to 2.5V 0.7 A

DL(SRC)

DLA forced to 2.5V 0.7

DLA Gate Driver Source/Sink Current

DL(SNK)

DLA forced to 2.5V 1.5

REGULATOR B (Internal 3A Step-Down Converter)

FBB Regulation Voltage I

LXB

= 0% duty cycle (Note 2) 0.747 0.755 0.762 V

FBB Regulation Voltage (Overload) V

FBB

LXB

= 0 to 2.5A, 0% duty cycle (Note 2) 0.720 0.762 V

FBB Load Regulation V

FBB

/I

LXB ILXB

= 0 to 2.5A -5 mV/A

FBB Line Regulation 0 to 100% duty cycle 7 8 10 mV

FBB Input Current I

FBB

TA = +25°C -100 -5 +100 nA

High-side n-channel 75 150

Internal MOSFET On-Resistance

Low-side n-channel 40 80

m

LXB Peak Current Limit I

PKB

3.0 3.45 4.0 A

LXB Idle-Mode Trip Level I

IDLEB

0.8 A

LXB Zero-Crossing Trip Level I

ZXB

100 mA

REGULATOR C (Internal 5A Step-Down Converter)

FBC Regulation Voltage I

LXC

= 0A, 0% duty cycle (Note 2) 0.747 0.755 0.762 V

FBC Regulation Voltage (Overload) V

FBC

LXC

= 0 to 4A, 0% duty cycle (Note 2) 0.710 0.762 V

FBC Load Regulation V

FBC

/I

LXC ILXC

= 0 to 4A -7 mV/A

FBC Line Regulation 0 to 100% duty cycle 12 14 16 mV

FBC Input Current I

FBC

TA = +25°C -100 -5 +100 nA

High-side n-channel 50 100

Internal MOSFET On-Resistance

Low-side n-channel 25 40

m

LXC Peak Current Limit I

PKC

5.0 5.75 6.5 A

LXC Idle-Mode Trip Level I

IDLEC

1.2 A

LXC Zero-Crossing Trip Level I

ZXC

100 mA

REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer)

IND Input Voltage Range V

IND

1 2.8 V

IND Supply Current OND = VCC 10 50 μA

IND Shutdown Current OND = GND, TA = +25°C 10 μA

REFIND Input Range 0.5 1.5 V

REFIND Input Bias Current V

REFIND

= 0 to 1.5V, TA = +25°C -100 +100 nA

OUTD Output Voltage Range V

OUTD

0.5 1.5 V

MAX17019

High-Input-Voltage Quad-Output Controller

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FBD

with respect to V

REFIND

, OUTD =

FBD, I

OUTD

= +50μA (source load)

-10 0

FBD Output Accuracy V

FBD

with respect to V

REFIND

OUTD = FBD, I

OUTD

= -50μA (sink load)

0 +10

FBD Load Regulation I

OUTD

= ±1A -17 -13 mV/A

FBD Line Regulation V

IND

= 1.0V to 2.8V, I

OUTD

= ±200mA 1 mV

FBD Input Current V

FBD

= 0 to 1.5V, TA = +25°C 0.1 0.5 μA

Source load +2 +4

OUTD Linear-Regulator Current Limit

Sink load -2 -4

Current-Limit Soft-Start Time With respect to internal OND signal 160 μs

High-side on-resistance 120 250

Internal MOSFET On-Resistance

Low-side on-resistance 180 450

m

VTTR

= ±0.5mA -10 +10

VTTR Output Accuracy REFIND to VTTR

VTTR

= ±3mA -20 +20

VTTR Maximum Current Rating ±5 mA

FAULT PROTECTION

Upper threshold rising edge, hysteresis = 50mV

9 12 14

SMPS POK and Fault Thresholds

Lower threshold falling edge, hysteresis = 50mV

-14 -12 -9

Upper threshold rising edge, hysteresis = 50mV

6 12 16

VTT LDO POKD and Fault Threshold

Lower threshold falling edge, hysteresis = 50mV

-16 -12 -6

POK Propagation Delay t

POK

FB_ forced 50mV beyond POK_ trip threshold

5 μs

Overvoltage Fault Latch Delay t

OVP

FB_ forced 50mV above POK_ upper trip threshold

5 μs

SMPS Undervoltage Fault Latch Delay

UVP

FBA, FBB, or FBC forced 50mV below POK_ lower trip threshold

5 μs

VTT LDO Undervoltage Fault Latch Delay

UVP

FBD forced 50mV below POKD lower trip threshold

5000 μs

POK Output Low Voltage V

POK

SINK

= 3mA 0.4 V

POK Leakage Currents I

POK

FBA

= 1.05V, V

FBB

= V

FBC

= 0.8V, V

FBD

REFIND

+ 50mV (POK high impedance);

POK_ forced to 5V, T

= +25°C

1 μA

Thermal-Shutdown Threshold T

SHDN

Hysteresis = 15°C +160 °C

MAX17019

High-Input-Voltage Quad-Output Controller

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL LOGIC LEVELS

SHDN Input Logic Threshold Hysteresis = 20mV 0.5 1.6 V

SHDN = 0~16V -2 +2

SHDN Input Bias Current TA = +25°C

SHDN = 17V~38V -2 +150

μA

ON_ Input Logic Threshold Hysteresis = 170mV 0.5 1.6 V

ON_ Input Bias Current TA = +25°C -1 +1 μA

UP/DN Input Logic Threshold 0.5 1.6 V UP/DN Input Bias Current TA = +25°C -1 +1 μA

High (VCC) VCC- 0.4V

Unconnected/REF 1.65 3.8

FREQ Input Voltage Levels

Low (GND) 0.5

FREQ Input Bias Current TA = +25°C -2 +2 μA

SYNC Input Logic Threshold 1.5 3.5 V

SYNC Input Bias Current TA = +25°C -1 +1 μA

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +125°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Voltage Range UP/DN = LDO5, INLDO, INA = LDO5 5.5 24 V

INA Undervoltage Threshold V

INA(UVLO)

UP/DN = LDO5, INA = VCC, ris ing edge, hysteresis = 160mV

3.9 4.5 V

INBC Input Voltage Range 2.3 5.5 V

SUPPLY CURRENTS

INLDO

Shutdown Supply Current I

IN(SHDN)VINLDO

= 5.5V to 38V, SHDN = GND 15 μA

INLDO

Suspend Supply Current I

IN(SUS)

INLDO

= 5.5V to 38V, ON_ = GND,

SHDN = INLDO

80 μA

INA Shutdown Current I

INA

SHDN = ONA = ONB = ONC = OND = GND, UP/DN = V

10 μA

VCC Supply C urrent Main Step-Down Only

ONA = V

, ONB = ONC = OND = GND; does not include switching losses, measured from V

350 μA

VCC Supply Current Main Step-Down and Regulator B

ONA = ONB = V

, ONC = OND = GND; does not include switching losses, measured from V

400 μA

VCC Supply Current Main Step-Down and Regulator C

ONA = ONC = V

, ONB = OND = GND, does not include switching losses, measured from V

400 μA

MAX17019

High-Input-Voltage Quad-Output Controller

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +125°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC Supply Current Main Step-Down and Reg ulator D

ONA = OND = V

, ONB = ONC = GND, does not include switching losses, measured from V

3.5 mA

INA Supply Current (Step-Down) I

INA

ONA = VCC, UP/DN = VCC(step-down) 75 μA

5V LINEAR REGULATOR

LDO5 Output Voltage V

LDO5

INLDO

= 5.5V to 38V, I

LDO5

= 0 to 50mA,

BYP = GND

4.75 5.25 V

LDO5 Short-Circuit Current Limit LDO5 = BYP = GND, V

INLDO

= 5.5V 55 mA

1.25V REFERENCE

Reference Output Voltage V

REF

No load 1.237 1.263 V

Reference Load Regulation V

REF

= -1μA to +50μA 12 mV

OSCILLATOR

Oscillator Frequency f

OSC

FREQ = GND 0.9 1.1 MHz

Maximum Duty Cycle (All Switching Regulator s)

MAX

89 %

REGULATOR A (Main Step-Down)

Output Voltage Adjust Range Step-down configuration (UP/DN = VCC) 1.0

0.3V

FBA Regulation Voltage

Step-down configuration, V

CSPA

- V

CSNA

= 0mV, 90% duty cycle

0.963 1.008 V

FBA Regulation Voltage (Overload)

FBA

Step-down configuration (UP/DN = VCC), V

CSPA

- V

CSNA

= 0 to 20mV, 90% duty cycle

0.925 1.008 V

FBA Line Regulation Step-down (UP/DN = VCC) 10 33 mV

Current-Sense Input CommonMode Range

CSA

0.3V

Current-Limit Threshold (Positive) V

ILIMA

17 23 mV

REGULATOR B (Internal 3A Step-Down Converter)

FBB Regulation Voltage I

LXB

= 0A, 0% duty cycle (Note 2) 0.742 0.766 V

FBB Regulation Voltage (Overload) V

FBB

LXB

= 0 to 2.5A , 0% duty cycle (Note 2) 0.715 0.766 V

FBB Line Regulation 6 12 mV

LXB Peak Current Limit I

PKB

2.7 4.2 A

REGULATOR C (Internal 5A Step-Down Converter)

FBC Regulation Voltage I

LXC

= 0A, 0% duty cycle (Note 2) 0.742 0.766 V

FBC Regulation Voltage (Overload) V

FBC

LXC

= 0 to 4A, 0% duty cycle (Note 2) 0.705 0.766 V

FBC Line Regulation 11 20 mV

LXC Peak Current Limit I

PKC

5.0 6.5 A

MAX17019

High-Input-Voltage Quad-Output Controller

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

INLDO

= 12V, V

INA

= V

INBC

= VDD= VCC= V

BYP

= V

CSPA

= V

CSNA

= 5V, V

IND

= 1.8V, V

SHDN

= V

ONA

= V

ONB

ONC

= V

OND

= 5V, I

REF

= I

LDO5

= I

OUTD

= no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +125°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer)

IND Input Voltage Range V

IND

1 2.8 V

IND Supply Current OND = VCC 70 μA

REFIND Input Range 0.5 1.5 V

OUTD Output Voltage Range V

OUTD

0.5 1.5 V

FBD

with respect to V

REFIND

OUTD = FBD, I

OUTD

= +50μA (source load)

-12 0

FBD Output Accuracy V

FBD

with respect to V

REFIND

OUTD = FBD, I

OUTD

= -50μA (sink load)

0 +12

FBD Load Regulation I

OUTD

= ±1A -20 mV/A

Source load +2 +4

OUTD Linear-Regulator Current Limit

Sink load -2 -4

High-side on-resistance 300

Internal MOSFET On-Resistance

Low-side on-resistance 475

m

VTTR Output Accuracy REFIND to VTTR, I

VTTR

= ±3mA -20 +20 mV

FAULT PROTECTION

Upper threshold rising edge, hysteresis = 50mV

8 16

SMPS POK and Fault Thresholds

Lower threshold falling edge, hysteresis = 50mV

-16 -8

Upper threshold rising edge, hysteresis = 50mV

6 16

VTT LDO POKD and Fault Threshold

Lower threshold falling edge, hysteresis = 50mV

-16 -6

POK Output Low Voltage V

POK ISINK

= 3mA 0.4 V

GENERAL LOGIC LEVELS SHDN Input Logic Threshold Hysteresis = 20mV 0.5 1.6 V

ON_ Input Logic Threshold Hysteresis = 170mV 0.5 1.6 V UP/DN Input Logic Threshold 0.5 1.6 V

High (VCC) VCC- 0.4V

Unconnected/REF 1.65 3.8

FREQ Input Voltage Levels

Low (GND) 0.5

SYNC Input Logic Threshold 1.5 3.5 V

Note 1: Limits are 100% production tested at TA= +25°C. Maximum and minimum limits are guaranteed by design and

characterization.

Note 2: Regulation voltage tested with slope compensation. Typical value is equivalent to 0% duty cycle. In real applications, the

regulation voltage is higher due to the line regulation times the duty cycle.

MAX17019

High-Input-Voltage Quad-Output Controller

_______________________________________________________________________________________

SMPS REGULATOR A EFFICIENCY

vs. LOAD CURRENT

MAX17019 toc01

LOAD CURRENT (A)

EFFICIENCY (%)

10.10.01

100

0.001 10

VIN = 20V

VIN = 12V

VIN = 8V

SMPS REGULATOR A OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX17019 toc02

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

4.54.03.53.02.52.01.51.00.5

4.80

4.85

4.90

4.95

5.00

5.05

4.75

05.0

= 20V

VIN = 12V

VIN = 8V

SMPS REGULATOR B EFFICIENCY

vs. LOAD CURRENT

MAX17019 toc03

LOAD CURRENT (A)

EFFICIENCY (%)

10.10.01

100

0.001 10

VIN = 3.3V

VIN = 5V

VIN = 2.5V

SMPS REGULATOR B OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX17019 toc04

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

1.5 2.0 2.51.00.5

1.77

1.82

1.72

03.0

VIN = 3.3V

VIN = 5V

VIN = 2.5V

SMPS REGULATOR C EFFICIENCY

vs. LOAD CURRENT

MAX17019 toc05

LOAD CURRENT (A)

EFFICIENCY (%)

10.10.01

0.001 10

VIN = 3.3V

VIN = 5V

VIN = 2.5V

SMPS REGULATOR C OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX17019 toc06

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

4.54.03.53.02.52.01.51.00.5

0.99

1.00

1.01

1.02

1.03

1.04

1.05

0.98

05.0

VIN = 3.3V

VIN = 5V

VIN = 2.5V

REGULATOR D VOLTAGE

vs. SOURCE/SINK LOAD CURRENT

MAX17019 toc07

LOAD CURRENT (A)

VOLTAGE (V)

1.51.00 0.5-1.0 -0.5-1.5

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.880

-2.0 2.0

Typical Operating Characteristics

(TA = +25°C, Circuit of Figure 1, unless otherwise noted.)

MAX17019

High-Input-Voltage Quad-Output Controller

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(TA = +25°C, Circuit of Figure 1, unless otherwise noted.)

REG B STARTUP WAVEFORM

(HEAVY LOAD)

MAX17019 toc10

400μs/div

ONB

OUTB

POKB

LXB

ONB: 5V/div OUTB: 2V/div POKB: 5V/div I

: 2A/div

LXB: 5V/div

LOAD

= 1.01Ω

REG B SHUTDOWN WAVEFORM

MAX17019 toc11

400μs/div

ONB

OUTB

POKB

LXB

ONB: 5V/div OUTB: 2V/div POKB: 5V/div I

: 2A/div

LXB: 5V/div

LOAD

= 0.8Ω

REG C STARTUP WAVEFORM

(HEAVY LOAD)

MAX17019 toc12

400μs/div

ONC

OUTC

POKC

LXC

ONC: 5V/div OUTC: 1V/div POKC: 5V/div I

: 5A/div

LXC: 5V/div

LOAD

= 0.25Ω

REG C SHUTDOWN

MAX17019 toc13

100μs/div

ONC

OUTC

POKC

LXC

ONC: 5V/div OUTC: 1V/div POKC: 5V/div I

: 5A/div

LXC: 5V/div

LOAD

= 0.25Ω

REG A STARTUP WAVEFORM

(HEAVY LOAD)

MAX17019 toc08

400μs/div

ONA

OUTA

POKA

LXA

ONA: 5V/div OUTA: 5V/div POKA: 5V/div I

: 5A/div

LXA: 10V/div

LOAD

= 1.6Ω

REG A SHUTDOWN WAVEFORM

MAX17019 toc09

400μs/div

ONA

OUTA

POKA

LXA

ONA: 5V/div OUTA: 5V/div POKA: 5V/div I

: 5A/div

LXA: 10V/div

LOAD

= 2.5Ω

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________

REG A LOAD TRANSIENT (1A TO 3.2A)

MAX17019 toc14

20μs/div

OUTA

LXA

OUTA: 100mV/div LXA: 10V/div I

: 2A/div

OUTA

: 2A/div

INA

= 12V, LOAD TRANSIENT

IS FROM 1A TO 3.2A

REG B LOAD TRANSIENT (0.4A TO 2A)

MAX17019 toc15

20μs/div

OUTB

LXB

OUTB: 50mV/div LXB: 5V/div I

: 1A/div

OUTB

: 2A/div

INBC

= 5V, 0.4A TO 2.0A

LOAD TRANSIENT

REG C LOAD TRANSIENT (0.8A TO 3A)

MAX17019 toc16

20μs/div

OUTC

LXC

OUTC: 50mV/div LXC: 5V/div I

: 2A/div

OUTC

: 2A/div

INBC

= 5V, 0.8A TO 3.0A

LOAD TRANSIENT

REG D LOAD TRANSIENT (SOURCE/SINK)

MAX17019 toc17

20μs/div

OUTD

OUTD: 20mV/div I

OUTD

: 1A/div

IND

= 1.8V, V

REFIND

= 0.9V,

OUT

= 2 x 10μF, LOAD TRANSIENT

IS FROM 1A SOURCING TO 1A SINKING

REG D LOAD TRANSIENT (SINK)

MAX17019 toc18

20μs/div

OUTD

OUTD: 10mV/div I

OUTD

: 1A/div

IND

= 1.8V, V

REFIND

= 0.9V,

OUT

= 2 x 10μF, LOAD TRANSIENT

IS FROM 0 TO 1A SINKING

Typical Operating Characteristics (continued)

(TA = +25°C, Circuit of Figure 1, unless otherwise noted.)

REG D LOAD TRANSIENT (SOURCE)

MAX17019 toc19

20μs/div

OUTD

OUTD: 10mV/div I

OUTD

: 1A/div

IND

= 1.8V, V

REFIND

= 0.9V,

OUT

= 2 x 10μF, LOAD TRANSIENT

IS FROM 0 TO 1A SOURCING

MAX17019

High-Input-Voltage Quad-Output Controller

12 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 POKC

Open-Drain Power-Good Output for the Internal 5A Step-Down Converter. POKC is low if FBC is more than 12% (typ) above or below the nominal 0.75V feedback regulation threshold. POKC is held low during startup and in shutdown. POKC becomes high impedance when FBC is in regulation.

2 BSTC

Boost Flying Capacitor Connection for the Internal 5A Step-Down Converter. The MAX17019 includes an internal boost switch/diode connected between VDD and BSTC. Connect to an external capacitor as shown in Figure 1.

3–6 LXC

Inductor Connection for the Internal 5A Step-Down Converter. Connect LXC to the switched side of the inductor.

7, 8 OUTD

Source/Sink Linear-Regulator Output. Bypass OUTD with 2x 10μF or greater ceramic capacitors to ground. Dropout needs additional output capacitance (see the VTT LDO Output Capacitor Selection (C

OUTD

)

section).

9 IND Source/Sink Linear-Regulator Input. Bypass IND with a 10μF or greater ceramic capacitor to ground.

10 FBD

Feedback Input for the Internal Source/Sink Linear Regulator. FBD tracks and regulates to the REFIND voltage.

11 VTTR Ouput of Reference Buffer. Bypass with 0.22μF for ±3mA of output current.

12 REFIND

Dynamic Reference Input Voltage for the Source/Sink Linear Regulator and the Reference Buffer. The linear-regulator feedback threshold (FBD) tracks the REFIND voltage.

13 SHDN

Shutdown Control Input. The device enters its 5μA supply current shutdown mode if V

SHDN

is less than

the SHDN input falling-edge trip level and does not restart until V

SHDN

is greater than the SHDN input

rising-edge trip level. Connect SHDN to V

INLDO

for automatic startup of LDO5.

14 INLDO

Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to GND with a 0.1μF or greater ceramic capacitor close to the controller. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Connect BYP and INLDO to the system’s 5V supply to effectively disable the linear regulator.

15 LDO5

5V Internal Linear-Regulator Output. Bypass with 4.7μF or greater ceramic capacitor. The 5V linear regulator provides the bias power for the gate drivers (V

) and analog control circuitry (VCC). The linear regulator sources up to 50mA (max guaranteed). When BYP exceeds 4.65V (typ), the MAX17019 bypasses the linear regulator through a 1.5 bypass switch. When the linear regulator is bypassed, LDO5 supports loads up to 100mA. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Bypass SHDN to ground and leave LDO5 unconnected. Connect BYP and INLDO to effectively disable the linear regulator.

16 BYP

Linear-Regulator Bypass Input. When BYP exceeds 4.65V, the controller shorts LDO5 to BYP through a

1.5 bypass switch and disables the linear regulator. When BYP is low, the linear regulator remains active. The BYP input also serves as the VTTR buffer supply, allowing VTTR to remain active even when the source/sink linear regulator (OUTD) has been disabled under system standby/suspend conditions. In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply. Bypass LDO5 to ground with a 1μF capacitor and leave this output unconnected. Connect BYP and INLDO to the system’s 5V supply to effectively disable the linear regulator.

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________ 13

Pin Description (continued)

PIN NAME FUNCTION

17 V

5V Analog Bias Supply. VCC powers all the analog control blocks (error amplifiers, current-sense amp lifiers, fault comparators, etc.) and control logic. Connect V

to the 5V system supply with a series 10 resistor,

and bypass to analog ground using a 1μF or greater ceramic capacitor.

18 INA Input to the Circuit in Reg A in Boost Mode. Connect INA to LDO5 in step-down mode (UP/DN = VCC).

19 UP/DN

Converter Configuration Selection Input for Regulator A. When UP/DN is pulled high (UP/DN = V

), regulator A

operates as a step-down converter (Figure 1). When UP/DN is pulled low (UP/DN = GND), regulator A operates as a low-voltage step-up converter. (Refer to the MAX17017 data sheet for step-up configuration.)

20 FREQ

Trilevel Oscillator Frequency Selection Input: FREQ = V

: RegA = 250kHz, RegB = 500kHz, RegC = 250kHz FREQ = REF: RegA = 375kHz, RegB = 750kHz, RegC = 375kHz FREQ = GND: RegA = 500kHz, RegB = 1MHz, RegC = 500kHz

21 REF

1.25V Reference-Voltage Output. Bypass REF to analog ground with a 0.1μF ceramic capacitor. The reference sources up to 50μA for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference shuts down when the system pulls SHDN low in buck mode (UP/DN = GND).

22 AGND Analog Ground

23 CSNA

Negative Current-Sense Input for the Main Switching Regulator. Connect to the negative terminal of the currentsense resistor. Due to the CSNA bias current requirements, limit the series impedance to less than 10.

24 CSPA

Positive Current-Sense Input for the Main Switching Regulator. Connect to the positive terminal of the currentsense resistor. Due to the CSPA bias current requirements, limit the series impedance to less than 10.

25 FBA Feedback Input for the Main Switching Regulator. FBA regulates to 1.0V.

26 POKA

Open-Drain Power-Good Output for the Main Switching Regulator. POKA is low if FBA is more than 12% (typ) above or below the nominal 1.0V feedback regulation point. POKA is held low during soft-start and in shutdown. POKA becomes high impedance when FBA is in regulation.

27 DHA High-Side Gate-Driver Output for the Main Switching Regulator. DHA swings from LXA to BSTA.

28 LXA Inductor Connection of Converter A. Connect LXA to the switched side of the inductor.

29 BSTA

Boost Flying Capacitor Connection of Converter A. The MAX17019 needs an external boost switch/diode connected between V

and BSTA. Connect to an external capacitor as shown in Figure 1.

30 DLA Low-Side Gate-Driver Output for the Main Switching Regulator. DLA swings from GND to VDD.

31, 32,

LXB

Inductor Connection for the Internal 3A Step-Down Converter. Connect LXB to the switched side of the inductor.

34 BSTB

Boost Flying Capacitor Connection for the Internal 3A Step-Down Converter. The MAX17019 includes an internal boost switch/diode connected between VDD and BSTB. Connect to an external capacitor as shown in Figure 1.

35 POKB

Open-Drain Power-Good Output for the Internal 3A Step-Down Converter. POKB is low if FBB is more than 12% (typ) above or below the nominal 0.75V feedback-regulation threshold. POKB is held low during softstart and in shutdown. POKB becomes high impedance when FBB is in regulation.

MAX17019

High-Input-Voltage Quad-Output Controller

14 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

36 FBB Feedback Input for the Internal 3A Step-Down Converter. FBB regulates to 0.75V.

37 ONB

Switching Regulator B Enable Input. When ONB is pulled low, LXB is high impedance. When ONB is driven high, the controller enables the 3A internal switching regulator.

38 SYNC External Synchronization Input. Used to override the internal switching frequency.

39 ONA

Switching Regulator A Enable Input. When ONA is pulled low, DLA and DHA are pulled low. When ONA is driven high, the controller enables the step-up/step-down converter.

40–43 INBC

Input for Regulators B and C. Power INBC from a 2.5V to 5.5V supply. Internally connected to the drain of the high-side MOSFETs for both regulator B and regulator C. Bypass to PGND with 2x 10μF or greater ceramic capacitors to support the RMS current.

44 V

5V Bias Supply Input for the Internal Switching Regulator Drivers. Bypass with a 1μF or greater ceramic capacitor. Provides power for the BSTB and BSTC driver supplies.

45 POKD

Open-Drain Power-Good Output for the Internal Source/Sink Linear Regulator. POKD is low if FBD is more than 10% (typ) above or below the REFIND regulation threshold. POKD is held low during soft-start and in shutdown. POKD becomes high impedance when FBD is in regulation.

46 OND

Source/Sink Linear Regulator (Regulator D) and Reference Buffer Enable Input. When OND is pulled low, OUTD is high impedance. When OND is driven high, the controller enables the source/sink linear regulator.

47 ONC

Switching Regulator C Enable Input. When ONC is pulled low, LXC is high impedance. When ONC is driven high, the controller enables the 5A internal switching regulator.

48 FBC Feedback Input for the Internal 5A Step-Down Converter. FBC regulates to 0.75V.

EP PGND

Power Ground. The source of the low-side MOSFETs (REG B and REG C), the drivers for all switching regulators, and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad. Connect the exposed backside pad to system power ground planes through multiple vias.

Detailed Description

The MAX17019 standard application circuit (Figure 1) provides a 5V/5A

P-P

main stage, a 1.8V/3A

P-P

VDDQ

and 0.9A/2A VTT outputs for DDR, and a 1.05V/5A

P-P

chipset supply.

The MAX17019 supports four power outputs—one highvoltage step-down controller, two internal MOSFET step-down switching regulators, and one high-current source/sink linear regulator. The step-down switching regulators use a current-mode fixed-frequency architecture compensated by the output capacitance. An internal 50mA 5V linear regulator provides the bias supply and driver supplies, allowing the controller to power up from input supplies greater than 5.5V.

Fixed 5V Linear Regulator (LDO5)

An internal linear regulator produces a preset 5V lowcurrent output from INLDO. LDO5 powers the gate drivers for the external MOSFETs, and provides the bias

supply required for the SMPS analog controller, reference, and logic blocks. LDO5 supplies at least 50mA for external and internal loads, including the MOSFET gate drive, which typically varies from 5mA to 15mA per switching regulator, depending on the switching frequency. Bypass LDO5 with a 4.7μF or greater ceramic capacitor to guarantee stability under the fullload conditions.

The MAX17019 switch-mode step-down switching regulators require a 5V bias supply in addition to the mainpower input supply. This 5V bias supply is generated by the controller’s internal 5V linear regulator (LDO5). This boot-strappable LDO allows the controller to power up independently. The gate driver V

input supply is typically connected to the fixed 5V linear regulator output (LDO5). Therefore, the 5V LDO supply must provide LDO5 (PWM controller) and the gatedrive power during power-up.

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________ 15

MAX17019

PWR

4.7μF, 6V

0603

AGND

1.0μF, 6V

0402

LDO5

INA

SHDN

UP/DN

ONA

ONB

ONC

10Ω

5%, 0402

R9–R12

(4x) 100kΩ

5%, 0402

5V SMPS

OUTPUT

AGND

C16

0.1μF, 6V

0402

REF

AGND

OND

POKA

POKB

POKC

POKD

VTTR

1.8V SMPS OUTPUT

ON OFF

40.2kΩ

1%, 0402

14.0kΩ

1%, 0402

R14

15.0kΩ

1%, 0402

0Ω

1%, 0402

AGND

R15

0Ω

5%, 0402

10.0kΩ

1%, 0402

R4 4mΩ

5%, 1206

FREQ

R13

15kΩ

1%, 0402

REFIND

AGND

SYNC

0.22μF, 4V

0402

AGND

C13

680pF, 50V

0402

0.1μF, 6V 0402

0.1μF

PWR

LDO5

C17, C18 (2x) 1μF, 50V 0603

GND

INLDO

BSTA

DHA

PWR

C19, C20 (2x) 4.7μF, 50V 1206

PWR

C7 1μF, 16V 0402

PWR

C9 10μF, 6V 0805

PWR

C21 22μF, 50V

PWR

C22 150μF 35mΩ, 6V, B2 CASE

PWR

C23 330μF 15mΩ, 2.5V, B2 CASE

5.5V TO 38V

DLA

CSPA

LXA

3.3μH, 6A, 30mΩ

BSTB

LXB

1μH, 7A, 14mΩ

FBD

CSNA

FBA

BYP

AGND

10.0kΩ

1%, 0402

AGND

C14

1000pF, 50V

0402

FBB

INBC

PWR

C8 1μF, 6V 0402

PWR

C10 10μF, 6V 0805

IND

OUTD

2.0A

1.8V

2.5A

4.02kΩ

1%, 0402

0.1μF, 6V 0402

PWR

C24 330μF 15mΩ, 2.5V, B2 CASE

BSTC

LXC

1μH, 7A, 14mΩ

AGND

10.0kΩ

1%, 0402

R16

1Ω 5%

AGND

C15

2200pF, 50V

0402

FBC

1.05V

4.0A

0.9V ±1A

PWR

C11, C12 (2x) 10μF, 6V 0805

Figure 1. Standard Application Circuit

MAX17019

High-Input-Voltage Quad-Output Controller

16 ______________________________________________________________________________________

MAX17019

SHDN

REFOK

INLDO

LDO5

TSDN

DRV

UVLO

CSB

BIAS

BYP

BYP_OK

_OK

UP/DN

UP/DN = V

[BUCK],

LOW BUCK MODE

REF_OK ONLDO

REF

PGOOD AND

FAULT

PROTECTION

OSC

REG A

ANALOG

REG D

ANALOG

TSDN

REF

SYNC

*ONA (SHDN)

IND

PGND

REG D PWR

OUTD

OND

FBD

REFIND

ON_VTTR

VTTR

BYP

ONA

*BUCK REF ENABLED BY SHDN; BOOST REF ENABLED BY ONA.

+SSDA ONLY USED IN STEP-UP MODE. SSDA = HIGH IN STEP-DOWN MODE.

ONB ONC OND

POKX

FAULTX

ONX

UVLO

INBC_OK

INA

BSTA

DHA

DLA

CSPA

CSNA ONA

FBA

REG B

ANALOG

FBB

SSDA+

LXA

BSTB

LXB

INBC

CSC

REG C

ANALOG

FBC

BSTC

LXC

INBC

ONB

INBC_OK

ONC

INBC_OK

Figure 2. MAX17019 Block Diagram

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________ 17

LDO5 Bootstrap Switchover

When the bypass input (BYP) exceeds the LDO5 bootstrap-switchover threshold for more than 500μs, an internal 1.5Ω (typ) p-channel MOSFET shorts BYP to LDO5, while simultaneously disabling the LDO5 linear regulator. This bootstraps the controller, allowing power for the internal circuitry and external LDO5 loading to be generated by the output of a 5V switching regulator. Bootstrapping reduces power dissipation due to driver and quiescent losses by providing power from a switch-mode source, rather than from a much-less-efficient linear regulator. The current capability increases from 50mA to 100mA when the LDO5 output is switched over to BYP. When BYP drops below the bootstrap threshold, the controller immediately disables the bootstrap switch and reenables the 5V LDO.

Reference (REF)

The 1.25V reference is accurate to ±1% over temperature and load, making REF useful as a precision system reference. Bypass REF to GND with a 0.1μF or greater ceramic capacitor. The reference sources up to 50μA and sinks 5μA to support external loads. If highly accurate specifications are required for the main SMPS output voltages, the reference should not be loaded. Loading the reference slightly reduces the output voltage accuracy because of the reference load-regulation error.

SMPS Detailed Description

Fixed-Frequency, Current-Mode

PWM Controller

The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums multiple signals: the output voltage-error signal with respect to the reference voltage, the current-sense signal, and the slope compensation ramp (Figure 3). The MAX17019 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it.

Frequency Selection (FREQ)

The FREQ input selects the PWM mode switching frequency. Table 1 shows the switching frequency based on the FREQ connection. High-frequency (FREQ = GND) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be acceptable in ultraportable devices where the load currents are lower. Low-frequency (FREQ = 5V) operation offers the best overall efficiency at the expense of component size and board space.

FB_

REF

CSH_

CSL_

SLOPE COMPENSATION

R1 R2

TO PWM LOGIC

OUTPUT DRIVER

UNCOMPENSATED HIGH-SPEED LEVEL TRANSLATOR AND BUFFER

I2 I3 V

BIAS

Figure 3. PWM Comparator Functional Diagram

MAX17019

High-Input-Voltage Quad-Output Controller

18 ______________________________________________________________________________________

Light-Load Operation Control

The MAX17019 uses a light-load pulse-skipping operating mode for all switching regulators. The switching regulators turn off the low-side MOSFETs when the current sense detects zero inductor current. This keeps the inductor from discharging the output capacitors and forces the switching regulator to skip pulses under light-load conditions to avoid overcharging the output.

Idle-Mode Current-Sense Threshold

When pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode currentsense threshold. Under light-load conditions, the ontime duration depends solely on the idle-mode current-sense threshold. This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Since the zero-crossing comparator prevents the switching regulator from sinking current, the MAX17019 switching regulators must skip pulses. Therefore, the controller regulates the valley of the output ripple under light-load conditions.

Automatic Pulse-Skipping Crossover

In skip mode, an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing

comparator senses the inductor current during the offtime. For regulator A, once V

CSPA

- V

CSNA

drops below the 1mV zero-crossing current-sense threshold, the comparator turns off the low-side MOSFET (DLA pulled low). For regulators B and C, once the current through the lowside MOSFET drops below 100mA, the zero-crossing comparator turns off the low-side MOSFET.

The minimum idle-mode current requirement causes the threshold between pulse-skipping PFM operation and constant PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs (I

LOAD(SKIP)

) is equivalent

to half the idle-mode current threshold (see the

Electrical Characteristics

table for the idle-mode thresholds of each regulator). The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).

Table 1. FREQ Table

REG A AND REG C REG B

SWITCHING

FREQUENCY

SOFT-START TIME

STARTUP

BLANKING

TIME

SWITCHING

FREQUENCY

SOFT-START

TIME

STARTUP

BLANKING

TIME

SELECT

SWA

AND f

SWC

REG A: 1200/f

SWA

REG C: 900/f

SWC

1500/f

SWA

SWB

1800/f

SWB

3000/f

SWB

LDO5 250kHz

REG A: 4.8ms REG C: 3.6ms

6ms 500kHz 3.6ms 6ms

REF 375kHz

REG A: 3.2ms REG C: 2.4ms

4ms 750kHz 2.4ms 4ms

GND 500 kH z

REG A: 2.4ms REG C: 1.8ms

3ms 1MHz 1.8ms 3ms

SYNC 0.5 x f

SYNC

— — f

SYNC

— —

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________ 19

SMPS POR, UVLO, and Soft-Start

Power-on reset (POR) occurs when VCCrises above approximately 1.9V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. The POR circuit also ensures that the low-side drivers are pulled low until the SMPS controllers are activated. The V

input undervoltage lockout (UVLO) circuitry prevents the switching regulators from operating if the 5V bias supply (VCCand VDD) is below its 4.2V UVLO threshold.

Regulator A Startup

Once the 5V bias supply rises above this input UVLO threshold and ONA is pulled high, the main step-down controller (regulator A) is enabled and begins switching. The internal voltage soft-start gradually increments the feedback voltage by 10mV every 12 switching cycles. Therefore, OUTA reaches its nominal regulation voltage 1200/f

SWA

after regulator A is enabled (see the

REG A Startup Waveform (Heavy Load) graph in the

Typical Operating Characteristics

Regulator B and C Startup

The internal step-down controllers start switching and the output voltages ramp up using soft-start. If the bias supply voltage drops below the UVLO threshold, the controller stops switching and disables the drivers (LX_ becomes high impedance) until the bias supply voltage recovers.

Once the 5V bias supply and INBC rise above their respective input UVLO thresholds (SHDN must be pulled high to enable the reference), and ONB or ONC is pulled high, the respective internal step-down controller (regulator B or C) becomes enabled and begins switching. The internal voltage soft-start gradually increments the feedback voltage by 10mV every 24 switching cycles for regulator B or every 12 switching cycles for regulator C. Therefore, OUTB reaches its nominal regulation voltage 1800/f

SWB

after regulator B is enabled, and OUTC reaches its nominal regulation voltage 900/f

SWC

after regulator C is enabled (see the REG B Startup Waveform (Heavy Load) and REG C Startup Waveform (Heavy Load) graphs in the

Typical

Operating Characteristics

SMPS Power-Good Outputs (POK)

POKA, POKB, and POKC are the open-drain outputs of window comparators that continuously monitor each output for undervoltage and overvoltage conditions. POK_ is actively held low in shutdown (SHDN = GND), standby (ONA = ONB = ONC = GND), and soft-start.

Once the soft-start sequence terminates, POK_ becomes high impedance as long as the output remains within ±8% (min) of the nominal regulation voltage set by FB_. POK_ goes low once its corresponding output drops 12% (typ) below its nominal regulation point, an output overvoltage fault occurs, or the output is shut down. For a logic-level POK_ output voltage, connect an external pullup resistor between POK_ and LDO5. A 100kΩ pullup resistor works well in most applications.

SMPS Fault Protection

Output Overvoltage Protection (OVP)

If the output voltage rises above 112% (typ) of its nominal regulation voltage, the controller sets the fault latch, pulls POK_ low, shuts down the respective regulator, and immediately pulls the output to ground through its low-side MOSFET. Turning on the low-side MOSFET with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. However, this commonly undamped response causes negative output voltages due to the energy stored in the output LC at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse-polarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the input source also fails (short-circuit fault). Cycle VCCbelow 1V or toggle the respective enable input to clear the fault latch and restart the regulator.

Output Undervoltage Protection (UVP)

Each MAX17019 includes an output UVP circuit that begins to monitor the output once the startup blanking period has ended. If any output voltage drops below 88% (typ) of its nominal regulation voltage, the UVP protection immediately sets the fault latch, pulls the respective POK output low, forces the high-side and low-side MOSFETs into high-impedance states (DH = DL = low), and shuts down the respective regulator. Cycle VCCbelow 1V or toggle the respective enable input to clear the fault latch and restart the regulator.

Thermal-Fault Protection

The MAX17019 features a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch, pulls all POK outputs low, and shuts down all regulators. Toggle SHDN to clear the fault latch and restart the controllers after the junction temperature cools by 15°C.

MAX17019

High-Input-Voltage Quad-Output Controller

20 ______________________________________________________________________________________

VTT LDO Detailed Description

VTT LDO Power-Good Output (POKD)

POKD is the open-drain output of a window comparator that continuously monitors the VTT LDO output for undervoltage and overvoltage conditions. POKD is actively held low when the VTT LDO is disabled (OND = GND) and in soft-start. Once the startup blanking time expires, POKD becomes high impedance as long as the output remains within ±6% (min) of the nominal regulation voltage set by REFIND. POKD goes low once its corresponding output drops or rises 12% (typ) beyond its nominal regulation point or the output is shut down. For a logic-level POKD output voltage, connect an external pullup resistor between POKD and LDO5. A 100kΩ pullup resistor works well in most applications.

VTT LDO Fault Protection

LDO Output OVP

If the output voltage rises above 112% (typ) of its nominal regulation voltage, the controller sets the fault latch, pulls POKD low, shuts down the source/sink linear regulator, and immediately pulls the output to ground through its low-side MOSFET. Turning on the low-side MOSFET with 100% duty cycle rapidly discharges the output capacitors and clamps the output to ground. Cycle VCCbelow 1V or toggle OND to clear the fault latch and restart the linear regulator.

LDO Output UVP

Each MAX17019 includes an output UVP circuit that begins to monitor the output once the startup blanking period has ended. If the source/sink LDO output voltage drops below 88% (typ) of its nominal REFIND regulation voltage for 5ms, the UVP sets the fault latch, pulls the POKD output low, forces the output into a highimpedance state, and shuts down the linear regulator. Cycle VCCbelow 1V or toggle OND to clear the fault latch and restart the regulator.

SMPS Design Procedure

(Step-Down Regulators)

Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:

• Input voltage range. The maximum value (V

IN(MAX)

) must accommodate the worst-case, high ACadapter voltage. The minimum value (V

IN(MIN)

) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency.

• Maximum load current. There are two values to con- sider. The peak load current (I

LOAD(MAX)

) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (I

LOAD

) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components.

• Switching frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and V

• Inductor operating point. This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency, higher output ripple, and lower maximum load current due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (light loads), the inductor value also determines the loadcurrent value at which PFM/PWM switchover occurs.

Step-Down Inductor Selection

The switching frequency and inductor operating point determine the inductor value as follows:

Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Most

VVV

Vf I LIR

OUT IN OUT

IN SW LOAD MAX

()

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________ 21

inductor manufacturers provide inductors in standard values, such as 1.0μH, 1.5μH, 2.2μH, 3.3μH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (ΔI

INDUCTOR

) is defined by:

Ferrite cores are often the best choice, although soft saturating molded core inductors are inexpensive and can work well at 500kHz. The core must be large enough not to saturate at the peak inductor current (I

PEAK

SMPS Output Capacitor Selection

The output filter capacitor selection requires careful evaluation of several different design requirements— stability, transient response, and output ripple voltage—that place limits on the output capacitance and ESR. Based on these requirements, the typical application requires a low-ESR polymer capacitor (lower cost but higher output-ripple voltage) or bulk ceramic capacitors (higher cost but low output-ripple voltage).

SMPS Loop Compensation

Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the loop gain. This reduces the output capacitance requirement (stability and transient) and output power dissipation requirements as well. The load-line is generated by sensing the inductor current through the high-side MOSFET on-resistance, and is internally preset to -5mV/A (typ) for regulator B and -7mV/A (typ) for regulator C. The loadline ensures that the output voltage remains within the regulation window over the full-load conditions.

The load line of the internal SMPS regulators also provides the AC ripple voltage required for stability. To maintain stability, the output capacitive ripple must be kept smaller than the internal AC ripple voltage, and crossover must occur before the Nyquist pole—(1 + duty)/(2fSW)—occurs. Based on these loop requirements, a minimum output capacitance can be determined from the following:

where R

DROOP

is 2R

SENSE

for regulator A, 5mV/A for

regulator B, or 7mV/A for regulator C as defined in the

Electrical Characteristics

table, and fSWis the switching

frequency selected by the FREQ setting (see Table 1).

Additionally, an additional feedback pole—capacitor from FB to analog ground (CFB)—might be necessary to cancel the unwanted ESR zero of the output capacitor. In general, if the ESR zero occurs before the Nyquist pole, then canceling the ESR zero is recommended:

If:

Then:

where RFBis the parallel impedance of the FB resistive divider.

SMPS Output Ripple Voltage

With polymer capacitors, the effective series resistance (ESR) dominates and determines the output ripple voltage. The step-down regulator’s output ripple voltage (V

RIPPLE

) equals the total inductor ripple current

(ΔI

INDUCTOR

) multiplied by the output capacitor’s ESR. Therefore, the maximum ESR to meet the output ripple voltage requirement is:

where fSWis the switching frequency. The actual capacitance value required relates to the physical case size needed to achieve the ESR requirement, as well as to the capacitor chemistry. Thus, polymer capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value. Alternatively, combining ceramics (for the low ESR) and polymers (for the bulk capacitance) helps balance the output capacitance vs. output ripple-voltage requirements.

Vf L

VV V

ESR

IN SW

IN OUT OUT

RI PPLE

≤

()

⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

C ESR

OUT

⎛ ⎝

⎜

⎞ ⎠

⎟

ESR

SW OUT

⎛

⎝

⎜

⎞

⎠

⎟

4π

OUT

SW DROOP

REF

OUT

⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

IIN

⎛ ⎝

⎜

⎞ ⎠

⎟

PEAK LOAD MAX

INDUCTOR

⎛ ⎝

⎜

⎞ ⎠

⎟

()

ΔI

VVV

Vf L

INDUCTOR

OUT IN OUT

IN SW

()

MAX17019

High-Input-Voltage Quad-Output Controller

22 ______________________________________________________________________________________

Internal SMPS Transient Response

The load-transient response depends on the overall output impedance over frequency, and the overall amplitude and slew rate of the load step. In applications with large, fast load transients (load step > 80% of full load and slew rate > 10A/μs), the output capacitor’s high-frequency response—ESL and ESR—needs to be considered. To prevent the output voltage from spiking too low under a load-transient event, the ESR is limited by the following equation (ignoring the sag due to finite capacitance):

where V

STEP

is the allowed voltage drop, ΔI

LOAD(MAX)

the maximum load step, and R

PCB

is the parasitic board

resistance between the load and output capacitor.

The capacitance value dominates the midfrequency output impedance and dominates the load-transient response as long as the load transient’s slew rate is less than two switching cycles. Under these conditions, the sag and soar voltages depend on the output capacitance, inductance value, and delays in the transient response. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step, especially with low differential voltages across the inductor. The sag voltage (V

SAG

) that occurs after applying the load current can be estimated by the following:

where D

MAX

is the maximum duty factor (see the

Electrical Characteristics

table), T is the switching peri-

od (1/f

OSC

), and ΔT equals V

OUT/VIN

x T when in PWM

mode, or L x I

IDLE

/(VIN- V

OUT

) when in pulse-skipping

mode. The amount of overshoot voltage (V

SOAR

) that occurs after load removal (due to stored inductor energy) can be calculated as:

When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V

SOAR

from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.

Input Capacitor Selection

The input capacitor must meet the ripple current requirement (I

RMS

) imposed by the switching currents.

The I

RMS

requirements of an individual regulator can be

determined by the following equation:

The worst-case RMS current requirement occurs when operating with VIN= 2V

OUT

. At this point, the above

equation simplifies to I

RMS

= 0.5 x I

LOAD.

However, the MAX17019 uses an interleaved fixed-frequency architecture, which helps reduce the overall input RMS current on the INBC input supply.

For the MAX17019 system (INA) supply, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. For the MAX17019 INBC input supply, ceramic capacitors are preferred on input due to their low parasitic inductance, which helps reduce the high-frequency ringing on the INBC supply when the internal MOSFETs are turned off. Choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity.

BST Capacitors

The boost capacitors (C

BST

) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. For these low-power applications, 0.1μF ceramic capacitors work well.

Regulator A Power-MOSFET Selection

Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention.

The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V

IN(MIN)

and V

IN(MAX)

. Ideally, the losses at V

IN(MIN)

should be roughly equal to the losses at V

IN(MAX)

, with

lower losses in between. If the losses at V

IN(MIN)

are significantly higher, consider increasing the size of NH. Conversely, if the losses at V

IN(MAX)

are significantly higher, consider reducing the size of NH. If VINdoes not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses.

Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (R

DS(ON)

), comes in a moder-

ate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),

VVV

RMS

LOAD

OUT IN OUT

⎛ ⎝

⎜

⎞ ⎠

⎟

()

SOA R

LOAD MAX

OUT OUT

≈

()

CVD V

SAG

LOAD MAX

OUT IN MAX OUT

()

LLOAD MAX

OUT

()

- Δ

()

ESR

STEP

LOAD MAX

PCB

≤

⎛

⎝

⎜

⎞

⎠

⎟

()

MAX17019

High-Input-Voltage Quad-Output Controller

______________________________________________________________________________________ 23

and is reasonably priced. Ensure that the MAX17019 DLA gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology.

Power-MOSFET Dissipation

Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage:

Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the R

DS(ON)

required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (R

DS(ON)

) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V.

Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:

where C

OSS

is the output capacitance of NH, Q

G(SW)

is the charge needed to turn on the NH MOSFET, and I

GATE

is the peak gate-drive source/sink current (1A typ).

Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x V

x f

). If the high-side MOSFET

chosen for adequate R

DS(ON)

at low battery voltages becomes extraordinarily hot when subjected to V

IN(MAX)

, consider choosing another MOSFET with

lower parasitic capacitance.

For the low-side MOSFET (N

) the worst-case power

dissipation always occurs at maximum battery voltage:

The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than I

LOAD(MAX)

, but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate:

where I

LIMIT

is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation.

Choose a Schottky diode (DL) with a forward voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical.

VTT LDO Design Procedure

IND Input Capacitor Selection (C

IND

)

The value of the IND bypass capacitor is chosen to limit the amount of ripple and noise at IND, and the amount of voltage sag during a load transient. Typically, IND connects to the output of a step-down switching regulator, which already has a large bulk output capacitor. Nevertheless, a ceramic capacitor equivalent to half the VTT output capacitance should be added and placed as close as possible to IND. The necessary capacitance value must be increased with larger load current, or if the trace from IND to the power source is long and results in relatively high input impedance.

VTT LDO Output Voltage (FBD)

The VTT output stage is powered from the IND input. The VTT output voltage is set by the REFIND input. REFIND sets the VTT LDO feedback regulation voltage (V

FBD

= V

REFIND

) and the VTTR output voltage. The VTT LDO (FBD voltage) and VTTR track the REFIND voltage over a 0.5V to 1.5V range. This reference input feature makes the MAX17019 ideal for memory applications in which the termination supply must track the supply voltage.

LOAD LIMIT

INDUCTOR

⎛ ⎝

⎜

⎞ ⎠

⎟

PD N sistive

OUT

IN MAX

LOAD DS ON

()

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

()

−1

PD N Switching

IQICV

LOAD G SW

GATE

OSS IN M() (

()

AAX

IN MAX SW

)

()

⎛

⎝

⎜

⎞

⎠

⎟

PD N sistive

OUT

LOAD DS O

(

()

⎛ ⎝

⎜

⎞ ⎠

⎟

()

NN)

MAX17019

High-Input-Voltage Quad-Output Controller

24 ______________________________________________________________________________________

VTT LDO Output Capacitor

Selection (C

OUTD

)

A minimum value of 20μF or greater ceramic is needed to stabilize the VTT output (OUTD). This value of capacitance limits the switching regulator’s unity-gain bandwidth frequency to approximately 1.2MHz (typ) to allow adequate phase margin for stability. To keep the capacitor acting as a capacitor within the switching regulator’s bandwidth, it is important that ceramic capacitors with low ESR and ESL be used.

Since the gain bandwidth is also determined by the transconductance of the output MOSFETs, which increases with load current, the output capacitor might need to be greater than 20μF if the load current exceeds 1.5A, but can be smaller than 20μF if the maximum load current is less than 1.5A. As a guideline, choose the minimum capacitance and maximum ESR for the output capacitor using the following:

and:

ESR

value is measured at the unity-gain-bandwidth

frequency given by approximately:

Once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or voltage ripple at the output.

VTTR Output Capacitor Selection

The VTTR buffer is a scaled-down version of the VTT regulator, with much smaller output transconductance. Therefore, the VTTR compensation requirements also scale. For typical applications requiring load currents up to ±3mA, a 0.22μF or greater ceramic capacitor is recommended (R

ESR

< 0.3Ω).

VTT LDO Power Dissipation

Power loss in the MAX17019 VTT LDO is significant and can become a limiting design factor in the overall MAX17019 design:

VTT

= 2A x 0.9V = 1.8W

The 1.8W total power dissipation is within the 40-pin TQFN multilayer board power-dissipation specification of 2.9W. The typical DDR termination application does not actually continuously source or sink high currents. The actual VTT current typically remains around 100mA to 200mA under steady-state conditions. VTTR is down in the microampere range, though the Intel specification requires 3mA for DDR1 and 1mA for DDR2. True worst-case power dissipation occurs on an output short-circuit condition with worst-case current limit. The MAX17019 does not employ any foldback current limiting, and relies on the internal thermal shutdown for protection. Both the VTT and VTTR output voltages are referenced to the same REFIND input.

Applications Information

Minimum Input Voltage

The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the

Electrical Characteristics

table). For the best dropout performance, use the slowest switching frequency setting (FREQ = GND). However, keep in mind that the transient performance gets worse as the stepdown regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the

SMPS Design Procedure

(Step-Down Regulators)

section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (ΔI

DOWN

) as much as it ramps up during the on-time (ΔIUP). This results in a minimum operating voltage defined by the following equation:

where V

CHG

and V

DIS

are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1.

VVVhDVV

IN MIN OUT CHG

MAX

OUT DIS()

=++

⎛ ⎝

⎜

⎞ ⎠

⎟

(

))

GBW

OUT

LOAD

=×

15.

ESR MAX

LOAD

=×515Ω

CμF

OUT MIN

LOAD

=×20

MAX17019

High-Input-Voltage Quad-Output Controller

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Maximum Input Voltage

The MAX17019 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the

Electrical Characteristics

table). Operation above this maximum input voltage results in pulse skipping to avoid overcharging the output. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (V

IN(SKIP)

where f

OSC

is the switching frequency selected by

FREQ.

PCB Layout Guidelines

Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another.

Follow the MAX17019 evaluation kit layout and use the following guidelines for good PCB layout:

• Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation.

• Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty.

• Minimize current-sensing errors by connecting CSPA and CSNA directly across the current-sense resistor (R

SENSE_

• When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.

• Route high-speed switching nodes (BST_, LX_, DHA, and DLA) away from sensitive analog areas (REF, REFIND, FB_, CSPA, CSNA).

IN SKIP OUT

OSC ON MIN

()

⎛

⎝

⎜

⎞

⎠

⎟

Chip Information

TRANSISTOR COUNT: 22,577

PROCESS: BiCMOS

Package Information

For the latest package outline information, go to

www.maxim-ic.com/packages

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

48 TQFN T4866-2

21-0141

Datasheet MAX17019, MAX17019ATM+ Datasheet (Maxim)

Specifications and Main Features

Frequently Asked Questions

User Manual