The MAX1601/MAX1604 DC power-switching ICs contain a network of low-resistance MOSFET switches that
deliver selectable VCC and VPP voltages to two
CardBus or PC Card host sockets. Key features include
ultra-low-resistance switches, small packaging, softswitching action, and compliance with PCMCIA specifications for 3V/5V switching. 3.3V-only power switching
for fast, 32-bit CardBus applications is supported in two
ways: stiff, low-resistance 3.3V switches allow high 3.3V
load currents (up to 1A); and completely independent
internal charge pumps let the 3.3V switch operate normally, even if the +5V and +12V supplies are disconnected or turned off to conserve power. The internal
charge pumps are regulating types that draw reduced
input current when the VCC switches are static. Also,
power consumption is automatically reduced to 10µA
max when the switches are programmed to high-Z or
GND states over the serial interface, unlike other solutions that may require a separate shutdown-control
input.
Other key features include guaranteed specifications for
output current limit level, and guaranteed specifications
for output rise/fall times (in compliance with PCMCIA
specifications). Reliability is enhanced by thermal-overload protection, accurate current limiting, an overcurrent-fault flag output, undervoltage lockout, and extra
ESD protection at the VCC/VPP outputs. The SMBus serial interface is flexible, and can tolerate logic input levels
in excess of the positive supply rail.
The MAX1604 and MAX1601 are identical, except
for the MAX1604’s VY switch, which has roughly threetimes the on-resistance (typically 140mΩ).The
MAX1601/MAX1604 fit two complete CardBus/PCMCIA
switches into a space-saving, narrow (0.2in. or 5mm
wide) SSOP package.
ADR Input to GND ...........................................-0.3V, (VL + 0.3V)
VCCA, VCCB Output Current (Note 2).....................................4A
VPPA, VPPB Output Current (Note 2)...............................250mA
Note 1: There are no parasitic diodes between any of these pins, so there are no power-up sequencing restrictions (for example,
logic input signals can be applied even if all of the supply voltage inputs are grounded).
Note 2: VCC and VPP outputs are internally current-limited to safe values. See the
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
MAX1601/MAX1604
(VL = VY = 3.3V, VX = 5V, 12INA = 12INB = 12V, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Note 3: Not production tested.
Note 4: Thermal limit not active in standby state (all switches programmed to GND or high-Z state).
Note 5: A transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of the falling
412INA+12V Supply Voltage Input, internally connects to channel A VPP switch. Tie to VPPA if not used.
5VPPAChannel A VPP Output
6, 8, 10VX
7, 22, 24VCCAChannel A VCC Outputs
9, 18, 20VCCBChannel B VCC Outputs
11VPPBChannel B VPP Output
1212INB+12V Supply Voltage Input, internally connects to channel B VPP switch. Tie to VPPB if not used.
13ADRAddress Input, sets SMBus address location. See Table 1 for address selection.
14
15SMBCLKSMBus Clock Input
16SMBDATASMBus Data Input/Output, open drain
17
19, 21, 23VY
28VL
NAMEFUNCTION
N.C.No internal connection
VX Supply-Voltage Inputs. VX pins must be connected together. Input range is 3V to 5.5V. VX is
normally connected to 5V.
SMBus Suspend-Mode Control Input. The device will execute commands previously stored in
SMBSUS
SMBALERT
the normal-mode register if SMBSUS is high, or will execute commands previously stored in the
suspend-mode register if SMBSUS is low.
Fault-Detection Interrupt Output. SMBALERT goes low if either channel VCC or VPP switch is
current limiting or undervoltage lockout, or if the thermal protection circuit is activated.
SMBALERT is an open-drain output that requires an external pull-up resistor.
VY Supply-Voltage Inputs. VY pins must be connected together. Input range is 3V to 5.5V. VY is
normally connected to 3V.
Logic Supply-Voltage Inputs. Connect to the +3.3V or +5V host system supply. VL can be supplied via the output of a CMOS-logic gate to produce an overriding shutdown. When used as a
shutdown input, VL should have a 1kΩ series resistor with a 0.1µF capacitor to ground (Figure 2).
Note that VL must be greater than undervoltage lockout for any switches to be turned on.
The MAX1601/MAX1604 power-switching ICs contain a
network of low-resistance MOSFET switches that deliver
selectable VCC and VPP voltages to two Cardbus or
PC Card host sockets. The MAX1601/MAX1604 differ
only in the VY switch on-resistance. Figure 1 is the
detailed block diagram.
The power-input pins (VY, VX, 12IN_) are completely
independent. Low inrush current is guaranteed by controlled switch rise times. VCC’s 100µs minimum output
rise time is 100% tested with a 1µF capacitive load, and
VPP’s 1ms minimum rise time is guaranteed with a 0.1µF
load. These respective capacitive loads are chosen as
worst-case card-insertion parameters. The internal
switching control allows VCC and VPP rise times to be
controlled, and makes them nearly independent of resistive and capacitive loads (see rise-time photos in the
Typical Operating Characteristics
function of loading, and are compensated by internal
circuitry.
Power savings is automatic: internal charge pumps draw
very low current when the VCC switches are static.
Standby mode reduces switch supply current to 1µA.
Driving the VL pin low with an external logic gate (master
shutdown) reduces total supply current to1µA (Figure 2).
The MAX1601/MAX1604 have three operating modes:
normal, standby, and shutdown. Normal mode supplies
the selected outputs with their appropriate supply voltages. Standby mode places all switches at ground, high
impedance, or a combination of the two. Shutdown mode
turns all switches off, and puts the VCC and VPP outputs
into a high-impedance state. Pull VL low to enter shutdown
mode. To ensure a 0.05V/µs fall rate on VL, use a 1kΩ
series resistor and a 0.1µF capacitor to ground (Figure 2).
Overcurrent Protection
Peak detecting circuitry protects both the VCC and
VPP switches against overcurrent conditions. When
current through any switch exceeds the internal current
limit (4A for VCC switches and 200mA for VPP switches), the switch turns off briefly, then turns on again at
the controlled rise rate. If the overcurrent condition
lasts more than 2µs, the SMBALERT output latches
). Fall times are a
Operating Modes
3.3V
VY
MAX1601
MAX1604
VPPA
VCCA
TO
SOCKETS
A AND B
VPPB
VCCB
MASTER
SHUTDOWN
74HC04
Figure 2. Master Shutdown Circuit
1k
0.1µF
VL
low. A continuous short-circuit condition results in a
pulsed output current until thermal shutdown is
reached. SMBALERT is open-drain and requires an
external pull-up resistor.
Thermal Shutdown
If the IC junction temperature rises above +150°C, the
thermal shutdown circuitry opens all switches, including
the GND switches, and SMBALERT is pulled low. When
the temperature falls below +130°C, the switches turn
on again at the controlled rise rate. If the overcurrent
condition remains, the part cycles between thermal
shutdown and overcurrent.
Undervoltage Lockout
If the VX or VY switch input voltage drops below 1.5V,
the associated switch turns off and SMBALERT goes
low. For example, if VY is 3.3V and VX is 0V, and if the
interface controller selects VY, the VCCA output will be
3.3V. If VX is selected, VCCA changes to a high-impedance output and SMBALERT goes low.
When a voltage is initially applied to 12IN_, it must be
greater than 8V to allow the switch to operate.
Operation continues until the voltage falls below 2V (the
VPP output is high impedance).
When VL drops to less than 2.3V, all switches are
turned off and the VCC and VPP outputs are high
impedance.
Dual-Channel CardBus and PCMCIA
Power Switches with SMBus™ Serial Interface
______SMBus™ Interface Operation
The SMBus serial interface is a two-wire interface with
multi-mastering capability, intended to control lowspeed peripheral devices in low-power portable equipment applications. SMBus is similar to I2C™ and
AccessBus, but has slightly different logic threshold
voltage levels, different fixed addresses, and a suspend-mode register capability. To obtain a complete
set of specifications on the SMBus interface, call Intel at
(800) 253-3696 and ask for product code SBS5220.
SMBus Addressing
These dual-channel PC Card switch devices respond to
two of four different addresses, depending on the state
of the ADR address pin. Normal writing to the device is
done by transmitting one of four addresses, followed by
a single data byte, to program the channel selected.
Write transmissions to the interrupt pointer address are
not supported by these devices. Reading from the
MAX1601/MAX1604
device is done by transmitting one of two addresses cor-
responding to either the A channel address (which will
provide data about faults for both A and B channels) or
to the interrupt pointer address (discussed later).
The normal start condition consists of a high-to-low
transition on SMBDATA while SMBCLK is high. The
7-bit address is followed by a bit that designates a read
or write operation: high = read, low = write. If the 7-bit
address matches one of the supported function
addresses, the IC issues an acknowledge pulse by
pulling the SMBDATA line low. If the address is not
valid, the IC stays off of the bus and ignores any data
on the bus until a new start condition is detected. Once
the IC receives a valid address that includes a write bit,
it expects to receive one additional byte of data. If a
stop condition or new start condition is detected before
a complete byte of data is clocked in, the IC interprets
this as an error and all of the data is rejected and lost.
SMBDATA and SMBCLK are Schmitt triggered and can
accommodate slower edges. However, rising edges
should still be faster than 1µs, and falling edges should
be faster than 300ns.
SMBus Write Operations
If the IC receives a valid address immediately followed
by a write bit, the IC becomes a slave receiver. The
slave IC generates a first acknowledge after the
address and write bit, and a second acknowledge after
the command byte. A stop condition following the command (data) byte causes immediate execution of the
command, unless the data included a low SUS/OP bit.
If the data included a low SUS/OP bit, the command is
stored in the suspend-mode register and is executed
only when the SMBSUS pin is pulled low (Figure 3).
Table 2. Command Format for Channel A Write Operations (address 1010000 or 1010010)
FUNCTIONPOR STATENAMEBIT
0OP/SUS7 (MSB)
I2C is a trademark of Philips Corp.
SMBus is a trademark of Intel Corp.
Operate/suspend bit. Selects which latch receives data: high = operation,
low = suspend.
Turns on VCCA when high, pulls VCCA to GND when low.0VCCAON6
If VCCA is on, a high connects VY to VCCA, and a low connects VX to VCCA.0VCCA3/55
Puts VCCA in a high-impedance state when high. Overrides VCCAON.0VCCAHIZ4
Turns on VPPA when high, pulls VPPA to GND when low.0VPPAON3
If VPPA is on, a high connects VPPA to 12INA, and a low connects VPPA to VCCA.0VPPAPGM2
Puts VPPA in a high-impedance state when high. Overrides VPPAON.0VPPAHIZ1
Masks fault interrupts from both channel A and channel B when high.0MASKFLT0 (LSB)
Dual-Channel CardBus and PCMCIA
Power Switches with SMBus™ Serial Interface
Table 3. Command Format for Channel B Write Operations (address 1010001 or 1010011)
BITNAMEPOR STATEFUNCTION
7 (MSB)OP/SUS0
6VCCBON0Turns on VCCB when high, pulls VCCB to GND when low.
5VCCB3/50If VCCB is on, a high connects VY to VCCB, and a low connects VX to VCCB.
4VCCBHIZ0Puts VCCB in a high-impedance state when high. Overrides VCCBON.
3VPPBON0Turns on VPPB when high, pulls VPPB to GND when low.
2VPPBPGM0If VPPB is on, a high connects VPPB to 12INB, and a low connects VPPB to VCCB.
1VPPBHIZ0Puts VPPB in a high-impedance state when high. Overrides VPPBON.
0 (LSB)RFU0Reserved for future use.
Operate/suspend bit. Selects which latch receives data: high = operation,
low = suspend.
Table 4. Read Format for Interrupt Pointer Address (0001100)
BITNAMEPOR STATEFUNCTION
7 (MSB)ADD70
6ADD60
5ADD50
4ADD40
3ADD30
2ADD20
1ADD10
0 (LSB)ADD00
ADD7 to ADD1 provide a return address for any interrupt query. For these devices, the
return addresses are:
1010000 = Channel A, ADD = low
1010001 = Channel B, ADD = low
1010010 = Channel A, ADD = high
1010011 = Channel B, ADD = high
MAX1601/MAX1604
Table 5. Read Format for Power Switch Address (1010000 or 1010010)
BITNAMEPOR STATEFUNCTION
7 (MSB)CATFAULT0Indicates catastrophic (thermal or undervoltage lockout) fault when high.
6FAULT10Indicates VCCA overcurrent/undervoltage lockout when high.
5FAULT20Indicates VPPA overcurrent/undervoltage lockout when high.
4FAULT30Indicates VCCB overcurrent/undervoltage lockout when high.
3FAULT40Indicates VPPB overcurrent/undervoltage lockout when high.
2SIG/DUAL0Indicates dual part (single-channel devices would read 1).
1RFU0Reserved for future use.
Dual-Channel CardBus and PCMCIA
Power Switches with SMBus™ Serial Interface
AB CD
t
LOWtHIGH
SMBCLK
SMBDATA
t
t
HD:STA
SU:STA
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
t
SU:DAT
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
MAX1601/MAX1604
Figure 3. SMBus Write Timing Diagram
SMBus Read Operations
If the IC receives a valid address that includes a read
bit, the IC becomes a slave transmitter. After receiving
the address data, the IC generates an acknowledge
during the acknowledge clock pulse and drives the
SMBDATA line in sync with SMBCLK. The SMB protocol requires that the master end the read transmission
by not acknowledging during the acknowledge bit of
SMBCLK. These PC Card ICs support the repeated
start-condition method for changing data-transfer direction; that is, a write transmission followed by a repeated
start instead of a stop condition prepares the IC for
data reading (Figure 4).
SMBus Interrupts
These PC Card power-switch ICs are slave devices
only, and never initiate communications except by
asserting an interrupt (by pulling SMBALERT low).
Interrupts are generated only for reporting fault conditions, including overcurrent at VCCA, VCCB, VPPA, or
VPPB, undervoltage lockout, and IC thermal overload. If
an interrupt occurs, it can be an indication of impending system failure. The host system can react by going
into suspend mode or taking other action. It can come
back later to interrogate the IC via the interrupt pointer
to determine status or perform corrective action (such
as disabling the appropriate power switch that might
be connected to a shorted PC card). The fastest
method for turning off the switches in response to a
E
FG H
t
HD:DAT
I
J
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
K
t
SU:STO
fault condition is to cycle the voltage on VL in order to
generate a power-on reset (which clears all of the
SMBus registers). Note that the SMBus registers retain
their data even if the main VX/VY supplies are turned
off, provided that VL remains powered.
When a fault occurs, SMBALERT is immediately asserted and latched low. If the fault is momentary and disappears before the IC is serviced, the data is still latched
in the interrupt pointer and SMBALERT remains asserted. Normally, the master (host system or PCMCIA digital controller) now sends out the interrupt pointer
address (00011000) followed by a read bit. SMBALERT
is cleared and the PC Card IC responds by putting out
its address on the bus. If the fault persists, SMBALERT
is re-asserted, but the data in the fault registers is not
reloaded. The data in the fault latches only reflects the
first time SMBALERT is asserted.
When the part enters operating mode, a false interrupt
flag may be issued. The user needs to send the interrupt address to clear the false interrupt.
Normally, the master sends out the appropriate PC Card
switch address on the bus, followed by a read bit. The
data in the fault registers is then clocked out onto the
bus (which also clears the fault registers). If the fault
persists, the fault bits and SMBALERT are latched
again.
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
Figure 4. SMBus Read Timing Diagram
t
SU:DAT
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
The interrupt pointer address provides quick fault identification for simple slave devices that lack the complex,
expensive logic needed to be a bus master. The host
can read the interrupt pointer to determine which slave
device generated an SMBALERT interrupt signal. The
interrupt pointer address can activate several different
slave devices simultaneously, similar to an I2C general
call. Any slave device that generated an interrupt
attempts to identify itself by putting its own address on
the bus during the first read byte. If more than one slave
attempts to respond, bus arbitration rules apply and the
device with the lower address code wins. The losing
device won’t generate an acknowledge and will continue to hold the SMBALERT line low until serviced, which
implies that the host interrupt input must be level
sensitive.
__________Applications Information
t
t
SU:STO
BUF
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
Changing SMBCLK and SMBDATA
Simultaneously
When clocking data into the MAX1601/MAX1604, SMBDATA must not fall before SMBCLK. Otherwise, the
MAX1601/MAX1604 may interpret this as a start condition. Even when SMBDATA and SMBCLK fall at the
same instant, different fall times for the two signals may
cause the erroneous generation of a start condition. To
ensure that SMBDATA transitions after the falling edge of
SMBCLK, add an RC network to SBMDATA (Figure 6).
1k
VL
0.1µF
VX+5V
MAX1601
MAX1604
Supply Bypassing
Bypass the VY, VX, and 12IN_ inputs with ceramic 0.1µF
capacitors. Bypass the VCC_ and VPP_ outputs with a
0.1µF capacitor for noise reduction and ESD protection.
Power-Up
Apply power to the VL input before any of the switch
inputs. If VX, VY, or 12IN receive power before VL rises
above 2.8V, the supply current may be artificially high
(about 5mA). When the voltage on VL is greater than
2.8V (operating mode), the part consumes its specified
24µA. To avoid power sequencing, diode-OR VX and
VY to VL through a 1kΩ resistor (Figure 5). Take care
not to allow VL to drop below the 2.8V maximum undervoltage lockout threshold.
________________________________________________________Package Information
DIM
A
A1
B
C
α
HE
C
L
D
E
e
H
L
α
INCHES
MIN
0.068
0.002
0.010
0.004
0.205
0.301
0.025
MAX
0.078
0.008
0.015
0.008
SEE VARIATIONS
0.209
0.311
0.037
0˚
8˚
MILLIMETERS
MIN
1.73
0.05
0.25
0.09
5.20
0.65 BSC0.0256 BSC
7.65
0.63
0˚
MAX
1.99
0.21
0.38
0.20
5.38
7.90
0.95
8˚
14
16
20
24
28
INCHES
MIN
0.239
0.239
0.278
0.317
0.397
DIM
PINS
e
SSOP
A
SHRINK
SMALL-OUTLINE
B
A1
PACKAGE
D
D
D
D
D
MAX
0.249
0.249
0.289
0.328
0.407
MILLIMETERS
MAX
MIN
6.33
6.07
6.33
6.07
7.33
7.07
8.33
8.07
10.33
10.07
21-0056A
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600