MAXIM MAX14983E Technical data

19-5935; Rev 0; 6/11

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

General Description

The MAX14983E integrates high-bandwidth analog switches, level-translating buffers, and 5V power switches to implement a complete 1:2 multiplexer for VGA monitors. The device switches graphics signals between a controller and two outputs. Integrated pullup resistors (2.2kI typ) are provided on the monitor-side display data channel (DDC) signal lines.

The device features a simple power interface that operates with a single +5V supply input. Two integrated power switches with current limiting and reverse-current protection pass the +5V supply to external loads with minimal voltage drop.

The horizontal and vertical synchronization (HSYNC/ VSYNC) buffers shift logic levels to support +2.5V to +5.0V CMOS or TTL-compatible graphics controllers while meeting the VESA drive capability requirement of Q8mA. An internal 2.5V regulator translates the DDC voltage levels to be compatible with low-voltage graphics controllers.

The device also features monitor-detect outputs and enable inputs that allow monitor switching to operate either automatically or with inputs from the graphics controller.

The MAX14983E is available in a 32-pin (5mm x 5mm) TQFN package, and is specified over the -40NC to +85NC extended temperature range.

Benefits and Features

S Design Flexibility

 Graphics Controller Port is Protected when VCC = 0V  DDC Switches Limit Voltage to Low-Voltage Supply  Internal +2.5V Regulator

S High Level of Integration for Enhanced

Performance

 Low 5.5pF (typ) RGB Capacitance  2.0ns (typ) tR/tF with 10pF, 2.2kI Load on

Monitor-Side SYNC Signals  Source and Sink 8mA While Meeting Speed Requirements  ±11kV Human Body Model (HBM)

S Saves Space on Board

 Internal Power Switches Pass +5V with 300mV (max) IR Drop Short-Circuit/Thermal/Reverse-Current Protection  5mm x 5mm, 32-Pin TQFN Package

Typical Operating Circuit

+5V

+2.5V

0.1µF

Applications

Servers

KVM Switches

Computing

Graphics Cards

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX14983E.related.

�� Maxim Integrated Products 1

GRAPHICS

CONTROLLER

S5V2

3

R0, G0, B0 R1, G1, B1

2

HSYNC0, VSYNC0

2

SCL0, SDA0

MDOR

S5V1

MAX14983E

MD1

MD2

EN1

EN2

V

CC

HSYNC1, VSYNC1

SCL1, SDA1

R2, G2, B2

HSYNC2, VSYNC2

SCL2, SDA2

GND

S5V1

S5V2

REF

3

2

VGA

2

PORT 1

1µF

3

2

VGA

2

PORT 2

1µF

105I

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to GND.) VCC, S5V1, S5V2, SDA_, SCL_, REF, MD_,

EN_, MDOR .........................................................-0.3V to +6V

HSYNC_, VSYNC_, R_, G_, B_ ................. -0.3V to (VCC + 0.3V)

Continuous Current Through R_, G_, B_ Switches ......... Q50mA

Continuous Current Through SDA_, SCL_ Switches ...... Q50mA

Continuous Current Through S5V_ ............................... Q750mA

Peak Current Through R_, G_, B_, SDA_, SCL_

(10% duty cycle) ....................................................... Q100mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

TQFN

Junction-to-Ambient Thermal Resistance (BJA) ..........29NC/W

Junction-to-Case Thermal Resistance (BJC) ..............1.7NC/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Continuous Power Dissipation (TA = +70NC)

TQFN (derate 34.5mW/NC above +70NC)...............2758.6mW

Operating Temperature Range .......................... -40NC to +85NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ...............................+300NC

Soldering Temperature (reflow) ......................................+260NC

ELECTRICAL CHARACTERISTICS

(VCC = +5V Q5%, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +5V, TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY

Quiescent Current I

Operating Current I

5V SWITCH (S5V1, S5V2 OUTPUTS)

S5V_ Voltage Drop V

Reverse Leakage Current I

Pulldown Resistor

Output Current Limit I

Thermal-Shutdown Threshold T

Thermal-Shutdown Hysteresis

R

T

SHDN_

Q

CC

S5V

L

S5V1

S5V2

LIM

SHDN

HYS

VCC = 5.25V, V unconnected

HSYNC0 = 50kHz, VSYNC0 = 60Hz 10% duty cycle, RL on SYNC outputs = 2kI, REF unconnected

I

= 55mA 0.3 V

OUT

VCC = 0V, V V

= 5.25V, no load on S5V1 or S5V2

S5V2

,

V

= V

S5V1

S5V2

EN1

= 1V, V

= V

EN2

= VCC, REF

EN2

= 0V, V

= V

EN1

S5V1

EN2

= V

=

CC

50 150

1.5 2.7 mA

10

250

55 300 500 mA

+150

25

FA

I

NC

�� Maxim Integrated Products 2

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +5V Q5%, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +5V, TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DDC SWITCHES (SDA�, SCL� INPUTS/OUTPUTS)

Input Leakage Current I

Off-Leakage Current I

On-Resistance R

SDA1, SDA2, SCL1, SCL2 Internal Pullup Resistance

CONTROL SIGNALS (HSYNC�, VSYNC�, EN_ INPUTS/OUTPUTS)

Input Logic-Low Voltage V

Input Logic-High Voltage V

Output Logic-Low Voltage V

Output Logic-High Voltage

Rise Time/Fall Time tR, t

MONITOR DETECTION OUTPUTS (MD_, MDOR)

Output-Voltage Low V

Input Leakage Current I

R�, G�, B� SWITCH PERFORMANCE

Bandwidth f

On-Loss I

On-Resistance R

On-Resistance Matching

On-Resistance Flatness R

B1, B2 Internal Pullup Resistance R

Off-Leakage Current I

Off-Capacitance C

On-Capacitance C

ESD PROTECTION

LOFF

R

PULLUPVSDA_

V

LOD

MAX

LOSS

DR

FLAT(ON)

LOFF

OFF

V

L

ON

IL

IH

OL

OH

F

OL

ON

B

ON

= VCC, V

EN1

VIN = +5.25V, VCC = 0V 10

VIN = 0.8V, I

= V

HSYNC0, VSYNC0, EN1, EN2 HSYNC0, VSYNC0, EN1, EN2

HSYNC1, HSYNC2, VSYNC1, VSYNC2, I

= 8mA

SINK

HSYNC1, HSYNC2, VSYNC1, VSYNC2, I

SOURCE

HSYNC0 input tR/tF < 5ns, 10% to 90% 2 ns

R

VIN = 3.3V, MD_ and MDOR deasserted

Figure 1, RS = RL = 50I

Figure 1, f = 50MHz, RS = RL = 50I

IIN = ±10mA, VIN = 0.7V

IIN = ±10mA, VIN = 0 to 0.7V

VR_ = VG_ = VB0 = 0V or V

f = 1MHz; R0, G0, B0 to R_, G_, B_ 2.5 pF

f = 1MHz; R0, G0, B0 to R_, G_, B_ 5.5 pF

= 8mA

= 3.3kI, VPU = 3.3V (Note 3)

PULLUP

= VCC, VIN = 0V or 5.25V

EN2

= I

SDA_

= 4V 2.2

SCL_

= ±10V 25

SCL_

CC

-1 +1

0.8 V

2 V

0.5 V

2.4 V

0.3 V

1

800 MHz

-0.6 dB

5 8

1

0.5 1

2.5

-1 +1

FA

I

kI

FA

I

kI

FA

High-ESD Pins ESD Protection Human Body Model (Note 4)

All Other Pins ESD Protection Human Body Model (Note 4)

Note 2: All units are production tested at TA = +25NC. Specifications over temperature are guaranteed by design. Note 3: VPU is the pullup voltage. Note 4: See the Pin Description section for the ESD status of each pin.

�� Maxim Integrated Products 3

Q11

Q2

kV

Enhanced 1:2 VGA Mux with

02

05

Monitor Detection and Priority Port Logic

+5V

0.1µF

V

0V OR V

50I

MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. ON-LOSS IS MEASURED BETWEEN R0 AND R1 ON EACH SWITCH. SIGNAL DIRECTION THROUGH IS REVERSED; WORST VALUES ARE RECORDED.

EN1,

CC

EN2

R1, G1, B1

CC

MAX14983E

GND

R0, G0, B0

R2, G2, B2

V

IN

V

OUT

NETWORK

ANALYZER

50I

MEAS REF

50I 50I

50I

MAX14983E

V

ON-LOSS = 20log

V

OUT

IN

Figure 1. On-Loss

(VCC = +5.0V, TA = +25NC, unless otherwise noted.)

DDC ON-RESISTANCE

vs. ANALOG SIGNAL VOLTAGE

50

I

= 10mA

SDA0

40

30

(I)

ON

R

20

TA = +85°C

10

0

TA = +25°C

V

SDA0

TA = -40°C

1.51.00.5

(V)

MAX14983E toc01

.0

Typical Operating Characteristics

RGB ON-RESISTANCE

vs. ANALOG SIGNAL VOLTAGE

50

IRO = 10mA

40

30

(I)

ON

R

20

TA = +85°C

10

0

TA = +25°C

TA = -40°C

4321

VR0 (V)

MAX14983E toc02

�� Maxim Integrated Products 4

Monitor Detection and Priority Port Logic

Typical Operating Characteristics (continued)

(VCC = +5.0V, TA = +25NC, unless otherwise noted.)

MAX14983E

Enhanced 1:2 VGA Mux with

0

FREQUENCY RESPONSE

-1

-2

-3

-4

-5

-6

-7

FREQUENCY RESPONSE (dB)

-8

-9

G0 TO G1

-10

FREQUENCY (Hz)

100E+610E+61E+6100E+3 1E+9

TOP VIEW

G1

R1

SCL1

SDA1

S5V1

MD2

MD1

EN1

*CONNECT EP TO GND.

MAX14983E toc03

HSYNC1

2324 22 20 19 18

25

26

27

28

29

30

31

+

32

12

RO

GND

REF

GNDB1VSYNC2

VSYNC1

21

MAX14983E

4567

3

G0

BO

HSYNC0

TQFN

*EP

VSYNC0

HSYNC_/ VSYNC_ OUTPUT VOLTAGE

vs. TEMPERATURE

5

V

4

I

SOURCE/ISINK

3

(V)

OL

/V

OH

V

2

1

0

-40 85

OH

= 8mA

V

OL

TEMPERATURE (°C)

Pin Configuration

HSYNC2

B2

17

16

G2

R2

15

14

SCL2

SDA2

13

12

S5V2

V

11

CC

10

MDOR

9

EN2

8

SCLO

SDAO

MAX14983E toc04

6035-10-15

�� Maxim Integrated Products 5

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Pin Description

PIN NAME FUNCTION ESD

1, 20 GND Ground —

2 R0 RGB Analog Input Standard

3 G0 RGB Analog Input Standard

4 B0 RGB Analog Input Standard

5 HSYNC0 Horizontal Sync Input Standard

6 VSYNC0 Vertical Sync Input Standard

7 SDA0 DDC Input/Output Standard

8 SCL0 DDC Input/Output Standard

9

10

11 V

12 S5V2 Switched 5V Out 2. S5V2 is internally pulled down when not connected. High

13 SDA2

14 SCL2

15 R2 RGB Analog Output for Port 2 High

16 G2 RGB Analog Output for Port 2 High

17 B2 RGB Analog Output for Port 2 High

18 HSYNC2 Horizontal Sync Output for Port 2 High

19 VSYNC2 Vertical Sync Output for Port 2 High

21 REF

22 VSYNC1 Vertical Sync Output for Port 1 High

23 HSYNC1 Horizontal Sync Output for Port 1 High

24 B1 RGB Analog Output for Port 1 High

25 G1 RGB Analog Output for Port 1 High

26 R1 RGB Analog Output for Port 1 High

27 SCL1

28 SDA1

29 S5V1 Switched 5V Out 1. S5V1 is internally pulled down when not connected. High

30

31

32

— EP Exposed Pad. Connect exposed pad to GND. —

EN2

MDOR

MD2

MD1

EN1 Enable Input 1. Assert EN1 to connect the graphics controller to the monitor on port 1 (see Table 1).

Active-Low Enable Input 2. Assert EN2 to connect the graphics controller to the monitor on port 2 (see Table 1).

Logic NOR Output of MD1 and MD2. MDOR asserts whenever a monitor is detected on either port. MDOR is an active-low, open-drain output.

Supply Voltage. VCC = +5.0V ±5%. Bypass VCC to GND with a 1FF or larger ceramic capacitor

CC

as close as possible to VCC.

DDC Input/Output. SDA2 has a 2.2kI (typ) internal pullup resistor to S5V2.

DDC Input/Output. SCL2 has a 2.2kI (typ) internal pullup resistor to S5V2.

Monitor-Detection Reference. Connect a 105I ±1% resistor from REF to ground.

DDC Input/Output. SCL1 has a 2.2kI (typ) internal pullup resistor to S5V1.

DDC Input/Output. SDA1 has a 2.2kI (typ) internal pullup resistor to S5V1.

Monitor-Detect Output 2. MD2 asserts when a monitor is detected on port 2. MD2 is an activelow, open-drain output.

Monitor-Detect Output 1. MD1 asserts when a monitor is detected on port 1. MD1 is an activelow, open-drain output.

Standard

High

Standard

High

Standard

�� Maxim Integrated Products 6

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Functional Diagram

V

CC

S5V1

250I

S5V2

250I

2.5V

REGULATOR

INTERNAL V

MAX14983E

L

MDOR

MD1

MD2

SDA0

SCL0

R0

G0

B0

MONITOR

DETECTION

2.2kI

R1

G1

B1

R2

G2

B2

S5V1

SDA1

SCL1

S5V2

SDA2

SCL2

HSYNC0

EN1

EN2

THERMAL

PROTECTION

CONTROL

LOGIC

GND

HSYNC1

VSYNC1VSYNC0

HSYNC2

VSYNC2

�� Maxim Integrated Products 7

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Truth Tables

Table 1. Channel Selection

EN1 EN2

0 0 Port 1

0 1 Port 1

1 0 Port 2

1 1 Not Connected

Note: The B_ switches are unconnected if the HSYNC_ input is idle.

VGA CONTROLLER

CONNECTED TO

Table 2. Monitor Detection

MONITOR 1

DETECTED

No No 1 1 1

No Yes 1 0 0

Yes No 0 1 0

Yes Yes 0 0 0

Note: MD1, MD2, and MDOR function regardless of the state of the EN_ inputs.

MONITOR 2

DETECTED

MD1 MD2 MDOR

Detailed Description

The MAX14983E integrates high-bandwidth analog switches and level-translating buffers to implement a complete 1:2 multiplexer for VGA signals. The device provides switching for red-green-blue (RGB) signals, horizontal and vertical synchronization (HSYNC/VSYNC) pulses, display data channel (DDC) signals, and 5V power supplies. The power switches provide +5V power with current limiting and reverse-voltage protection.

The device uses a simplified power-supply interface that operates from a single +5V supply. An internal 2.5V regulator limits the voltage passed by the DDC switches to provide compatibility with low-voltage graphics controllers.

The device features two enable inputs and three monitordetection outputs. This interface signals to the graphics controller when a monitor is inserted or removed from either of the VGA ports and allows it to switch between

them. Alternatively, these signals can be connected together to automatically select the port when a monitor is plugged in. A dedicated output (MDOR) signals the graphics controller when any monitor is detected.

5V Power Switches (S5V1, S5V2)

The device provides a switched +5V output in addition to the regular VGA signals (S5V1 and S5V2). Each output can supply 55mA with less than 300mV drop from VCC. The S5V_ outputs tolerate +5V while turned off.

The power switches are protected against overcurrent and overtemperature faults. The device limits current supplied to each monitor side to 300mA (typ). Thermalprotection circuitry shuts off the switch when the temperature exceeds +150NC. The device is re-enabled once the temperature has fallen below +125NC.

Each power switch output has a 250I (typ) pulldown resistor to discharge filter capacitors when the switch is off.

RGB Switches

The device provides three single-pole/double-throw (SPDT) high-bandwidth switches to route the standard VGA R, G, and B signals (Table 1). The R, G, and B analog switches are identical, and any of the three switches can be used to route red, green, or blue video signals.

Horizontal/Vertical Sync Multiplexer

The HSYNC_/VSYNC_ signals are buffered to provide level shifting and drive capability to meet the VESA specification. HSYNC_/VSYNC_ signals are only routed to the port selected by EN2 and EN1 (Table 1). HSYNC_ and VSYNC_ are not interchangeable.

Display Data Channel Multiplexer

(SDA_, SCL_)

The device provides two voltage-limited SPDT switches to route DDC signals (SDA_, SCL_). These switches limit the voltage that can be passed through to the graphics controller to less than 2.5V. Internal pullup resistors on the monitor side of the switches translate the graphics controller signals to 5V compatible logic. Connect pullup resistors on SCL0 and SDA0 to define the logic level of the graphics controller.

The SDA_ and SCL_ switches are identical, and either of these two switches can be used to route SDA or SCL I2C signals.

�� Maxim Integrated Products 8

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Applications Information

1:2 Multiplexer for Low-Voltage

Graphics Controllers

The device provides the level shifting necessary to drive two standard VGA ports using a single graphics controller. Internal buffers drive the HSYNC_ and VSYNC_ signals to VGA standard TTL levels. The DDC multiplexer provides level shifting by limiting signal levels to less than 2.5V.

Power-Supply Decoupling

Bypass VCC to ground with a 1FF or larger ceramic capacitor as close as possible to the device.

PCB Layout

High-speed switches such as the MAX14983E require proper PCB layout for optimum performance. Ensure that impedance-controlled PCB traces for high-speed signals are matched in length and as short as possible. Connect the exposed pad to a solid ground plane.

HIGH-

VOLTAGE

DC

SOURCE

R

C

1MI

CHARGE CURRENT-

LIMIT RESISTOR

C

100pF

S

R

D

1.5kI

DISCHARGE

RESISTANCE

STORAGE CAPACITOR

DEVICE UNDER

TEST

High-ESD Protection

Electrostatic discharge (ESD)-protection structures are incorporated on all pins to protect against electrostatic discharges up to Q2kV Human Body Model (HBM) encountered during handling and assembly. All outputs are further protected against ESD up to Q15kV (HBM) without damage (see the Pin Description).

The ESD structures withstand high ESD both in normal operation and when the device is powered down. After an ESD event, the device continues to function without latchup.

ESD Test Conditions

ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test methodology and results.

Human Body Model

Figure 2 shows the Human Body Model. Figure 3 shows

the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5kI resistor.

(AMPS)

I

PEAK

100%

AMPERES

36.8%

90%

10%

0

t

RL

PEAK-TO-PEAK RINGING

I

r

(NOT DRAWN TO SCALE)

t

DL

TIME

Figure 2. Human Body ESD Test Model Figure 3. Human Body Current Waveform

�� Maxim Integrated Products 9

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX14983EETJ+

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed paddle.

-40NC to +85NC

32 TQFN-EP*

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

32 TQFN-EP T3255+4

PACKAGE

CODE

OUTLINE

NO.

21-0140 90-0012

LAND

PATTERN NO.

�� Maxim Integrated Products 10

MAX14983E

Enhanced 1:2 VGA Mux with

Monitor Detection and Priority Port Logic

Revision History

REVISION

NUMBER

0 6/11 Initial release —

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 11

©

2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

MAXIM MAX14983E Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Benefits and Features

Typical Operating Circuit

Applications

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

Figure 1. On-Loss

Typical Operating Characteristics

Pin Configuration

Pin Description

Functional Diagram

Truth Tables

Table 1. Channel Selection

Table 2. Monitor Detection

Detailed Description

5V Power Switches (S5V1, S5V2)

RGB Switches

Horizontal/Vertical Sync Multiplexer

Applications Information

Power-Supply Decoupling

PCB Layout

High-ESD Protection

ESD Test Conditions

Human Body Model

Figure 2. Human Body ESD Test Model Figure 3. Human Body Current Waveform

Ordering Information

Chip Information

Package Information

Revision History