MAXIM MAX148, MAX149 Technical data

General Description

The MAX148/MAX149 10-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from a
single +2.7V to +5.25V supply, and sample to 133ksps.
Both devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.

The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial-strobe output allows direct connection to
TMS320-family digital signal processors. The MAX148/
MAX149 use either the internal clock or an external serial­interface clock to perform successive-approximation
analog-to-digital conversions.

The MAX149 has an internal 2.5V reference, while the
MAX148 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage­adjustment range.

These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be pro­grammed to automatically shut down at the end of a con­version. Accessing the serial interface automatically
powers up the MAX148/MAX149, and the quick turn-on
time allows them to be shut down between all conver­sions. This technique can cut supply current to under
60µA at reduced sampling rates.

The MAX148/MAX149 are available in a 20-pin DIP and a
20-pin SSOP.

For 4-channel versions of these devices, see the
MAX1248/MAX1249 data sheet.

________________________Applications

Portable Data Logging Data Acquisition
Medical Instruments Battery-Powered Instruments
Pen Digitizers Process Control

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Single-Supply Operation: +2.7V to +5.25V
♦ Internal 2.5V Reference (MAX149)
♦ Low Power: 1.2mA (133ksps, 3V supply)

54µA (1ksps, 3V supply)
1µA (power-down mode)

♦ SPI/QSPI/MICROWIRE/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP/SSOP Packages

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

________________________________________________________________

Maxim Integrated Products

1

V

DD

I/O
SCK (SK)
MOSI (SO)
MISO (SI)

V

SS

SHDN

SSTRB

DOUT

DIN

SCLK

CS

COM

AGND

DGND

V

DD

CH7

4.7µF

0.1µF

CH0

0V TO

+2.5V

ANALOG

INPUTS

MAX149

CPU

+3V

VREF

0.01µF

REFADJ

__________Typical Operating Circuit

19-0464; Rev 2; 5/98

PART

†

MAX148ACPP
MAX148BCPP
MAX148ACAP 0°C to +70°C

0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

20 Plastic DIP
20 Plastic DIP
20 SSOP

EVALUATION KIT

AVAILABLE

Ordering Information

Ordering Information continued at end of data sheet.

†

Contact factory for availability of alternate surface-mount
packages.

MAX148BCAP 0°C to +70°C 20 SSOP

INL

(LSB)

±1/2
±1
±1/2
±1

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.

Pin Configuration appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone] ext. 3468.

查询MAX148ACAP供应商

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

VDD= +2.7V to +5.25V; COM = 0V; f

SCLK

= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; T

A

= T

MIN

to T

MAX

; unless

otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto AGND, DGND................................................. -0.3V to 6V

AGND to DGND...................................................... -0.3V to 0.3V

CH0–CH7, COM to AGND, DGND............ -0.3V to (V

DD

+ 0.3V)

VREF, REFADJ to AGND........................... -0.3V to (V

DD

+ 0.3V)

Digital Inputs to DGND.............................................. -0.3V to 6V

Digital Outputs to DGND........................... -0.3V to (V

DD

+ 0.3V)

Digital Output Sink Current.................................................25mA

Continuous Power Dissipation (T

A

= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW

SSOP (derate 8.00mW/°C above +70°C) ................... 640mW

CERDIP (derate 11.11mW/°C above +70°C).............. 889mW

Operating Temperature Ranges

MAX148_C_P/MAX149_C_P.............................. 0°C to +70°C

MAX148_E_P/MAX149_E_P............................ -40°C to +85°C

MAX148_MJP/MAX149_MJP........................ -55°C to +125°C

Storage Temperature Range............................ -60°C to +150°C

Lead Temperature (soldering, 10sec)............................ +300°C

µs1.5t

ACQ

Differential Nonlinearity

Track/Hold Acquisition Time

ns30Aperture Delay

6

µs

35 65

t

CONV

Conversion Time (Note 5)

5.5 7.5

ps

MHz1.0Full-Power Bandwidth

MHz2.25Small-Signal Bandwidth

dB-75Channel-to-Channel Crosstalk

dB70SFDRSpurious-Free Dynamic Range

dB-70THDTotal Harmonic Distortion

dB66SINADSignal-to-Noise + Distortion Ratio

LSB±0.05

Channel-to-Channel Offset
Matching

ppm/°C±0.25Gain Temperature Coefficient

±0.5

<50

Bits10Resolution

Gain Error (Note 3)

±1

Aperture Jitter

Offset Error

LSB

±1.0

INLRelative Accuracy (Note 2)

LSB±1DNL

±0.15 ±1

LSB

±0.15 ±2

UNITSMIN TYP MAXSYMBOLPARAMETER

External clock = 2MHz, 12 clocks/conversion

Internal clock, SHDN = V

DD

Internal clock, SHDN = FLOAT

MAX14_A

-3dB rolloff

65kHz, 2.500V

p-p

(Note 4)

Up to the 5th harmonic

MAX14_A

MAX14_B
No missing codes over temperature
MAX14_A
MAX14_B

CONDITIONS

LSB

±2MAX14_B

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)

CONVERSION RATE

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 3

Multiplexer Leakage Current

µA0.01 10Shutdown VREF Input Current

kΩ18 25VREF Input Resistance

µA100 150VREF Input Current

V

1.0

V

DD

+

50mV

VREF Input Voltage Range
(Note 9)

pF16Input Capacitance

1.8
MHz

0.225

Internal Clock Frequency

µA±0.01 ±1

UNITSMIN TYP MAXSYMBOLPARAMETER

SHDN = FLOAT

VREF = 2.500V

SHDN = V

DD

On/off leakage current, V

CH_

= 0V or V

DD

CONDITIONS

ELECTRICAL CHARACTERISTICS (continued)

VDD= +2.7V to +5.25V; COM = 0V; f

SCLK

= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; T

A

= T

MIN

to T

MAX

; unless

otherwise noted.)

V2.470 2.500 2.530VREF Output Voltage TA= +25°C (Note 7)

mA30VREF Short-Circuit Current

±30MAX149

mV0.35Load Regulation (Note 8) 0mA to 0.2mA output load

0Internal compensation mode

µF

4.7

Capacitive Bypass at VREF

External compensation mode

µF0.01Capacitive Bypass at REFADJ

%±1.5REFADJ Adjustment Range

V

VDD-

0.5

REFADJ Buffer-Disable Threshold

µF

0

Capacitive Bypass at VREF

Internal compensation mode

2.00

V/V

2.06

Reference Buffer Gain

4.7

MAX148

MAX149

External compensation mode

±10

µA

±50

REFADJ Input Current

MAX148

MAX149

ppm/°CVREF Temperature Coefficient

0 to VREF

V

±VREF / 2

Input Voltage Range, Single­Ended and Differential (Note 6)

Unipolar, COM = 0V
Bipolar, COM = VREF / 2

0.1 2.0
MHz

0 2.0

External Clock Frequency

Data transfer only

CONVERSION RATE (continued)

ANALOG/COM INPUTS

INTERNAL REFERENCE (MAX149 only, reference buffer enabled)

EXTERNAL REFERENCE AT VREF (Buffer disabled)

EXTERNAL REFERENCE AT REFADJ

I

DD

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

VDD= +2.7V to +5.25V; COM = 0V; f

SCLK

= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; T

A

= T

MIN

to T

MAX

; unless

otherwise noted.)

V

3.0

V

IH

DIN, SCLK, CS Input High Voltage

VDD> 3.6V

mV±0.3PSRSupply Rejection (Note 12)

Full-scale input, external reference = 2.500V,
VDD= 2.7V to 5.25V

pF15C

IN

DIN, SCLK, CS Input Capacitance

µA±0.01 ±1I

IN

DIN, SCLK, CS Input Leakage

V0.2V

HYST

DIN, SCLK, CS Input Hysteresis

V0.8V

IL

DIN, SCLK, CS Input Low Voltage

2.0

µA±4.0I

S

SHDN Input Current

V0.4V

SL

SHDN Input Low Voltage

VVDD- 0.4V

SH

SHDN Input High Voltage

SHDN = 0V or V

DD

nA±100

SHDN Maximum Allowed
Leakage, Mid Input

VV

DD

/ 2V

FLT

SHDN Voltage, Floating

SHDN = FLOAT

SHDN = FLOAT

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 10)

VIN= 0V or V

DD

V

DD

≤ 3.6V

CONDITIONS

µA±0.01 ±10I

L

Three-State Leakage Current

VVDD- 0.5V

OH

Output Voltage High

V

0.8

V

OL

Output Voltage Low

0.4

pF15C

OUT

Three-State Output Capacitance

CS = VDD(Note 10)

CS = V

DD

I

SOURCE

= 0.5mA

I

SINK

= 16mA

I

SINK

= 5mA

2.70 5.25

1.2 2.0

Operating mode,
full-scale input (Note 11)

3.5 15

Full power-down

1.2 10

mA

1.6 3.0

V1.1 VDD- 1.1V

SM

SHDN Input Mid Voltage

Positive Supply Current

V

DD

Positive Supply Voltage V

I

DD

µA

30 70

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER REQUIREMENTS

Fast power-down (MAX149)I

DD

VDD= 5.25V
VDD= 3.6V
VDD= 5.25V
VDD= 3.6V

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 5

Figure 1

__________________________________________Typical Operating Characteristics

(VDD= 3.0V, VREF = 2.500V, f

SCLK

= 2.0MHz, C

LOAD

= 20pF, TA = +25°C, unless otherwise noted.)

0 256 512 768 1024

INTEGRAL NONLINEARITY

vs. CODE

0.10

0.05

-0.10

-0.05

0

MAX148/9-01

CODE

INL (LSB)

0.125

0

2.25 2.75 4.25

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.100

0.075

0.050

0.025

SUPPLY VOLTAGE (V)

INL (LSB)

3.75 5.253.25 4.75

MAX148/9-02

MAX149

MAX148

0

0.025

0.050

0.075

0.100

0.125

-60 -20 20 60 100 140

INTEGRAL NONLINEARITY

vs. TEMPERATURE

TEMPERATURE (°C)

INL (LSB)

MAX148/9-03

MAX148

MAX149

VDD = 2.7V

TIMING CHARACTERISTICS

(VDD= +2.7V to +5.25V, TA= T

MIN

to T

MAX

, unless otherwise noted.)

Note 1: Tested at V

DD

= 2.7V; COM = 0V; unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V

DD

.

Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note

10:

Guaranteed by design. Not subject to production testing.

Note

11:

The MAX148 typically draws 400µA less than the values shown.

Note

12:

Measured as |VFS(2.7V) - VFS(5.25V)|.

Internal clock mode only (Note 7)

External clock mode only, Figure 2

External clock mode only, Figure 1

DIN to SCLK Setup

Figure 1

Figure 2

Figure 1

MAX14_ _C/E

CONDITIONS

MAX14_ _M

ns

20 240

Figure 1

ns

t

CSH

ns240t

STR

CS Rise to SSTRB Output Disable

ns240t

SDV

CS Fall to SSTRB Output Enable

240t

SSTRB

SCLK Fall to SSTRB ns

200t

CL

SCLK Pulse Width Low

ns200SCLK Pulse Width High

ns0

CS to SCLK Rise Hold

ns100t

CSS

CS to SCLK Rise Setup

ns240t

TR

CS Rise to Output Disable

ns240t

DV

CS Fall to Output Enable

t

CH

20 200

t

DO

SCLK Fall to Output Data Valid

ns0t

DH

DIN to SCLK Hold

ns

µs1.5t

ACQ

Acquisition Time

0t

SCK

SSTRB Rise to SCLK Rise

ns100t

DS

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs

6 _______________________________________________________________________________________

2.00

0.50

2.25 2.75

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

1.75

1.25

1.50

1.00

0.75

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.75 5.253.25 4.25 4.75

MAX148/9-04

RL = ∞
CODE = 1010101000

C

LOAD

= 50pF

MAX148

MAX149

C

LOAD

= 20pF

0

2.25 2.75

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

3.0

2.5

1.5

2.0

1.0

0.5

SUPPLY VOLTAGE

(V)

SHUTDOWN SUPPLY CURRENT (µA)

3.75 5.253.25 4.25 4.75

MAX148/9-05

FULL POWER-DOWN

2.5020

2.4990

2.25 2.75

MAX149

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

2.5015

2.5005

2.5010

2.5000

2.4995

SUPPLY VOLTAGE

(V)

INTERNAL REFERENCE VOLTAGE (V)

3.75 5.253.25 4.25 4.75

MAX148/9-06

0.8

0.9

1.0

1.1

1.2

1.3

-60 -20 20 60 100 140

SUPPLY CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX148/9-07

MAX148

MAX149

R

LOAD

= ∞

CODE = 1010101000

0

0.4

0.8

1.2

1.6

2.0

-60 -20 20 60 100 140

SHUTDOWN CURRENT

vs. TEMPERATURE

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

MAX148/9-08

2.494

2.495

2.496

2.497

2.498

2.499

2.500

2.501

-60 -20 20 60 100 140

MAX149

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

MAX148/9-09

VDD = 2.7V

VDD = 3.6V

VDD = 5.25V

____________________________Typical Operating Characteristics (continued)

(VDD= 3.0V, VREF = 2.500V, f

SCLK

= 2.0MHz, C

LOAD

= 20pF, TA = +25°C, unless otherwise noted.)

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 7

______________________________________________________________Pin Description

V

DD

6k

DGND

DOUT

C

LOAD

50pF

C

LOAD

50pF

DGND

6k

DOUT

a) High-Z to V

OH

and VOL to V

OH

b) High-Z to VOL and VOH to V

OL

Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.REFADJ12

Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).

SSTRB16

Serial-Data Input. Data is clocked in at SCLK’s rising edge.DIN17
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

CS

18

Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)

SCLK19

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.

VREF11

Analog GroundAGND13
Digital GroundDGND14
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

DOUT15

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are
fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.
Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

SHDN

10

Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.

COM9

PIN

Sampling Analog InputsCH0–CH71–8

FUNCTIONNAME

Positive Supply VoltageV

DD

20

DOUT

C

LOAD

50pF

6k

DGND

a) V

to High-Z b) VOL to High-Z

OH

DOUT

V

DD

6k

C

LOAD

50pF
DGND

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs

8 _______________________________________________________________________________________

_______________Detailed Description

The MAX148/MAX149 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible seri­al interface provides easy interface to microprocessors
(µ Ps). Figure 3 is a block diagram of the MAX148/
MAX149.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com­parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol­lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.

In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN- (the selected analog input) to AGND.

During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor C

HOLD

.
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the

acquisition interval, the T/H switch opens, retaining
charge on C

HOLD

as a sample of the signal at IN+.

The conversion interval begins with the input multiplexer
switching C

HOLD

from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 10-bit resolution. This action is equiv­alent to transferring a 16pF x [(V

IN

+

) - (VIN-)] charge

from C

HOLD

to the binary-weighted capacitive DAC,
which in turn forms a digital representation of the analog
input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif­ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-

| is sampled. At the end of the

conversion, the positive input connects back to IN+,
and C

HOLD

charges to the input signal.

The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be

INPUT
SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

OUTPUT

SHIFT

REGISTER

+1.21V

REFERENCE

(MAX149)

T/H

ANALOG

INPUT

MUX

10+2-BIT

SAR
ADC

IN

DOUT
SSTRB

V

DD

DGND
AGND

SCLK

DIN

COM

REFADJ

VREF

OUT

REF

CLOCK

+2.500V

20k

*A ≈ 2.00 (MAX148)

10

11

12

9

15
16

17

18
19

CH6

7

CH4

5

CH2

3

CH0

1

CH7

8

CH5

6

CH3

4

CH1

2

MAX148
MAX149

CS

SHDN

20
14

13

≈ 2.06*

A

Figure 3. Block Diagram

CH0

CH2

CH4

CH6

CH1

CH3

CH5

CH7

COM

C

SWITCH

TRACK

T/H

SWITCH

R

IN

9k

C

HOLD

HOLD

CAPACITIVE DAC

VREF

ZERO

COMPARATOR

–

+

16pF

SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit