MAXIM MAX14830 Technical data

19-5547; Rev 2; 9/11

EVALUATION KIT

AVAILABLE

Quad Serial UART with 128-Word FIFOs

General Description

The MAX14830 is an advanced quad universal asynchronous receiver-transmitter (UART), each UART having 128 words of receive and transmit first-in/first-out (FIFO) and a high-speed serial peripheral interface (SPIK) or I baud-rate generators allow a high degree of flexibility in baud-rate programming and reference clock selection.

Each of the four UARTs is selected by in-band SPI/I addressing. Logic-level translation on the transceiver and controller interfaces allows ease of interfacing to microcontrollers, FPGAs, and transceivers that are powered by differing supply voltages.

Extensive features simplify transceiver control in halfduplex communication applications. The MAX14830 features the ability to synchronize the start of individual UART’s transmission by SPI-based triggering. On-board timers allow programming of delays between transmitters as well as clock generation on GPIOs.

The 128-word FIFOs have advanced FIFO control reducing host processor data flow management.

The MAX14830 is available in a 48-pin TQFN (7mm x 7mm) package and is specified to operate over the extended -40NC to +85NC temperature range.

Applications

C controller interface. A PLL and fractional

Industrial Control Systems

Programmable Logic Controllers (PLC)

IO-Link Master Controllers

Automotive Infotainment Systems

Medical Systems

Point-of-Sales Systems

Airplane Communication Buses

Features

S SPI Up to 26MHz Clock Rate

S Fast-Mode Plus (Fm+) I

S 128-Word Transmit and Receive FIFOs Per UART

S 6Mbaud (max) Data Rate in 16x Sampling Mode

S 12/24Mbaud (max) Data Rate in 2x/4x Rate Modes

S Fractional Baud-Rate Generators, Predivider, and

C Interface Up to 1MHz

Phase-Locked Loop (PLL)

S Transmitter Synchronization Through SPI

Commands

S Four Timers Routed to GPIOs S Automatic Hardware Flow Control Using RTS_

and CTS_ Outputs and Inputs

S Automatic Software Flow Control (XON/XOFF)

S Auto Transceiver Direction Control

S Programmable Setup and Hold Times for

Transceiver Control

S Auto Transmitter Disable

S Half-Duplex Echo Suppression

S Special Character Detection

S 9-Bit Multidrop Mode Address Detection and

Filtering

S SIR- and MIR-Compliant IrDA

S 16 Flexible GPIOs with 20mA Drive Capability

S +2.35V to +3.6V Supply Range

S Logic-Level Translation Down to 1.61V on

Encoder/Decoders

Controller and Transceiver Interfaces

S Small TQFN (7mm x 7mm) Package

Ordering Information

MAX14830

PART TEMP RANGE PIN-PACKAGE

Typical Operating Circuits appear at end of data sheet.

SPI is a trademark of Motorola, Inc. IrDA is a registered service mark of Infrared Data Association

Corporation.

_______________________________________________________________ Maxim Integrated Products 1

MAX14830ETM+

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.

-40NC to +85NC

48 TQFN-EP*

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Quad Serial UART with 128-Word FIFOs

General Description ............................................................................ 1

Applications .................................................................................. 1

Features ..................................................................................... 1

Ordering Information ........................................................................... 1

Functional Diagram ............................................................................ 7

Absolute Maximum Ratings ...................................................................... 8

MAX14830

Package Thermal Characteristics.................................................................. 8

DC Electrical Characteristics ..................................................................... 8

AC Electrical Characteristics .................................................................... 10

Test Circuits/Timing Diagrams ................................................................... 13

Typical Operating Characteristics ................................................................ 14

Pin Configuration ............................................................................. 15

Pin Description ............................................................................... 15

Detailed Description........................................................................... 18

Receive and Transmit FIFOs...................................................................18

Transmitter Operation ........................................................................18

Receiver Operation ..........................................................................19

Line Noise Indication.........................................................................20

Clocking and Baud-Rate Generation ............................................................20

Crystal Oscillator .........................................................................20

External Clock Source .....................................................................20

PLL and Predivider ..........................................................................20

Fractional Baud-Rate Generators ...............................................................21

2x and 4x Rate Modes .......................................................................21

Low-Frequency Timer ........................................................................22

UART Clock to GPIO.........................................................................22

Multidrop Mode .............................................................................22

Auto Data Filtering in Multidrop Mode .........................................................22

Auto Transceiver Direction Control ..............................................................22

Transmitter Triggering and Synchronization .......................................................23

Transmitter Synchronization .................................................................23

Intrachip and Interchip Synchronization........................................................23

Delayed Triggering........................................................................23

Trigger Accuracy .........................................................................24

Synchronization Accuracy ..................................................................24

Auto Transmitter Disable ......................................................................24

Echo Suppression ...........................................................................24

Auto Hardware Flow Control ...................................................................26

Quad Serial UART with 128-Word FIFOs

TABLE OF CONTENTS (continued)

AutoRTS Control..........................................................................26

AutoCTS Control..........................................................................26

FIFO Interrupt Triggering......................................................................26

Auto Software (XON/XOFF) Flow Control .........................................................26

Transmitter Flow Control....................................................................27

Receiver Overflow Control ..................................................................27

Power-Up and IRQ ..........................................................................27

Shutdown Mode ............................................................................27

Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt Enabling.........................................................................28

Interrupt Clearing .........................................................................28

Detailed Register Description ..................................................................30

Serial Controller Interface....................................................................... 58

SPI Interface ...............................................................................58

MISO Operation ..........................................................................58

SPI Burst Access .........................................................................58

Fast Read Cycle..........................................................................59

I2C Interface ...............................................................................59

START, STOP, and Repeated START Conditions.................................................59

Slave Address ...........................................................................60

Bit Transfer ..............................................................................61

Single-Byte Write .........................................................................61

Burst Write ..............................................................................61

Single-Byte Read .........................................................................62

Burst Read ..............................................................................62

Acknowledge Bits ........................................................................63

Applications Information ........................................................................63

Startup and Initialization ......................................................................63

Low-Power Operation ........................................................................63

Interrupts and Polling ........................................................................63

Logic-Level Translation .......................................................................63

IO-Link Application ..........................................................................63

Typical Operating Circuit .......................................................................65

Chip Information .............................................................................. 67

Package Information........................................................................... 67

Revision History ..............................................................................68

MAX14830

Quad Serial UART with 128-Word FIFOs

LIST OF FIGURES

Figure 1. I2C Timing Diagram.................................................................... 13

Figure 2. SPI Timing Diagram ................................................................... 13

Figure 3. Transmit FIFO Signals .................................................................. 18

Figure 4. Receive Data Format................................................................... 19

Figure 5. Receive FIFO ........................................................................ 19

Figure 6. Midbit Sampling ...................................................................... 19

MAX14830

Figure 7. Clock Selection Diagram................................................................ 20

Figure 8. 2x and 4x Baud Rates.................................................................. 21

Figure 9. GPIO_ Clock Pulse Generator............................................................ 22

Figure 10. Auto Transceiver Direction Control .......................................................23

Figure 11. Setup and Hold times in Auto Transceiver Direction Control ...................................23

Figure 12. Single Transmitter Trigger Accuracy ...................................................... 24

Figure 13. Multiple Transmitter Synchronization Accuracy.............................................. 25

Figure 14. Echo Suppression Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15. Half-Duplex with Echo Suppression ...................................................... 26

Figure 16. Simplified Interrupt Structure............................................................ 27

Figure 17. PLL Signal Path ...................................................................... 51

Figure 18. SPI Write Cycle ......................................................................58

Figure 19. SPI Read Cycle ...................................................................... 59

Figure 20. SPI Fast Read Cycle .................................................................. 59

Figure 21. I2C START, STOP, and Repeated START Conditions ......................................... 60

Figure 22. Write Byte Sequence.................................................................. 61

Figure 23. Burst Write Sequence ................................................................. 61

Figure 24. Read Byte Sequence ................................................................. 62

Figure 25. Burst Read Sequence................................................................. 62

Figure 26. Acknowledge Bits .................................................................... 63

Figure 27. Startup and Initialization Flow Chart ......................................................63

Figure 28. Logic-Level Translation ................................................................ 64

Figure 29. Interchip Synchronization .............................................................. 64

Quad Serial UART with 128-Word FIFOs

LIST OF TABLES

Table 1. UART GPIO Assignments for GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 2. StopBits Truth Table .................................................................... 41

Table 3. Length_ Truth Table .................................................................... 41

Table 4. SwFlow_ Truth Table....................................................................46

Table 5. UART GPIO Assignments for GPIO Configuration ............................................. 49

Table 6. UART GPIO Assignments for GPIO Input/Output Data ......................................... 50

Table 7. PLLFactor_ Selector Guide ............................................................... 51

Table 8. GloblComnd Command Descriptions ...................................................... 54

Table 9. Extended Mode Addressing (SPI only) .....................................................54

Table 10. SPI Command Byte Configuration ........................................................58

Table 11. SPI U1, U0 UART Selection ............................................................. 58

Table 12. I2C Address Map ..................................................................... 60

MAX14830

Quad Serial UART with 128-Word FIFOs

LIST OF REGISTERS

RHR—Receive Hold Register ................................................................... 30

THR—Transmit Hold Register ................................................................... 30

IRQEn—IRQ Enable Register.................................................................... 31

ISR—Interrupt Status Register ................................................................... 32

LSRIntEn—Line Status Interrupt Enable Register .................................................... 33

LSR—Line Status Register...................................................................... 34

MAX14830

SpclChrIntEn—Special Character Interrupt Enable Register............................................ 35

SpclCharInt—Special Character Interrupt Register ................................................... 36

STSIntEn—STS Interrupt Enable Register .......................................................... 37

STSInt—Status Interrupt Register................................................................. 38

MODE1 Register.............................................................................. 39

MODE2 Register .............................................................................40

LCR—Line Control Register ..................................................................... 41

RxTimeOut—Receiver Timeout Register ...........................................................42

HDplxDelay Register ..........................................................................42

IrDA Register ................................................................................ 43

FlowLvl—Flow Level Register.................................................................... 44

FIFOTrigLvl—FIFO Interrupt Trigger Level Register ................................................... 44

TxFIFOLvl—Transmit FIFO Level Register ..........................................................45

RxFIFOLvl—Receive FIFO Level Register ..........................................................45

FlowCtrl—Flow Control Register .................................................................45

XON1 Register ............................................................................... 47

XON2 Register ............................................................................... 47

XOFF1 Register ..............................................................................48

XOFF2 Register .............................................................................. 48

GPIOConfg—GPIO Configuration Register ......................................................... 49

GPIOData—GPIO Data Register ................................................................. 50

PLLConfig—PLL Configuration Register ........................................................... 51

BRGConfig—Baud-Rate Generator Configuration Register ............................................ 52

DIVLSB—Baud-Rate Generator LSB Divisor Register................................................. 52

DIVMSB—Baud-Rate Generator MSB Divisor Register................................................ 52

CLKSource—Clock Source Register .............................................................. 53

GlobalIRQ—Global IRQ Register................................................................. 53

GloblComnd—Global Command Register.......................................................... 54

TxSynch—Transmitter Synchronization Register ..................................................... 55

SynchDelay1—Synchronization Delay Register 1 ....................................................56

SynchDelay2—Synchronization Delay Register 2 ....................................................56

TIMER1—Timer Register 1......................................................................56

TIMER2—Timer Register 2......................................................................57

RevID—Revision Identification Register............................................................ 57

Quad Serial UART with 128-Word FIFOs

Functional Diagram

MAX14830

LDOEN

SPI/I2C

MOSI/A1

MISO/SDA

CS/A0

SCLK/SCL

RST

IRQ

XIN

XOUT

LOGIC-LEVEL

TRANSLATION

CRYSTAL

OSCILLATOR

SPI AND

INTERFACE

MAX14830

LDO

I2C

EXT

TX0

RX0

CTS0

RTS0

GPIO0

GPIO3

TX1

RX1

CTS1

LOGIC-LEVEL TRANSLATION

RTS1

GPIO4

GPIO7

TX2

RX2

CTS2

RTS2

GPIO8

GPIO11

TX3

RX3

CTS3

RTS3

GPIO12

GPIO15

PLLDIVIDER

REGISTERS

AND

CONTROL

TRANSMITTER

SYNC

FRACTIONAL

BAUD-RATE

GENERATOR

UARTO

UART1

UART2

UART3

DGNDAGND

Quad Serial UART with 128-Word FIFOs

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to AGND.) VL, VA, V

V18, XOUT ........... -0.3V to the lesser of (VA + 0.3V) and +2.0V

RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL,

MISO/SDA, LDOEN, SPI/I2C .................. -0.3V to (VL + 0.3V)

TX0, RX0, CTS0, GPIO0, GPIO1,

GPIO2, GPIO3 ..................................... -0.3V to (V

TX1, RX1, CTS1, GPIO4, GPIO5,

GPIO6, GPIO7 ..................................... -0.3V to (V

MAX14830

TX2, RX2, CTS2, GPIO8, GPIO9,

GPIO10, GPIO11 ................................. -0.3V to (V

, XIN ................................................ -0.3V to +4.0V

EXT

+ 0.3V)

TX3, RX3, CTS3, GPIO12, GPIO13,

GPIO14, GPIO15 ................................. -0.3V to (V

DGND .................................................................. -0.3V to +0.3V

Continuous Power Dissipation (TA = +70NC)

TQFN (derate 38.5mW/NC above +70NC).....3076.9mW

Operating Temperature Range ........................ -40NC to +85NC

Maximum Junction Temperature ................................. +150NC

Storage Temperature Range ......................... -65NC to +150NC

Lead Temperature (soldering, 10s) ..................................300NC

Soldering Temperature (reflow) .....................................+260NC

EXT

+ 0.3V)

PACKAGE THERMAL CHARACTERISTICS

TQFN

Junction-to-Ambient Thermal Resistance (BJA) ...........26NC/W

Junction-to-Case Thermal Resistance (BJC) ..................1NC/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(Note 1)

DC ELECTRICAL CHARACTERISTICS

(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V are at VA = +2.5V, VL = +1.8V, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Digital Interface Supply Voltage V Analog Supply Voltage V

UART Interface Logic Supply Voltage

Logic Supply Voltage V

CURRENT CONSUMPTION

VA Supply Current I

VA Shutdown Supply Current I

VL Shutdown or Sleep Supply Current

Shutdown Supply Current I

EXT

= +2.8V, TA = +25NC.) (Notes 2, 3)

EXT

ASHDN

EXT

= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values

EXT

1.71 3.6 V

2.35 3.6 V

1.71 3.6 V

1.65 1.95 V

1.8MHz crystal oscillator active, PLL disabled, SPI/I2C interface idle, UART interfaces idle, V

Baud rate = 1Mbps, 20MHz external clock, SPI/I2C interface idle, PLL disabled, all UARTs in loopback mode, V

Shutdown mode, V all inputs and outputs are idle

LDOEN

= V

LDOEN

= 0V, V

= 0V

RST

= 0V,

400

0.5 mA

Quad Serial UART with 128-Word FIFOs

DC ELECTRICAL CHARACTERISTICS (continued)

(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V are at VA = +2.5V, VL = +1.8V, V

= +2.8V, TA = +25NC.) (Notes 2, 3)

EXT

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V18 Input Power-Supply Current in Shutdown Mode

V18 Input Power-Supply Current I

18SHDN

SCLK/SCL, MISO/SDA

MISO/SDA Output Low Voltage in I2C Mode

MISO/SDA Output Low Voltage in SPI Mode

MISO/SDA Output High Voltage in SPI Mode

Input Low Voltage V Input High Voltage V Input Hysteresis V Input Leakage Current I Input Capacitance C

OL,I2C

OL,SPIILOAD

OH,SPIILOAD

HYST

SPI/I2C, CS/A0, MOSI/A1 INPUTS

Input Low Voltage V Input High Voltage V Input Hysteresis V Input Leakage Current I Input Capacitance C

HYST

IRQ OUTPUT (OPEN DRAIN)

Output Low Voltage V Output Leakage Current I

LDOEN AND RST INPUTS

Input Low Voltage V Input High Voltage V Input Hysteresis V Input Leakage Current I

HYST

UART INTERFACE RTS0, RTS1, RTS2, RTS3, TX0, TX1, TX2, TX3 OUTPUTS

Output Low Voltage V Output High Voltage V Input Leakage Current I Input Capacitance C

= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values

EXT

Shutdown mode, V

LDOEN

all inputs and outputs are idle

Baud rate = 1Mbps, 20MHz external clock, PLL disabled, all UARTs in loopback mode, V

I I

= 0V (Note 4)

LDOEN

= -3mA, VL > 2V 0.4

LOAD

= -3mA, VL < 2V 0.2 x V

LOAD

= -2mA 0.4 V

= 2mA

SPI and I2C mode 0.3 x V SPI and I2C mode 0.7 x V SPI and I2C mode 0.05 x V V

= 0 to VL, SPI and I2C mode -1 +1

SPI and I2C mode 5 pF

SPI and I2C mode 0.3 x V SPI and I2C mode 0.7 x V SPI and I2C mode 50 mV V

= 0 to VL, SPI and I2C mode -1 +1

SPI and I2C mode 5 pF

= -2mA 0.4 V

LOAD

= 0 to VL, IRQ is not asserted

IRQ

= 0 to V

LOAD

= -2mA 0.4 V

= 2mA V Output is three-stated, V High-Z mode 5 pF

= 0V, V

RTS_

RST

= 0 to V

= 0V,

EXT

-1 +1

0.3 x V

0.7 x V

50 mV

-1 +1

- 0.4 V

EXT

-1 +1

200

5 mA

VL -

0.4

MAX14830

V V V

V V

Quad Serial UART with 128-Word FIFOs

DC ELECTRICAL CHARACTERISTICS (continued)

(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V are at VA = +2.5V, VL = +1.8V, V

= +2.8V, TA = +25NC.) (Notes 2, 3)

EXT

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RX0, RX1, RX2, RX3, CTS0, CTS1, CTS2, CTS3 INPUTS

Input Low Voltage V Input High Voltage V Input Hysteresis V

MAX14830

CTS0, CTS1, CTS2, CTS3 Input Leakage Current

RX0, RX1, RX2, RX3 Pullup Current

Input Capacitance C

HYST

IN_CTS

IN_RX_VRX_

IN_UART

GPIO0–GPIO15 INPUTS/OUTPUTS

Output Low Voltage V

Output High Voltage V Input Low Voltage V Input High Voltage V Pulldown Current I

XIN

Input Low Voltage V Input High Voltage V Input Capacitance C

XIN

XOUT

Input Capacitance C

XOUT

= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values

EXT

0.7 x V

CTS_

= 0 to V

EXT

-1 +1

= 0V -7.5 -5.5 -3.5

LOAD

= -20mA, V

> 2.3V, push-pull or

EXT

open drain

LOAD

= -20mA, V

< 2.3V, push-pull or

EXT

open drain

= 5mA, push-pull V

LOAD

GPIO_ is configured as an input 0.4 V GPIO_ is configured as an input 2/3 x V GPIO_ = V

EXT

3.5 5.5 7.5

1.2 V

0.3 x V

EXT

50 mV

5 pF

0.45

0.55

EXT

0.2 V

16 pF

EXT

- 0.4 V

V V

AC ELECTRICAL CHARACTERISTICS

(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V are at VA = +2.8V, VL = +1.8V, V

= +2.5V, TA = +25NC.) (Notes 2, 3)

EXT

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INTERNAL OSCILLATOR

External Crystal Frequency f External Clock Frequency f

XOSC

CLK

External Clock Duty Cycle (Note 5) 45 55 %

Baud-Rate Generator Clock Input

REF

= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values

EXT

1 4 MHz

0.5 35 MHz

(Note 5) 96 MHz

Quad Serial UART with 128-Word FIFOs

AC ELECTRICAL CHARACTERISTICS (continued)

(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V are at VA = +2.8V, VL = +1.8V, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I2C BUS: TIMING CHARACTERISTICS (SEE FIGURE 1)

SCL Clock Frequency f

Bus Free Time Between a STOP and START Condition

Hold Time for START Condition and Repeated START Condition

Low Period of the SCL Clock t

High Period of the SCL Clock t

Data Hold Time t

Data Setup Time t

Setup Time for Repeated START Condition

Rise Time of SDA and SCL Signals Receiving

Fall Time of SDA and SCL Signals

Setup Time for STOP Condition t

Capacitive Load for SDA and SCL (Note 4)

= +2.5V, TA = +25NC.) (Notes 2, 3)

EXT

SCL

BUF

HD:STA

LOW

HIGH

HD:DAT

SU:DAT

SU:STA

SU:STO

= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values

EXT

Standard mode 100

Fast mode plus 1000 Standard mode 4.7 Fast mode 1.3 Fast mode plus 0.5 Standard mode 4.0 Fast mode 0.6 Fast mode plus 0.26 Standard mode 4.7 Fast mode 1.3 Fast mode plus 0.5 Standard mode 4.0 Fast mode 0.6 Fast mode plus 0.26 Standard mode 0 0.9 Fast mode 0 0.9 Fast mode plus 0 Standard mode 250

Fast mode plus 50 Standard mode 4.7 Fast mode 0.6 Fast mode plus 0.26

Standard mode (0.3 x VL to 0.7 x VL) (Note 6)

Fast mode (0.3 x VL to 0.7 x VL) (Note 6)

Fast mode plus 120

Standard mode (0.7 x VL to 0.3 x VL) (Note 6)

Fast mode (0.7 x VL to 0.3 x VL) (Note 6)

Fast mode plus 120 Standard mode 4.7 Fast mode 0.6 Fast mode plus 0.26 Standard mode 400

Fast mode plus 550

20 +

0.1C

20 +

0.1C

20 +

0.1C

20 +

0.1C

MAX14830

kHzFast mode 400

nsFast mode 100

1000

300

pFFast mode 400

Quad Serial UART with 128-Word FIFOs

AC ELECTRICAL CHARACTERISTICS (continued)

(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V are at VA = +2.8V, VL = +1.8V, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCL and SDA I/O Capacitance C

Pulse Width of Spike Suppressed

SPI BUS: TIMING CHARACTERISTICS (SEE FIGURE 2)

MAX14830

SCLK Clock Period t SCLK Pulse Width High t SCLK Pulse Width Low t CS Fall to SCLK Rise Time MOSI Hold Time t MOSI Setup Time t Output Data Propagation Delay t MISO Rise and Fall Times t CS Hold Time

Note 2: All devices are production tested at TA = +25NC. Specifications over temperature are guaranteed by design. Note 3: Currents entering the IC are negative, and currents exiting the IC are positive. Note 4: When V18 is powered by an external voltage regulator, the external power supply must have current capability above or

equal to I18.

Note 5: Not production tested. Guaranteed by design. Note 6: Cb is the total capacitance of either the clock or data line of the synchronous bus in pF.

= +2.5V, TA = +25NC.) (Notes 2, 3)

EXT

I/O

CH+CL

CSS

CSH

= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values

EXT

(Note 5) 10 pF

50 ns

38.4 ns 16 ns 16 ns

0 ns 3 ns 5 ns

20 ns 10 ns

30 ns

Quad Serial UART with 128-Word FIFOs

Test Circuits/Timing Diagrams

MAX14830

START CONDITION

(S)

SDA

HD:STA

SCL

Figure 1. I2C Timing Diagram

SCLK

CSS

HD:DAT

SU:DAT

HIGH

REPEATED START CONDITION

SU:STA

(Sr)

HD:STA

LOW

SU:STO

STOP CONDITION

CSH

(P)

BUF

START CONDITION

(S)

MOSI

MISO

Figure 2. SPI Timing Diagram

Quad Serial UART with 128-Word FIFOs

Typical Operating Characteristics

= +25°C, unless otherwise noted.)

GPIO_ OUTPUT HIGH VOLTAGE

vs. SOURCE CURRENT (PUSH-PULL)

MAX14830

(mA)

SOURCE

EXT

= 1.8V

EXT

= 2.5V

VOH (V)

GPIO_ OUTPUT LOW VOLTAGE

vs. SINK CURRENT (PUSH-PULL)

160

= 3.3V

EXT

321

MAX14830 toc01

TRANSMITTER SYNCHRONIZATION

200µs/div

MAX14830 toc03

140

120

100

(mA)

SINK

TX0 2V/div

138.46kbaud

TX1 2V/div

19.23kbaud

TX2 2V/div

9.615kbaud

TX3 2V/div

6.41kbaud

EXT

VOL (V)

= 1.8V

= 3.3V

EXT

= 2.5V

EXT

321

MAX14830 toc02

Quad Serial UART with 128-Word FIFOs

Pin Configuration

MAX14830

TOP VIEW

GPIO14

GPIO15

RTS3

CTS3

RX3

TX3

EXT

XOUT

XIN

AGND

*CONNECT EP TO AGND.

GPIO12

GPIO13

34 33 32 31 30 29 28 27

TX2

RX2

CTS2

MAX14830

345 678910

SPI/I2C

LDOEN

SCLK/SCL

MISO/SDA

CS/A0

(7mm

RTS2

MOSI/A1

TQFN

GPIO11

IRQ

7mm)

GPIO10

RST

GPIO9

*EP

GPIO8

DGND

TX1

GPIO0

RX1

GPIO1

CTS1

RTS1

GPIO7

GPIO6

GPIO5

GPIO4

TX0

RX0

CTS0

RTS0

GPIO3

GPIO2

Pin Description

PIN NAME FUNCTION

2 LDOEN

3 MISO/SDA

4 SCLK/SCL

6 MOSI/A1

SPI/I2C SPI or Active-Low I2C Selector Input. Drive SPI/I2C high to enable SPI. Drive SPI/I2C low to enable I2C.

LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN low to disable the internal LDO. When LDOEN is low, V

can be supplied by an external voltage source.

Serial-Data Output. When SPI/I2C is high, MISO/SDA functions as the MISO, SPI serial-data output. When SPI/I2C is low, MISO/SDA functions as the SDA, I2C serial-data input/output.

Serial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK, SPI serial-clock input (up to 26MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I2C serial-clock input (up to 1MHz).

Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI

CS/A0

active-low chip-select input. When SPI/I2C is low, CS/A0 functions as the A0, I2C device address programming input. Connect CS/A0 to SDA, SCL, DGND, or VL when SPI/I2C is low.

Serial-Data and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the MOSI, SPI serialdata input. When SPI/I2C is low, MOSI/A1 functions as the A1, I2C device address programming input. Connect MOSI/A1 to SDA, SCL, DGND, or VL when SPI/I2C is low.

IRQ Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending.

RST

Active-Low Reset Input. Drive RST low to force all of the UARTs into hardware reset mode. In hardware reset mode, the oscillator and the internal PLL are shut down and there is no clock activity.

Quad Serial UART with 128-Word FIFOs

Pin Description (continued)

PIN NAME FUNCTION

Digital Interface Logic-Level Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/

9 V

10 DGND Digital Ground

MAX14830

11 GPIO0

12 GPIO1

13 GPIO2

14 GPIO3

16 17 RX0 Serial Receiving Data Input for UART0. RX0 has a weak pullup to V 18 TX0 Serial Transmitting Data Output for UART0

19 GPIO4

RTS0

CTS0 Active-Low Clear-to-Send Input for UART0. CTS0 is a flow control status input.

A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to

DGND.

General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO0 has a weak pulldown resistor to ground. GPIO0 is the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO section for more information).

General-Purpose Input/Output 1. GPIO1 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO1 has a weak pulldown resistor to ground. GPIO1 is the TIMER output when bit 7 of the TIMER2 register is set to 1.

General-Purpose Input/Output 2. GPIO2 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO2 has a weak pulldown resistor to ground.

General-Purpose Input/Output 3. GPIO3 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO3 has a weak pulldown resistor to ground.

Active-Low Request-to-Send Output for UART0. RTS0 can be set high or low by programming the LCR register. RTS0 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is set to 1.

EXT

General-Purpose Input/Output 4. GPIO4 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO4 has a weak pulldown resistor to ground. GPIO4 is the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO section for more information).

General-Purpose Input/Output 5. GPIO5 is user-programmable as an input or output (push-pull or open

20 GPIO5

21 GPIO6

22 GPIO7

24 25 RX1 Serial Receiving Data Input for UART1. RX1 has a weak pullup to V 26 TX1 Serial Transmitting Data Output for UART1

27 GPIO8

RTS1

CTS1 Active-Low Clear-to-Send Input for UART1. CTS1 is a flow control status input.

drain) or external event interrupt source. GPIO5 has a weak pulldown resistor to ground. GPIO5 is the TIMER output when bit 7 of the TIMER2 register is set to 1.

General-Purpose Input/Output 6. GPIO6 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO6 has a weak pulldown resistor to ground.

General-Purpose Input/Output 7. GPIO7 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO7 has a weak pulldown resistor to ground.

Active-Low Request-to-Send Output for UART1. RTS1 can be set high or low by programming the LCR register. RTS1 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is set to 1.

General-Purpose Input/Output 8. GPIO8 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO8 has a weak pulldown resistor to ground. GPIO8 is the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO section for more information).

EXT

Quad Serial UART with 128-Word FIFOs

Pin Description (continued)

PIN NAME FUNCTION

General-Purpose Input/Output 9. GPIO9 is user-programmable as an input or output (push-pull or open

28 GPIO9

29 GPIO10

30 GPIO11

32 33 RX2 Serial Receiving Data Input for UART2. RX2 has a weak pullup to V 34 TX2 Serial Transmitting Data Output for UART2

35 GPIO12

36 GPIO13

37 GPIO14

38 GPIO15

40 41 RX3 Serial Receiving Data Input for UART3. RX3 has a weak pullup to V 42 TX3 Serial Transmitting Data Output for UART3

43 V

44 XOUT

45 XIN

46 AGND Analog Ground

47 V

48 V

— EP Exposed Paddle. Connect EP to AGND. Do not use EP as the main AGND connection.

RTS2

CTS2 Active-Low Clear-to-Send Input for UART2. CTS2 is a flow control status input.

RTS3

CTS3 Active-Low Clear-to-Send Input for UART3. CTS3 is a flow control status input.

EXT

drain) or external event interrupt source. GPIO9 has a weak pulldown resistor to ground. GPIO9 is the TIMER output when bit 7 of the TIMER2 register is set to 1.

General-Purpose Input/Output 10. GPIO10 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO10 has a weak pulldown resistor to ground.

General-Purpose Input/Output 11. GPIO11 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO11 has a weak pulldown resistor to ground.

Active-Low Request-to-Send Output for UART2. RTS2 can be set high or low by programming the LCR register. RTS2 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is set to 1.

EXT

General-Purpose Input/Output 12. GPIO12 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO12 has a weak pulldown resistor to ground. GPIO12 is the reference clock output when bit 7 of the TxSynch register is set to 1 (see the UART Clock to GPIO section for more information).

General-Purpose Input/Output 13. GPIO13 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO13 has a weak pulldown resistor to ground. GPIO13 is the TIMER output if bit 7 of the TIMER2 register is set to 1.

General-Purpose Input/Output 14. GPIO14 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO14 has a weak pulldown resistor to ground.

General-Purpose Input/Output 15. GPIO15 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO15 has a weak pulldown resistor to ground.

Active-Low Request-to-Send Output for UART3. RTS3 can be set high or low by programming the LCR register. RTS3 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is set to 1.

EXT

Transceiver Interface Level Supply. V CTS_, and GPIO_. Bypass V

Crystal Output. When using an external crystal, connect one end of the crystal to XOUT and the other to XIN. When using an external clock source, leave XOUT unconnected.

Crystal/Clock Input. When using an external crystal, connect one end of the crystal to XIN and the other one to XOUT. When using an external clock source, drive XIN with the external clock.

Analog Supply. VA powers the PLL, and the internal LDO. Bypass VA with a 0.1FF ceramic capacitor to

AGND.

Internal 1.8V LDO Output and 1.8V Logic Supply Input. Bypass V18 with a 1FF ceramic capacitor to

DGND.

with a 0.1FF ceramic capacitor to DGND.

EXT

powers the internal logic-level translators for RX_, TX_, RTS_,

EXT

MAX14830

Quad Serial UART with 128-Word FIFOs

Detailed Description

The MAX14830 quad UART bridges an SPI/MICROWIRE™ or I2C microprocessor bus to an asynchronous interface like RS-485, RS-232, or IrDA. The MAX14830 contains advanced UARTs and baud-rate generators with a synchronous serial-data interface and an interrupt generator. The MAX14830 is configured by writing an 8-bit word to the configuration registers through either SPI or I2C. These registers are organized by related function as

MAX14830

shown in the Register Map.

The host controller loads transmit data into the THR register through SPI or I2C. This data is automatically pushed into the Transmit FIFOs, formatted, and sent out at TX_. The MAX14830 adds START and STOP and parity bits to the data and sends the data out at the selected baud rates. The clock configuration registers determine the baud rates, clock source selection, clock frequency prescaling, and fractional baud-rate generators.

The MAX14830 receiver detects a START bit as a highto-low RX_ transition. An internal clock samples this data at 16 times the data rate. The received data is automatically placed in the Receive FIFOs and can then be read out of the RxFIFOs through the RHRs.

The MAX14830 features four identical UARTS. Text in this data sheet references individual UART operation, unless otherwise noted.

generates an interrupt when the Transmit FIFO level is above the programmed trigger level. The host then knows to throttle data writing to the Transmit FIFO.

The host can read out the number of words present in each of the FIFOs at any time through the TxFIFOLvl and RxFIFOLvl registers.

Transmitter Operation

Figure 3 shows the structure of the transmitter with the TxFIFO. The Transmit FIFO can hold up to 128 words that are written to it through the Transmit Hold Register (THR).

The current number of words in the TxFIFO can be read out through the TxFIFOLvl register. The Transmit FIFO can be programmed to generate an interrupt when a programmed number of words are present in the TxFIFO through the FIFOTrgLvl register. The TxFIFO interrupt trigger level is selectable through FIFOTrgLvl[3:0]. When the Transmit FIFO fill level reaches the programmed trigger level, the ISR[4] interrupt is set.

The Transmit FIFO is empty when ISR[5]:TFifoEmptyInt is set. ISR[5] turns high when the transmitter starts transmitting the last word in the TxFIFO. Hence the transmitter is completely empty after ISR[5] is set with an additional delay equal to the length of a complete character (including START, parity, and STOP bits).

Receive and Transmit FIFOs

The UART’s receiver and the transmitter each have a 128-word deep FIFO reducing the intervals that the host processor needs to dedicate for high-speed, highvolume data transfer. As the data rates of the asynchronous RX_ and TX_ interfaces increase and get closer to those of the host controller’s SPI/I2C data rates, UART management and flow control can make up a significant portion of the host’s activity. By increasing FIFO size, the host is interrupted less often and can utilize SPI and I2C burst data block transfers to/from the FIFOs.

FIFO trigger levels can generate interrupts to the host controller, signaling that programmed FIFO fill levels have been reached. The transmitter and receiver trigger levels are programmed through FIFOTrigLvl with a resolution of eight FIFO locations. When a Receive FIFO trigger is generated, the host knows that the Receive FIFO has a defined number of words waiting to be read out or that a known number of vacant FIFO locations are available, ready to be filled. The Transmit FIFO trigger

MICROWIRE is a trademark of National Semiconductor Corp.

DATA FROM SPI/I2C

TRIGGER

ISR[4]

LEVEL

TxFIFOLvL

ISR[5]

Figure 3. Transmit FIFO Signals

EMPTY

CURRENT FILL LEVEL

INTERFACE

THR 128

FIFO TRGLVL[3:0]

TRANSMIT

FIFO

TRANSMIT

SHIFT-REGISTER

3 2 1

TX_

Quad Serial UART with 128-Word FIFOs

MAX14830

RECEIVED DATA

MID BIT

SAMPLING

START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP

Figure 4. Receive Data Format

ISR[3]

ISR[6]

OVERRUN

TRIGGER

TIMEOUT

EMPTY

ERRORS

LSR[1]

CURRENT FILL LEVEL

I2C/SPI INTERFACE

LSR[0]

LSR[5:2]

Figure 5. Receive FIFO

LSB

RECEIVER RX_

WORD ERROR 128

FIFOTrgLvl[7:4]

RECEIVE FIFO

RxFIFOLvl

RHR

RECEIVED

DATA

4 3 2 1

MSB

The contents of the TxFIFO and RxFIFOs are both cleared through MODE2[1]: FIFORst.

To halt transmission, set MODE1[1]: TxDisabl to 1. After MODE1[1] is set, the transmitter completes transmission of the current character and then ceases transmission.

The TX_ output logic can be inverted through IrDA[5]: TxInv. If not stated otherwise, all transmitter logic described in this data sheet assumes that IrDA[5] is 0.

Receiver Operation

The receiver expects the format of the data at RX_ to be as shown in Figure 4. The quiescent logic state is high and the first bit (the START bit) is logic-low. The receiver samples the data near the midbit instant (Figure 4). The received words and their associated errors are deposited into the Receive FIFO. Errors and status information are stored for every received word (Figure 5). The host reads the data out of the Receive FIFO through the Receive Hold Register (RHR), oldest data first. The status information of the most recently read word in the RHR is located in the Line Status Register (LSR). After a word is read out of the RHR, the LSR contains the status information for that word.

The following three error conditions are determined for each received word: parity error, framing error, and noise on the line. Line noise is detected by checking the consistency of the logic of the three samples (Figure 6).

RX_

BAUD

BLOCK

Figure 6. Midbit Sampling

ONE BIT PERIOD

23456789

10 11

MAJORITY

CENTER

SAMPLER

12 13 14 15 16

Quad Serial UART with 128-Word FIFOs

The receiver can be turned off through MODE1[0]: RxDisabl. When this bit is set to 1, the MAX14830 turns the receiver off immediately following the current word and does not receive any further data.

The RX_ input logic can be inverted through IrDA[4]: RxInv.

Line Noise Indication

When operating in standard or 2x (i.e. not 4x) rate mode, the MAX14830 checks that the binary logic level of the

MAX14830

three samples per received bit are identical. If any of the three samples have differing logic levels, then noise on the transmission line has affected the received data and is considered to be noisy. This noise indication is reflected in the LSR[5]: RxNoise bit for each received byte. Parity errors are another indication of noise, but are not as sensitive.

Clocking and Baud-Rate Generation

The MAX14830 can be clocked by an external crystal, or an external clock source. Figure 7 shows a simplified diagram of the clocking circuitry. When the MAX14830 is clocked by a crystal, the STSInt[5]: ClockReady indicates when the clocks have settled and the baud-rate generator is ready for stable operation.

Each UART baud rate can be individually programmed. To achieve fast baud rate changes, first disable the UART's clock by setting CLKDisabl to 1. Then change the baud rate divisor and subsequently enable the clock via CLKDisabl.

To check that the UART's clocking is programmed as expected, route the baud rate clock to RTS using the CLKtoRTS bit. The clock rate of this is 16x the baud rate in standard operating mode and 8x the baud rate in 2x rate mode. In 4x rate mode, the CLKOUT frequency is 4x the programmed baud rate. If the fractional portion of the baud-rate generator is used, the clock is not regular and exhibits jitter.

Crystal Oscillator

Set BRGConfig[6]: CLKDisabl to 0 and CLKSource[1]: CrystalEn to 1 to enable and select the crystal oscillator. The on-chip crystal oscillator circuit has load capacitances of 16pF (typ) integrated in both XIN and XOUT. Connect an external crystal or ceramic oscillator between XIN and XOUT.

External Clock Source

Connect an external clock source to XIN when not using a crystal oscillator. Leave XOUT unconnected. Set CLKSource[1]: CrystalEn to 0 to select external clocking.

PLL and Predivider

The internal predivider and PLL allow for a wide range of external clock frequencies and baud rates. The PLL can be configured to multiply the input clock rate by a factor of 6, 48, 96, or 144 through the PLLConfig register. The predivider, located between the input clock and the PLL, allows division of the input clock by a factor between 1 and 63 by writing to PLLConfig[5:0]. See the PLLConfig register description for more information.

XOUT

XIN

Figure 7. Clock Selection Diagram

CRYSTAL

OSCILLATOR

CrystalEn

DIVIDER

PLLEn ClkDisabl[0...3]

PLLBypass

PLL

FRACTIONAL

BAUD RATE

GENERATOR 0

FRACTIONAL

BAUD RATE

GENERATOR 1

FRACTIONAL

BAUD RATE

GENERATOR 2

FRACTIONAL

BAUD RATE

GENERATOR 3

Quad Serial UART with 128-Word FIFOs

Fractional Baud-Rate Generators

The internal fractional baud-rate generator provides a high degree of flexibility and high resolution in baudrate programming. The baud-rate generator has a 16-bit integer divisor and a 4-bit word for the fractional divisor. The fractional baud-rate generator can be used with the external crystal or clock source.

The integer and fractional divisors are calculated through the divisor, D:

where f

is the reference frequency input to the baud-

REF

rate generator and D is the ideal divisor. In 2x and 4x rate modes, replace the divisor 16 by 8 or 4, respectively.

The integer divisor portion, DIV, of the divisor, D, is obtained by truncating D:

DIV = TRUNC(D)

DIV can be a maximum of 16 bits wide and is programmed into the 2-byte-wide registers DIVMSB and DIVLSB. The minimum allowed value for DIVLSB is 1.

The fractional portion of the divisor, FRACT, is a 4-bit nibble, which is programmed into BRGConfig[3:0]. The maximum value is 15, allowing the divisor to be programmed with a resolution of 0.0625. FRACT is calculated as:

FRACT = ROUND(16 x (D-DIV)).

The following is an example of calculating the divisor. It is based on a required baud rate of 190kbaud and a reference input frequency of 28.23MHz and default rate mode.

The ideal divisor is calculated as:

D = 28,230,000 / (16 x 190,000) = 9.286

hence DIV = 9.

FRACT = ROUND(4.579) = 0x05

so that DIVMSB = 0x00, DIVLSB = 0x09, and BRGConfig[3:0] = 0x05.

REF

16 BaudRate

The resulting actual baud rate can be calculated as:

ACTUAL

For this example: D D

ACTUAL

= DIV + (FRACT/16) and

ACTUAL

= 28,230,000 / (16 x 9.3125) = 189,463.087

ACTUAL

REF

16 D=×

ACTUAL

= 9 + 5/16 = 9.313, where

baud.

Thus the baud rate is within 0.28% of the ideal rate.

2x and 4x Rate Modes

To support higher baud rates than possible with standard (16x sampling) operation, the MAX14830 offers 2x and 4x rate modes. In this case, the reference clock rate only needs to be either 8x or 4x of the baud rate, respectively. In 4x mode only, the bits are only sampled once, at the midbit instant, instead of the usual three samples to determine the logic value of the bits. This reduces the tolerance to line noise on the received data. The 2x and 4x modes are selectable through BRGConfig[5:4]. Note that IrDA encoding and decoding does not operate in 2x and 4x modes.

When 2x rate mode is selected, the actual baud rate is twice the rate programmed into the baud-rate generator. If 4x rate mode is enabled, the actual baud rate on the line is quadruple that of the programmed baud rate (Figure 8).

DIVLSB

DIVMSB

FRACT

REF

NOTE: IrDA DOES NOT WORK IN 2x AND 4x MODES.

Figure 8. 2x and 4x Baud Rates

FRACTIONAL

RATE

GENERATOR

BRGConfig[5:4]

RATE MODE

SELECTION

1 x BAUD RATE, 2 x BAUD RATE, 4 x BAUD RATE

MAX14830

+ 47 hidden pages

MAXIM MAX14830 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Applications

Features

Ordering Information

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

LIST OF REGISTERS

Functional Diagram

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

Test Circuits/Timing Diagrams

Typical Operating Characteristics

Pin Configuration

Pin Description

Detailed Description

Transmitter Operation

Receive and Transmit FIFOs

Receiver Operation

Line Noise Indication

Clocking and Baud-Rate Generation

Crystal Oscillator

External Clock Source

PLL and Predivider

Fractional Baud-Rate Generators

2x and 4x Rate Modes