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MAX14824
User Manual
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MAXIM MAX14824 User Manual

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EVALUATION KIT AVAILABLE
19-5788; Rev 3; 5/12
MAX14824
IO-Link Master Transceiver

General Description

The MAX14824 is an IO-LinkM master interface that inte­grates an IO-Link physical layer transceiver with an auxiliary digital input and two linear regulators. High port count IO-Link master applications are supported through in-band SPI addressing, and the 12MHz SPI interface minimizes host controller access times. In-band address­ing and selectable SPI addresses enable cascading up to 16 devices.
The device supports all the IO-Link data rates and fea­tures slew-rate-controlled drivers to reduce EMI. The driver is guaranteed to drive up to 300mA (min) load currents. Internal wake-up circuitry automatically deter­mines the correct wake-up polarity, allowing for the use of simple UARTs for wake-up pulse generation.
The MAX14824 is available in a 4mm x 4mm, 24-pin TQFN package with exposed pad, and operates over the extended -40NC to +105NC temperature range.

Applications

IO-Link Master Controllers PLC Fieldbus Gateways High Port Count IO-Link Masters 24V Digital Inputs and Outputs
Ordering Information appears at end of data sheet.

Features

S IO-Link v.1.0 and v.1.1 Physical Layer Compliant
S Supports COM1, COM2, and COM3 Data Rates
S Push-Pull, High-Side, or Low-Side Outputs
S 300mA C/Q Output Drive
S 1µF C/Q Load Drive Capability
S Generates 500mA Wake-Up Pulse
S Automatic Wake-Up Pulse Polarity
S Auxiliary Digital Input
S 5V and 3.3V Linear Regulators
S SPI Interface for Configuration and Monitoring
S SPI-Based Chip Addressing
S EMI Emission Control Through Slew-Controlled
Driver
S Reverse-Polarity Protection on DI
S Short-Circuit Protection on C/Q
S High Temperature Warning and Thermal Shutdown
S Extensive Fault Monitoring and Reporting
S -40NC to +105NC Operating Temperature Range
S 4mm x 4mm TQFN Package

Typical Operating Circuits

24V
1μF 0.1μF
V
CC
IO-LINK
CONTROLLER
Typical Operating Circuits continued at end of data sheet.
IO-Link is a registered trademark of Profibus User Organization (PNO).
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX14824.related
SPI
WUENGPO
RXRX
TXCTX
TXENRTS
LDO33VLTXQ
V
MAX14824
LDOIN
5
GNDA3A2A1A0GND
1μF
V
CC
C/Q C/Q
DI
270pF
270pF
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX14824
IO-Link Master Transceiver

Functional Diagram

SDI
SDO
SCLK
IRQ
A3:A0
WUEN
TXQ
TXC
TXEN
FILTER
DRIVER
V
5
5V LDO
MAX14824
SHORT-CIRCUIT
PROTECTION
C/Q LOAD
REVERSE
POLARITY
PROTECTION
V
CC
C/Q
GND
DI
LDO33 LDOIN
UV
UV MONITOR
V
L
CS
STATUS
AND
CONFIGURATION
RX
WU POLARITY
GENERATOR
LI
3.3V LDO
DI LOAD
2
MAX14824
IO-Link Master Transceiver

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND, unless otherwise specified.)
VCC ........................................................................ -0.3V to +40V
LDOIN ....................................................................-0.3V to +40V
V5 .......................0.3V to the lesser of (V
LDO33 .................... -0.3V to the lesser of (V5 + 0.3V) and +6V
VL ............................................................................. -0.3V to +6V
DI ............................................................................ -40V to +40V
C/Q ........................................................... -0.3V to (VCC + 0.3V)
Logic Inputs
TXC, TXQ, TXEN, A2, CS, SDI, SCLK, WUEN .. -0.3V to (VL + 0.3V)
A3, A1, A0 ...........................................................-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera­tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
+ 0.3V) and +6V
LDOIN
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (BJA) ..........36NC/W
Junction-to-Case Thermal Resistance (BJC) .................3NC/W
Logic Outputs
RX, LI, SDO, IRQ ..................................... -0.3V to (VL + 0.3V)
UV ........................................................................ -0.3V to +6V
Continuous Current Into Any Logic Pin .......................... Q50mA
Continuous Power Dissipation
TQFN (derate 27.8mW/NC above +70NC)..................2222mW
Operating Temperature Range ........................ -40NC to +105NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

DC ELECTRICAL CHARACTERISTICS

(VCC = 18V to 36V, VL = 2.3V to 5.5V, V values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage V
VCC Supply Current I
VCC Undervoltage Lockout Threshold
VCC Undervoltage Lockout Threshold Hysteresis
V5 Supply Current I
V5 Undervoltage Lockout Threshold
VL Logic-Level Supply Voltage V
VL Logic-Level Supply Current I
VL Undervoltage Threshold V
5V LDO (V5)
LDOIN Input Voltage Range V
V
= 0V; all logic inputs at VL or GND; TA = -40NC to +105NC, unless otherwise noted. Typical
GND
CC
CC
V
CCUVLO
CCUVLO_HYST
5_IN
V
5UVLO
L
L
LUVLO
LDOIN
For driver operation 9 36 V
VCC = 24V, C/Q as input, no load on V5 or LDO33, LDOIN not connected to VCC, V
= 24V
LDOIN
VCC falling 6 7.5 9 V
LDOIN shorted to V5, external 5V applied to V5, no switching, LDO33 disabled
V5 falling 2.4 V
2.3 5.5 V
All logic inputs at VL or GND 5
VL falling 0.65 0.95 1.3 V
7 36 V
1.3 2.5 mA
200 mV
3 mA
FA
3
IO-Link Master Transceiver
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 18V to 36V, VL = 2.3V to 5.5V, V values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LDOIN Supply Current I
V5 Output Voltage Range V
V5 Load Regulation
3.3V LDO (LDO33)
LDO33 Output Voltage V
LDO33 Undervoltage Lockout Threshold
LDO33 Load Regulation 1mA < I
24V INTERFACE
C/Q Output Resistance High R
C/Q Output Resistance Low R
C/Q Source Current Limit I
C/Q Sink Current Limit I
C/Q Input Threshold High V
C/Q Input Threshold Low V
C/Q Input Hysteresis V
DI Input Threshold High V
DI Input Threshold Low V
DI Input Hysteresis V
C/Q Weak Pulldown Current I
DI Weak Pulldown Current I
C/Q Input Capacitance C
DI Input Capacitance C
C/Q, DI INPUT LOAD
C/Q Load Current I
DI Load Current I
= 0V; all logic inputs at VL or GND; TA = -40NC to +105NC, unless otherwise noted. Typical
GND
V
= 24V, C/Q as input, no load on
LDOIN
5
LDO33
V
LDO33UVLOVLDO33
OH_C/Q
OL_C/Q
OH_C/Q
OL_C/Q
IH_C/Q
IL_C/Q
HYS_C/Q
IH_DI
IL_DI
HYS_DI
PDC/Q
PDDI
C/Q
DI
LLM_C/Q
LLM_DI
LDOIN
V5 or LDO33
No load on V5, 7V P V
1mA < I
LOAD
< 10mA, V
0.1FF bypass capacitor on V
LDOIN
LDOIN
P 36V
= 7V,
5
No load on LDO33 3.1 3.5 V
falling 2.4 V
< 10mA, V
LOAD
C/Q high-side enabled, I
= 7V 0.25 %
LDOIN
= -200mA,
C/Q
9V P VCC P 36V (Note 5)
C/Q low-side enabled, I
= +200mA,
C/Q
9V P VCC P 36V (Note 5)
C/Q high-side enabled, V
< (VCC -
C/Q
3V), 9V P VCC P 36V
C/Q low-side enabled, V
> 3V, 9V P
C/Q
VCC P 36V
C/Q driver disabled 10.5 13.0 V
C/Q driver disabled 8.0 11.5 V
C/Q driver disabled 1.0 V
C/Q driver disabled, V
DI load disabled, VDI = V
C/Q
= V
CC
CC
C/Q driver disabled 40 pF
C/Q load enabled (C/QLoad = 1)
DI load enabled (DiLoad = 1)
0 P V
9V P V
0 P VDI P 5V
9V P V
C/Q
C/Q
DI
P 5V
MAX14824
3.0 5 mA
4.75 5.00 5.25 V
0.08 %
1.8 2.9
2.0 3.6
+500 +670 mA
-660 -500 mA
6.8 8 V
5.2 6.4 V
1 V
100 400
50 300
20 pF
0 8.1
5 6.8 8.1
0 4.3
2 3.5 4.3
I
I
FA
FA
mA
mA
4
MAX14824
IO-Link Master Transceiver
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 18V to 36V, VL = 2.3V to 5.5V, V values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (TXC, TXQ, TXEN, CS, WUEN, SDI, SCLK, A3, A2, A1, A0)
Logic Input-Voltage Low V
Logic Input-Voltage High V
Logic Input Leakage Current I
Logic Input Capacitance C
A1 Pulldown Resistance R
LOGIC OUTPUTS (RX, LI, UV, SDO, IRQ)
Logic Output-Voltage Low V
Logic Output-Voltage High
SDO Leakage Current I
THERMAL SHUTDOWN
Thermal Warning Threshold Die temperature rising, OTemp bit is set +115
Thermal Warning Threshold Hysteresis
Thermal Shutdown Threshold Die temperature rising +150
Thermal Shutdown Hysteresis 20
V
= 0V; all logic inputs at VL or GND; TA = -40°C to +105°C, unless otherwise noted. Typical
GND
0.3 x V
L
-1 +1
325 800
VL -
0.6
-1 +1
V
OHRX
OHWU
V
OHSDO
V
OHIRQ
LK_SDO
IL
IH
LEAK
IN
A1PD
OL
, V
Logic input = GND or V
I
= -5mA 0.4 V
OUT
,
,
OHLI
I
= 5mA (Note 3)
OUT
,
,
SDO disabled, SDO = GND or V
Die temperature falling, OTemp bit is cleared
L
L
0.7 x V
L
5 pF
20
V
V
FA
kI
V
FA
NC
NC
NC
NC

AC ELECTRICAL CHARACTERISTICS

(VCC = 18V to 36V, VL = 2.3V to 5.5V, V values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
C/Q, DI INTERFACES
Data Rate DR
DRIVER (C/Q)
Driver Low-to-High Propagation Delay
Driver High-to-Low Propagation Delay
= 0V; all logic inputs at VL or GND; TA = -40°C to +105°C, unless otherwise noted. Typical
GND
HiSlew = 1 4.8 230.4
HiSlew = 0 4.8 38.4
t
PDLH
t
PDHL
Push-pull or high-side (PNP) configuration, Figure 1
Push-pull or low-side (NPN) configuration, Figure 1
HiSlew = 1 0.5 2
HiSlew = 0 1.6 5
HiSlew = 1 0.5 2
HiSlew = 0 1.6 5
kbps
Fs
Fs
5
IO-Link Master Transceiver
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 18V to 36V, VL = 2.3V to 5.5V, V values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Driver Skew t
Driver Rise Time t
Driver Fall Time t
Driver Enable Time High t
Driver Enable Time Low t
Driver Disable Time High t
Driver Disable Time Low t
RECEIVER (C/Q, DI) (Figure 4)
Receiver Low-to-High Propagation Delay
Receiver High-to-Low Propagation Delay
WAKE-UP GENERATION (Figure 5)
Wake-Up Enable Setup Time t
Wake-Up Enable Hold Time t
Wake-Up Pulse Rise Propagation Delay
Wake-Up Pulse Fall Propagation Delay
SPI TIMING (CS, SCLK, SDI, SDO) (Figure 6)
SCLK Clock Period t
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Time SCLK Rise to CS Rise Hold
Time
SDI Hold Time t
= 0V; all logic inputs at VL or GND; TA = -40oC to +105oC, unless otherwise noted. Typical
GND
|t
- t
SKEW
RISE
FALL
ENH
ENL
DISH
DISL
t
PRLH
t
PRHL
WUEN,S
WUEN,H
t
1
t
2
CH+CL
CH
CL
t
CSS
t
CSH
DH
PDLH
Push-pull or high-side (PNP) configuration, Figure 1
Push-pull or low-side (NPN) configuration, Figure 1
Push-pull or high-side (PNP) configuration, Figure 3
Push-pull or low-side (NPN) configuration, Figure 2
Push-pull or high-side (PNP) configuration, Figure 2 (Note 4)
Push-pull or low-side (NPN) configuration, Figure 3 (Note 4)
RxFilter = 0 0.4 2
RxFilter = 1 0.2 2
RxFilter = 0 0.5 2
RxFilter = 1 0.3 2
| 0.1 2
PDHL
HiSlew = 1 0.4 0.85
HiSlew = 0 1.5 4
HiSlew = 1 0.4 0.85
HiSlew = 0 1.4 4
HiSlew = 1 0.3 1.5
HiSlew = 0 0.8 7
HiSlew = 1 0.3 1.5
HiSlew = 0 0.9 7
HiSlew = 1 1.6 3
HiSlew = 0 1.6 3
HiSlew = 1 0.1 3
HiSlew = 0 0.1 3
MAX14824
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
30 ns
30 ns
1.5 5
1.5 3
83.3 ns
41.65 ns
41.65 ns
20 ns
20 ns
10 ns
Fs
Fs
6
MAX14824
IO-Link Master Transceiver
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 18V to 36V, VL = 2.3V to 5.5V, V values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SDI Setup Time t
Output Data Propagation Delay t
SDO Rise and Fall Times t
Minimum CS Pulse
Note 2: All devices are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by
design.
Note 3: UV is an open-drain output. Connect UV to a voltage less than 5.5V through an external pullup resistor. Note 4: Disable time measurements are load-dependent. Note 5: Guaranteed by design. Limits are not production tested.
= 0V; all logic inputs at VL or GND; TA = -40oC to +105oC, unless otherwise noted. Typical
GND
DS
DO
FT
t
CSW
10 ns
32 ns
20 ns
76.8 ns
7
MAX14824
IO-Link Master Transceiver
TXEN
TXC AND TXQ
C/Q

Figure 1. Driver Polarity and Timing

t
PDHL
TXC
TXQ
t
FALL
TXEN
MAX14824
GND
C/Q
t
RISE
V
CC
3.3nF 5kΩ
50%
t
PDLH
90% 50%
10%
V
L
0V
V
L
0V
V
CC
0V
V
L
TXC
TXQ
TXEN
t
ENL
C/Q
10%

Figure 2. Driver Enable Low and Disable High Timing

TXEN
MAX14824
GND
C/Q
t
DISH
3.3nF
10%
5kΩ
V
L
0V
V
CC
0V
8
TXEN
C/Q
t
ENH
TXC
TXQ
90%
MAX14824
IO-Link Master Transceiver
TXEN
C/Q
MAX14824
GND
t
DISL
3.3nF 5kΩ
90%
V
L
0V
V
CC
0V

Figure 3. Driver Enable High and Disable Low Timing

C/Q OR DI
C/Q OR DI
t
PRLH
OR LI
RX

Figure 4. Receiver Polarity and Timing

TXEN
MAX14824
GND
RX OR LI
t
PRHL
50%
15pF
50%
V
CC
0V
V
L
0V
9
WUEN
MAX14824
IO-Link Master Transceiver
TXC AND TXQ
C/Q

Figure 5. Wake-Up Generation

CS
t
CSS
SCLK
t
CSH
t
WUEN, S
t
WUEN, H
80µs
t
1
WAKE-UP PULSE
t
t
CL
CH
t
2
X
t
CSH
SDI
SDO

Figure 6. SPI Timing Diagram

t
DS
t
DH
t
DO
10
MAX14824
IO-Link Master Transceiver

Typical Operating Characteristics

(VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.)
C/Q DRIVER OUTPUT HIGH
vs. LOAD CURRENT
24
23
22
(V)
21
OH_C/Q
20
V
19
18
TXEN = V TCX = TXQ = GND
17
0 800
TA = +25°C
TA = +85°C
L
LOAD CURRENT (mA)
TA = -40°C
TA = +105°C
C/Q DRIVER PROPAGATION DELAY
vs. TEMPERATURE (HiSlew = 0)
1.50
TXEN = V TXC = TXQ
L
TEMPERATURE (°C)
1.48
1.46
1.44
1.42
(µs)
1.40
PDHL
t
1.38
1.36
1.34
1.32
1.30
-45 90
C/Q DRIVER OUTPUT LOW
vs. LOAD CURRENT
7
TXEN = V
L
TCX = TXQ = V
MAX14824 toc01
700600500400300200100
6
5
(V)
4
OL_C/Q
3
V
2
1
0
0 800
L
MAX14824 toc02
TA = +105°C
TA = +85°C
TA = +25°C
TA = -40°C
700600500400300200100
LOAD CURRENT (mA)
C/Q DRIVER PROPAGATION DELAY
vs. TEMPERATURE (HiSlew = 1)
0.50
TXEN = V
L
TXC = TXQ
MAX14824 toc03
756030 45-15 0 15-30
0.45
0.40
0.35
(µs)
PDHL
t
0.30
0.25
0.20
0.15
-45 90 TEMPERATURE (°C)
60 754530150-15-30
MAX14824 toc04
C/Q DRIVER OUTPUT SWITCHING
(HiSlew = 0)
V
TXC
2V/div
0V
TXEN = V TXC = TXQ
V
C/Q
5V/div
0V
L
2µs/div
MAX14824 toc05
Ch1 Ch2
1.593µs
Ch1 Ch2
1.408µs
Ch2 RISE
1.618µs
Ch2 FALL
1.520µs
V
TXC
2V/div
V
C/Q
5V/div
C/Q DRIVER OUTPUT SWITCHING
(HiSlew = 1)
0V
TXEN = V
L
TXC = TXQ
0V
2µs/div
MAX14824 toc06
Ch1 Ch2
425.9ns
Ch1 Ch2
381.9ns
Ch2 RISE
365.6ns
Ch2 FALL
370.4ns
11
MAX14824
IO-Link Master Transceiver
Typical Operating Characteristics (continued)
(VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.)
500
450
400
350
300
(ns)
250
PRHL
t
200
150
100
50
0
-45 90
C/Q SHORT-CIRCUIT PROTECTION
TXC = TXQ = GND, t
SHORT
40µs/div
= 200µs
RECEIVER PROPAGATION DELAY vs. TEMPERATURE (RxFilter = 0)
DI TO LI
C/Q TO RX
TEMPERATURE (°C)
MAX14824 toc09
V
C/Q
10V/div 0V
V
IRQ
2V/div 0V
I
SOURCE
500mA/div 0mA
C/Q SHORT-CIRCUIT PROTECTION
TXC = TXQ = VL, t
C/Q RECEIVER PROPAGATION DELAY
vs. TEMPERATURE (RxFilter = 1)
500
450
756030 45-15 0 15-30
20µs/div
MAX14824 toc08
MAX14824 toc11
V
WUEN
2V/div 0V
V
TXC
2V/div 0V
V
C/Q
10V/div
0V
MAX14824 toc07
756030 45-15 0 15-30
= 300µs
SHORT
40µs/div
400
350
300
(ns)
250
PRHL
t
200
DI TO LI
150
C/Q TO RX
100
50
0
-45 90
TEMPERATURE (°C)
MAX14824 toc10
V
C/Q
10V/div
0V
V
IRQ
2V/div
0V
I
SINK
500mA/div 0mA
WAKE-UP GENERATION
12
MAX14824
93
93
05
05
IO-Link Master Transceiver
Typical Operating Characteristics (continued)
(VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.)
2.0
1.8
1.6
1.4
1.2
(mA)
1.0
CC
I
0.8
0.6
0.4
V
LDOIN
C/Q DRIVER IS ENABLED
0.2
TXC = TXQ = V
0
0.1
0
-0.1
-0.2
-0.3
% VOLTAGE CHANGE
-0.4
-0.5
VCC SUPPLY CURRENT
vs. V
CC
TA = +85°C
TA = +25°C
= 7V
L
VCC VOLTAGE (V)
TA = -40°C
VOLTAGE
TA = -40°C
V5 LOAD REGULATION
TA = +25°C
TA = +85°C
LOAD CURRENT (mA)
MAX14824 toc14
(mA)
LDOIN
I
333024 2715 18 2112
6
MAX14824 toc12
40302010
0
LDOIN SUPPLY CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
TA = +85°C
VCC = 36V C/Q DRIVER IS ENABLED TXC = TXQ = V
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
% VOLTAGE CHANGE
-0.7
-0.8
-0.9
-1.0
vs. LDOIN VOLTAGE
TA = +25°C
L
V
(V)
LDOIN
0
TA = -40°C
30 33272421181512
LDO33 LOAD REGULATION
TA = -40°C
TA = +25°C
TA = +85°C
LOAD CURRENT (mA)
20
V
LDOIN
18
HiSlew = 1, NO LOAD ON C/Q,
MAX14824 toc15
6
CONTINUOUS 1010 PATTERN TRANSMISSION
16
14
12
(mA)
10
CC
I
8
6
4
2
0
1 1000
MAX14824 toc13
454030 3510 15 20 255
0
VCC SUPPLY CURRENT
vs. C/Q DATA RATE
= V5 = 5V, TXEN = VL,
VCC = 36V
VCC = 30V
VCC = 24V
10010
C/Q DATA RATE (kbps)
MAX14824 toc16
13
MAX14824
IO-Link Master Transceiver

Pin Configuration

TOP VIEW
GND
C/Q
V
LI
1718 16 14 13
DI
19
20
21
22
23
CC
A0
+
24
12A1456
5
V
LDOIN
A2
MAX14824
3
LDO33
15
WUEN
IRQ
RXUVTXEN
*EP
SCLK
12
TXC
TXQ
11
A3
10
9
V
L
SDI
8
SDO
7
CS
TQFN
(4mm × 4mm)
*CONNECT EXPOSED PAD TO GND.

Pin Description

PIN NAME FUNCTION
1 LDOIN
2 V
3 LDO33
4
IRQ Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to VL.
5 SCLK SPI Clock Input
6
CS
7 SDO SPI Serial-Data Output Port
8 SDI SPI Serial-Data Input Port
9 V
10 A3 Chip-Select Address Input 3. Do not leave A3 unconnected.
11 TXQ Transmit Level Input. TXQ is ANDed with TXC. Drive TXQ high if not in use.
12 TXC Transmit Communication Input. TXC is ANDed with TXQ. Drive TXC high if not in use.
13 TXEN
5V Linear-Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor.
5V Power-Supply Input and 5V Linear-Regulator Output. Bypass V5 to GND with a 0.1FF ceramic capacitor.
5
See the 5V and 3.3V Linear Regulators section for more information.
3.3V Linear-Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor.
SPI Chip-Select Input
Logic-Level Supply Input. VL defines the logic levels on all the logic inputs and outputs. Bypass VL to
L
GND with a 0.1FF ceramic capacitor.
Transmitter Enable. Driving TXEN high enables the C/Q transmitter. While the C/Q transmitter is enabled, the C/Q current sink is turned off.
14
MAX14824
IO-Link Master Transceiver
Pin Description (continued)
PIN NAME FUNCTION
14 RX
15 WUEN Wake-Up Enable Input. Drive WUEN high to enable automatic wake-up pulse generation.
16 A2 Chip-Select Address Input 2. Do not leave A2 unconnected.
17 LI Logic Output of 24V DI Logic Input. LI is the inverse logic of DI. LI is referenced to VL.
18 UV Open-Drain Undervoltage Indicator Output. UV is active high.
19 DI 24V Logic-Level Digital Input
20 GND Ground
21 C/Q
22 A1 Chip-Select Address Input 1. Do not leave A1 unconnected.
23 V
24 A0 Chip-Select Address Input 0. Do not leave A0 unconnected.
— EP Exposed Pad. Connect EP to GND.
Receiver Output. RX is the inverse logic level of C/Q. RX is always high when the RxDis bit in the CQConfig register is set to 1.
SIO/IO-Link Data Input/Output. Drive TXEN high to enable the C/Q driver. The logic on the C/Q output is the inverse logic level of the signals on the TXC and TXQ inputs. Drive TXEN low to disable the C/Q driver. RX is the logic inverse of C/Q.
Power-Supply Input. Bypass VCC to GND with a 1FF ceramic capacitor.
CC

Detailed Description

The MAX14824 is an IO-LinkM master transceiver that integrates an IO-Link physical interface with an additional 24V digital input and two LDOs. A 12MHz SPIK interface allows fast programming and monitoring.
The device supports COM1, COM2, and COM3 IO-Link data rates and has the option of limiting emitted EMI by selecting a lower slew rate at lower data rates. The auto­matic wake-up circuitry determines the correct wake-up pulse polarity, allowing the use of simple UARTs for wake-up pulse generation.
The C/Q and DI inputs have selectable current sinks that can be enabled for use in actuators.
The device is configured and monitored through an SPI interface. Extensive alarms are available through SPI.

24V Interface

The device features an IO-Link transceiver interface capable of operating with voltages up to 36V. This includes the C/Q input/output and the logic-level digital input (DI).
IO-Link is a registered trademark of Procibus User Organization (PNO).
SPI is a trademark of Motorola Inc.
DI is reverse-polarity protected. Short-circuit protection is provided on the C/Q driver.

Configurable C/Q Driver

The device’s C/Q driver has a selectable push-pull, high­side (PNP), or low-side (NPN) switching driver.
Set the C/Q_N/P and C/Q_PP bits in the CQConfig reg­ister to select the driver mode for the C/Q driver. When configured as a push-pull output, C/Q switches between VCC and ground. Set the C/Q_PP bit to 1 to select push­pull operation. Set the C/Q_PP bit to 0 to configure the C/Q output for open-drain operation. The C/Q_N/P bit selects NPN or PNP operation when C/Q is configured as an open-drain output.

C/Q Driver and Receiver

The C/Q driver can be enabled through hardware (TXEN) or software (C/QDEn). Drive TXEN high to enable the C/Q driver and drive TXEN low to disable the driver. The C/Q driver can be enabled through the C/QDEn bit in the C/QConfig register.
The C/Q driver on the device is specified for 300mA to drive large capacitive loads over 1FF and dynamic impedances like incandescent lamps.
15
MAX14824
IO-Link Master Transceiver
The HiSlew bit increases the slew rate of the C/Q driver output. Set HiSlew to 1 for data rates of 230kbps or higher. Set HiSlew to 0 to reduce the C/Q driver slew rate and reduce EMI emission and reflections.
The C/Q receiver is always on. Disable the RX output through the RxDis bit in the CQConfig register. Set the RxDis bit to 1 to set the RX output high. Set the RxDis bit to 0 for normal receive operation.
The C/Q receiver has an analog lowpass filter to reduce high-frequency noise present on the line. Set the RxFilter bit in the CQConfig register to 0 to set the filter corner frequency to 500kHz (typ). Set the RxFilter bit to 1 to set the corner frequency of the filter to 1MHz (typ). Noise filters are present on both the C/Q and DI receivers and are controlled simultaneously by the RxFilter bit.

C/Q Fault Detection

The device registers a C/QFault condition under either of two conditions:
1) When it detects a short circuit for longer than 160µs (typ). A short condition exists when the C/Q driver’s load current exceeds the 670mA (typ) current limit.
2) When it detects a voltage level error at the C/Q out­put. A voltage level error occurs when the C/Q driver is configured for open-drain operation (NPN or PNP), the driver is turned off, and the C/Q voltage is not pulled to exceed the C/Q receiver’s threshold levels (< 8V or > 13V) by the external supply.
When a C/QFault error occurs, the C/QFault and C/QFaultInt bits are set, IRQ asserts, and the driver is turned off 240µs (typ) after the start of the fault condition.
When a short-circuit event occurs on C/Q, the driver enters autoretry mode. In autoretry mode the device peri­odically checks if the short is still present and attempts to correct the driver output. Autoretry attempts last for 350µs (typ) and occur every 26ms (typ).

DI Auxillary Digital Input

DI is a digital input that is Type 1 and Type 3 compliant when the internal 3.5mA DI current load is enabled. If the IO-link master system does not require auxilliary digital inputs, DI can be connected to C/Q as shown in the
Typical Operating Circuits. This reduces the power dissi-
pation when C/Q is operated as a digital input, by enabling the DI current load instead of the C/Q current load. Di is tolerant to reverse polarity voltages down to -40V when not connected to C/Q.

5V and 3.3V Internal Regulators

The device includes two internal current-limited regulators to generate 5V (V5) and 3.3V (LDO33). V5 is specified at 10mA. LDO33 is specified at 10mA. The input of V5, LDOIN, can be connected to VCC or to another voltage in the 7V to 36V range.
V5 consitutes the supply for the logic block in the device. The device can be powered by an external 5V power supply. Disable the 5V LDO by connecting LDOIN to V5. Apply an external voltage from 4.75V to 5.25V to V5 when the LDO is disabled.
Use the LDO33Dis bit in the Mode register to enable/ disable LDO33. See the Mode Register [R1, R0] = [1,1] section for more information. V5 and LDO33 are not pro­tected against short circuits.
Power-Up
The C/Q driver output and the UV output are high imped­ance when VCC, V5, VL, and/or LDO33 voltages are below their respective undervoltage thresholds during power-up. UV goes low and the C/Q driver is enabled when all these voltages exceed their respective under­voltage lockout thresholds.
The C/Q driver is automatically disabled if VCC, V5, or VL falls below its threshold.

Undervoltage Detection

The device monitors VCC, V5, VL, and, optionally, LDO33 for undervoltage conditions. UV is high impedance when any monitored voltage falls below its UVLO threshold.
VCC, V abled. When VCC falls below the V UV24 and UV24Int bits are set, UV asserts high, and IRQ asserts low.
The SPI register contents are unchanged while V5 is present, regardless of the state of VCC or LDO33. The SPI interface is not accessible and IRQ is not available when UV is asserted due to a V5 or VL undervoltage event.
When the internal 3.3V LDO regulator voltage (V falls below the LDO33 undervoltage lockout threshold, the UV33Int bit in the Status register is set and IRQ asserts. UV asserts if the UV33En bit in the Mode register is set to 1.
The UV output deasserts once the undervoltage condi­tion is removed; however, the associated interrupts bits in the Status register and the IRQ output are not cleared until the Status register has been read.
, and V
5
undervoltage detection cannot be dis-
L
CCUVLO
threshold, the
LDO33
)
16
MAX14824
IO-Link Master Transceiver

Wake-Up Generation

The MAX14824 features automatic wake-up polarity gen­eration functionality that can be initiated through hard­ware or software. The following conditions must be met prior to automatic wake-up polarity generation to ensure proper functionality:
• WUENislow
• TXENislowandC/QDEn=0
• Q=0
• TXCandTXQarebothhigh
Drive WUEN high to enable the automatic wake-up polarity generation circuitry in the device. When WUEN is high, apply an external pulse to TXC or TXQ from high-to-low for 80Fs (typ) to generate a valid wake-up pulse. The applied pulse is independent of the logic state that the IO-Link sensor was forcing on the C/Q level (Figure 5). Drive WuEN low after the wake-up has been generated.
The C/Q driver is automatically enabled while TXC/TXQ is low and C/Q is pulled either from high-to-low or from low-to-high, depending on the previous state. The C/Q driver is automatically disabled when the TXC/TXQ inputs are pulled high again.
Wake-up polarity generation can also be enabled through software by setting the WuEnBit bit in the Mode register to 1. See the Mode Register [R1, R0] = [1,1] section for more information.

Thermal Protection and Considerations

The internal LDOs and C/Q driver can generate more power than the package for the device can safely dis­sipate. Ensure that the driver LDO loading is less than the package can dissipate. Total power dissipation for the device is calculated using the following equation:
P
where P P5 and P
TOTAL
= P
C/Q
+ P5 + P
C/Q
LDO33
+ PQ + P
CLCQ
+ P
is the power generated in the C/Q driver,
are the power generated by the LDOs,
LDO33
CLDI
PQ is the quiescent power generated by the device, and P
CLCQ
and P
are the power generated in the C/Q
CLDI
and DI current sinks.
Ensure that the total power dissipation is less than the limits listed in the Absolute Maximum Ratings section.
Use the following to calculate the power dissipation (in mW) due to the C/Q driver:
P
C/Q
= [I
C/Q
]2 x [RO]
Calculate the power dissipation in the 5V LDO, V5, using the following equation:
P5 = (V
where I5 includes the I
LDOIN
LDO33
- V5) × I
5
current sourced from
LDO33.
Calculate the power dissipated in the 3.3V LDO, LDO33, using the following equation:
P
LDO33
= 1.7V × I
LDO33
Calculate the quiescent power dissipation in the device using the following equation:
PQ = ICC × V
CC
If the current sinks are enabled, calculate their associ­ated power dissipation as:
P
CLCQ
P
CLDI
= I
= I
LLM_C/Q
LLM_DI
× V
× V
C/Q
DI

Overtemperature Warning

Two bits in the Status and Mode registers are set when the temperature of the device exceeds +115NC (typ). The OTempInt bit in the Status register is set and IRQ asserts when the OTemp bit in the Mode register is set. Read the Status register to clear the OTempInt bit and IRQ.
The OTemp bit is cleared when the die temperature falls below +95NC.
The device continues to operate normally unless the die temperature reaches the +150NC thermal shutdown threshold, when the device enters thermal shutdown.

Thermal Shutdown

When the die temperature rises above +150NC (typ) ther­mal shutdown threshold, the C/Q drivers and the C/Q and DI current loads are automatically turned off. The internal
3.3V and 5V LDOs remain on during thermal shutdown, if enabled. If the internal or external V5 supply remains on during thermal shutdown (which is always true in case of the internal V5 regulator), the register contents are main­tained and SPI communication available.
When the die temperature falls below the thermal shut­down threshold plus hysteresis, the C/Q driver and C/Q and DI current sinks turn on automatically.
17
MAX14824
IO-Link Master Transceiver

Register Functionality

The device has four 8-bit-wide registers for configuration and monitoring (Table 1). R1 and R0 are the register address.

Table 1. Register Summary

REGISTER R1 R0 D7 D6 D5 D4 D3 D2 D1 D0
Status 0 0 X X DiLvl
CQConfig 0 1 RxFilter HiSlew C/Q_N/P C/Q_PP C/QDEn Q RxDis C/QLoad
DIOConfig 1 0 X X X X X X LiDis DiLoad
Mode 1 1 RST WuEnBit X C/QFault UV24 OTemp UV33En LDO33Dis
R1/R0 = Register address, X = Unused bits.
Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Read/Write POR State Reset Upon Read
X = Unused bits. U = Unknown. These bits are dependent on the DI logic and C/Q inputs.
X X DiLvl R R R R R R R R 0 0 U U 0 0 0 0
Yes Yes No No Yes Yes Yes Yes
QLvl
QLvl
C/QFaultInt UV33Int UV24Int OTempInt

Status Register [R1, R0] = [0,0]

C/QFaultInt UV33Int UV24Int OTempInt
The Status register reflects the logic levels of C/Q and DI and shows the source of interrupts that cause an IRQ hardware interrupt. The IRQ interrupt is asserted when an alarm condition (OTemp, UV33En, UV24, C/QFault) is detected. All bits in the Status register are read-only. The interrupt bits return to the default state after the Status register is read. If a C/Q fault condition persists, the C/QFaultInt bit is immediately set after the Status register is read.
BIT NAME DESCRIPTION
D7:D6 X
D5 DiLvl DI Logic Level. The DiLvl bit mirrors the current logic level at the DI input. It is the
D4
D3 C/QFaultInt C/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register)
QLvl C/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the
Unused
inverse of the LI output and is always active regardless of the state of the LiDis bit (Table 2). DiLvl does not affect IRQ. DiLvl is not changed when the Status register is read.
C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3).
QLvl remains active when the C/Q receiver is disabled (RxDis = 1). QLvl does not affect IRQ. QLvl is not changed when the Status register is read.
are set when a short circuit or voltage fault occurs on the C/Q driver output (see the C/Q Fault Detection section for more information). IRQ asserts when C/QFault is 1. Read the
Status register to clear the C/QFaultInt bit and deassert IRQ.
18
IO-Link Master Transceiver
BIT NAME DESCRIPTION
MAX14824
D2 UV33Int Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and
D1 UV24Int VCC Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode
D0 OTempInt Overtemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode
the UV33En bit (in the Mode register) are set when V undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ.
Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV deasserts when V
rises above the LDO33 undervoltage threshold.
LDO33
register) are set when the VCC voltage falls below the 7.4V undervoltage threshold. IRQ asserts low when the UV24Int bit is 1. Read the Status register to clear the UV24Int bit and deassert IRQ. VCC undervoltage detection cannot be disabled.
register) are set when a high-temperature condition is detected by the device. OTemp is set when the temperature of the die exceeds +115NC (typ). OTempInt is set and IRQ asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ deasserts when the Status register is read.
Once cleared, OTempInt is not reset if the die temperature remains above the thermal warning threshold and does not fall below +95°C.
falls below the 2.4V LDO33
LDO33

Table 2. DiLvl and LI Output Table 3. QLvl and RX Output

V
(V) DiLvl BIT LI OUTPUT
DI
< 5.2 0 High
> 8 1 Low
V
(V)
C/Q
< 8 1 High
>13 0 Low
QLvl BIT
RX OUTPUT
19
MAX14824
IO-Link Master Transceiver

CQConfig Register [R1, R0] = [0,1]

Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Read/Write POR State
Use the CQConfig register to control the C/Q receiver and driver parameters. All bits in the CQConfig register are read-write and are set to 0 at power-up.
BIT NAME DESCRIPTION
D7 RxFilter C/Q and DI Receiver Filter Control. The C/Q and DI receivers have analog
D6 HiSlew Slew-Rate Control. The HiSlew bit increases the slew rate for the C/Q driver
D5 C/Q_N/P C/Q Driver NPN/PNP Mode. The C/Q_N/P bit selects between low-side (NPN)
RxFilter HiSlew C/Q_N/P C/Q_PP C/QDEn Q RxDis C/QLoad
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
lowpass filters to reduce high-frequency noise on the receiver inputs. Set the RxFilter bit to 0 to set the filter corner frequency to 500kHz. Set the RxFilter bit to 1 to set the filter corner frequency to 1MHz (this setting is used for high­speed COM3 operation).
Noise filters on C/Q and DI are controlled simultaneously by the RxFilter bit.
and is used for high-speed COM3 (230kbps) data rates. Set HiSlew to 0 for COM1 and COM2 operation.
and high-side (PNP) modes when the C/Q driver is configured as an open­drain output (C/Q_PP = 0). Set C/Q_N/P to 1 to configure the driver for low­side (NPN) operation. Set C/Q_N/P to 0 for high-side (PNP) operation.
D4 C/Q_PP C/Q Driver Push-Pull Operation. Set C/Q_PP to 1 to enable push-pull opera-
tion on the C/Q driver. The C/Q output is open drain when C/Q_PP is 0.
D3 C/QDEn C/Q Driver Enable/Disable. Set the C/QDEn bit to 1 to enable the C/Q driver.
Set C/QDEn to 0 for hardware (TXEN) control. See Table 4.
D2 Q C/Q Driver Output Logic. The Q bit can be used to program the C/Q output
driver through software. The C/Q driver must be enabled and TXC = TXQ must be high to control the C/Q driver through the Q bit (Figure 8). C/Q has the same logic polarity as the Q bit.
Set the Q bit to 0 to control the C/Q driver with TXC and TXQ.
The C/Q driver output state depends on the C/Q_PP and C/Q_N/P bits as shown in Table 5. Note that Table 5 assumes that the C/Q driver is enabled (TXEN = VL or C/QDEn = 1).
D1 RxDis C/Q Receiver Enable/Disable. Set the RxDis bit to 1 to disable the C/Q
receiver. The RX output is high when RxDis is 1.
D0 C/QLoad C/Q Current Sink Enable. Set the C/QLoad bit to 1 to enable the internal cur-
rent sink at C/Q. The C/Q current sink is automatically disabled while the C/Q driver is enabled (TXEN = high or C/QDEn = 1). This saves power.
20

Table 4. C/QDEn and TXEN C/Q Driver Control

C/QDEn TXEN C/Q DRIVER
0 Low Disabled X High Enabled 1 X Enabled
X = Don’t care.

Table 5. C/Q Driver Output State

MAX14824
IO-Link Master Transceiver
TXQ TXC
Q

Figure 7. Equivalent C/Q Logic

C/Q
TXC AND TXQ
(SEE NOTE)
High 1 0 0 PNP, open drain On, C/Q is high High 0 0 0 PNP, open drain Off, C/Q is high impedance High 1 0 1 NPN, open drain Off, C/Q is high impedance High 0 0 1 NPN, open drain On, C/Q is low High 1 1 X Push-pull High High 0 1 X Push-pull Low
Note: TXC and TXQ = VL. X = Don’t care.
Q C/Q_PP C/Q_N/P C/Q CONFIGURATION C/Q STATE

DIOConfig Register [R1, R0] = [1,0]

Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Read/Write POR State
X = Unused bits.
X X X X X X LiDis DiLoad
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
Use the DIOConfig register to control the DI and DO interfaces. All bits in the DIOConfig register are read-write and are set to 0 at power-up.
BIT NAME DESCRIPTION
D7:D2 X Unused
D1 LiDis LI Output Enable/Disable. Set the LiDis bit to 1 to disable the LI output.
The LI output is low when LiDis is 1.
D0 DiLoad DI Current Sink Enable. Set the DiLoad bit to 1 to enable the internal
current sink at the DI input.
21
MAX14824
IO-Link Master Transceiver

Mode Register [R1, R0] = [1,1]

Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Read/Write POR State
X = Unused bits.
Use the Mode register to reset the device and manage the 3.3V LDO. The Mode register has bits that represent the current status of fault conditions. When writing to the Mode register, the contents of the fault indication bits (bits 2 to 4) do not change.
BIT NAME DESCRIPTION
D7 RST Register Reset. Set RST to 1 to reset all registers to their default power-up state. Then
D6 WuEnBit Auto Wake-Up Polarity Enable. Drive the WUEN input high or set the WuEnBit bit to 1
RST WuEnBit X C/QFault UV24 OTemp UV33En LDO33Dis R/W R/W R/W R R R R/W R/W
0 0 0 0 0 0 0 0
set RST to 0 for normal operation.
The Status register is cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts are not generated while RST = 1.
to enable wake-up generation. When auto wake-up polarity is enabled, the device sam­ples the logic state of C/Q and uses this as the basis for determining the subsequent wake-up pulse that is initiated through a high-to-low pulse on the TXQ and TXC inputs.
Set the WuEnBit to 1 before a negative-going, 80µs (typ) wake-up pulse is transmitted to ensure that the device produces the correct polarity wake-up pulse on the C/Q output. For example, if C/Q is connected to a voltage high, then it pulls the line low for the wake­up pulse duration. If C/Q is connected to a voltage low, then it pulls the line high for the wake-up pulse duration. Clear WuEnBit after the wake-up has been generated (Table 6).
D5 X D4 C/QFault C/Q Fault Status. The C/QFault bit is set when a short circuit or voltage fault occurs at
D3 UV24 VCC Undervoltage Condition. Both the UV24 and the UV24Int bits are set when VCC
D2 OTemp Temperature Warning. The OTemp bit is set when a high-temperature condition
D1 UV33En LDO33 UV Enable. Set the UV33En bit to 1 to assert the UV output when LDO33 volt-
D0 LDO33Dis LDO33 Enable/Disable. Set LDO33Dis to 1 to disable the 3.3V linear regulator (LDO33).
Unused
the C/Q driver output (see the C/Q Fault Detection section for more information). The C/QFault and C/QFaultInt bits are both set when a fault occurs on C/Q. C/QFault is cleared when the fault is removed.
falls below V must be present for VCC undervoltage monitoring.
occurs on the device. Both the OTempInt interrupt in the Status register and the OTemp bit are set when the junction temperature of the die rises to above +115NC (typ). The OTemp bit is cleared when the junction temperature falls below +95NC (typ).
age falls below the 2.4V (typ) undervoltage lockout threshold. The UV33En bit does not affect the UV33Int bit in the Status register; IRQ asserts when V V
LDO33UVLO
CCUVLO
. UV24 is cleared when VCC rises above the V
regardless of the state of UV33En.
threshold. V5
CC
falls below
LDO33
22
IO-Link Master Transceiver

Table 6. Auto Wake-Up Polarity Generation

WuEnBit WUEN MODE
0 Low Normal operation 0 High Wake-up generation mode 1 Low Wake-up generation mode 1 High Wake-up generation mode
MAX14824

SPI Interface

The device communicates through an SPI-compatible 4-wire serial interface. The interface has three inputs— clock (SCLK), chip select (CS), and data in (SDI)—and one output, data out (SDO). The maximum SPI clock rate
CS
SCLK
SDI
W0A3 A2 A1 A0
A_ = DEVICE ADDRESS R_ = REGISTER ADDRESS D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED

Figure 8. SPI Write Cycle

CS
R1
for the device is 12MHz. The SPI interface complies with clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 8 and Figure 9).
The SPI interface is not available when V5 or VL is not present.
R0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
SDI 0R
SDO
A_ = DEVICE ADDRESS R_ = REGISTER ADDRESS D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED
= CLOCK EDGE AT WHICH LOGIC IS WRITTEN

Figure 9. SPI Read Cycle

R1 R0A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
XX
23
MAX14824
IO-Link Master Transceiver

Address Selection

The device includes four chip-select address inputs, A0–A3, allowing up to 16 devices on a single bus. Drive the address inputs high or low to program the device address as shown in Table 7. Do not leave any address input unconnected.

Table 7. Address Input Selection

A3 A2 A1 A0 DEVICE ADDRESS
Low Low Low Low 0x00 Low Low Low High 0x01 Low Low High Low 0x02 Low Low High High 0x03 Low High Low Low 0x04 Low High Low High 0x05 Low High High Low 0x06
Low High High High 0x07 High Low Low Low 0x08 High Low Low High 0x09 High Low High Low 0x0A High Low High High 0x0B High High Low Low 0x0C High High Low High 0x0D High High High Low 0x0E High High High High 0x0F

Applications Information

UART Interfacing

The logic level of the MAX14824 microcontroller’s UART interface I/Os (TXC, TXQ, TXEN, and RX) is defined by VL.
The device can be interfaced to microcontrollers whose on-board UART TX output cannot be programmed as a logic output (GPO). In this case, connect the TX output of the UART to the TXC input for IO-Link communication and connect a separate GPO output on the microcon­troller to TXQ for standard IO (SIO) mode operation (Figure 10). As the TXQ and TXC inputs are internally logically ANDed, the unused input (TXC or TXQ) must be held high while the other is in operation.

Transient Protection

Inductive load switching, surges, ESD and short circuits create high transient voltages. C/Q and DI must be pro­tected against high overvoltage and undervoltage tran­sients. Positive voltage transients on DI must be limited to +55V relative to GND and negative voltage transients must be limited to -55V (relative to GND) on DI. Two Schottky diodes having low forward voltage, like the DLFS240, must be connected to C/Q to clamp under- and overvoltage transients. Figure 11 shows suitable protection to meet IEC 61000-4-2 ESD testing. For reduction of bit errors induced by burst transients, enable the receiver filters and add capacitors to C/Q and DI. If surge tests need to be met, a TVS diode is recommended on V
CC.
MICROCONTROLLER

Figure 10. UART Interface

TXQGPO
TXCTX
TXENRTS
RXRX
MAX14824
1µF
270pF
V
CC
C/Q
270pF
MAX14824
DI
1nF
GND

Figure 11. MAX14824 Operating Circuit with TVS Protection

DFLS240
DFLS240
SDC36C
24
3.3V
10kΩ
EN
IN
MAX17501
GND
MAX14824
IO-Link Master Transceiver
LX
FB
1μF 1μF
V
CC
MICROCONTROLLER
GND
SPI
UVGPIO2
WUENGPIO1
RXRX
TXCTX
TXENRTS
LIGPIO3
MAX14824

Figure 12. Use an External Supply to Power the MAX14824

External Power

The device is powered by VCC and the 5V regulator, V5. VL is a reference voltage input to set the logic levels of the microcontroller interface. The logic and SPI interface are operational when V5 and VL are present even if VCC is not present.
V
LDO33VLTXQ
GND
5
LDOIN
V
C/Q
CC
270pF
270pF
DI
1nF
L+
1
2
4
3
L-
Connect LDOIN to V5 to power the V5 input with an external supply (Figure 12). This configuration disables operation of the internal 5V regulator and reduces power consumption.
25
MAX14824
IO-Link Master Transceiver
Typical Operating Circuits (continued)
CONTROLLER
V
EXT
MISO
MOSI
SCLK
CS1
CS2
RST
GPIO1
GPIO5
GPIO9
GPIO13
MAX14830
IO-LINK QUAD MASTER APPLICATION
MAX14824
PORT 1
RX TXC TXEN
ADDR 1
MAX14824
MISOMOSISCLKCSRST
TX0
RX0
RTS0
TX1
RX1
RTS1
TX2
RX2
RTS2
TX3
RX3
RTS3
XOUTXIN
RX TXC TXEN
ADDR 2
MAX14824
RX TXC TXEN
ADDR 3
PORT 2
PORT 3
RX TXC TXEN
MAX14824
PORT 1
ADDR 4
26
MAX14824
IO-Link Master Transceiver

Ordering Information

PART TEMP RANGE PIN-PACKAGE
MAX14824GTG+
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
-40NC to +105NC
24 TQFN-EP*

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
24 TQFN-EP T2444+4
PACKAGE
CODE
OUTLINE
NO.
21-0139 90-0022
LAND
PATTERN NO.
27
MAX14824
IO-Link Master Transceiver

Revision History

REVISION
NUMBER
0 3/11 Initial release —
1 6/11
2 8/11
3 5/12
REVISION
DATE
DESCRIPTION
Changed DI threshold to accommodate all three types of industrial sensors, added 24V supply connection in Figure 13
Corrected IO-Link trademark. Corrected block description in Functional Diagram. Corrected C/Q minimum and maximum ratings in the Absolute Maximum Ratings section. Corrected ICC maximum value and shuffled row parameters in the Electrical Characteristics Table. Replaced Figures 9 and 10. Added Maxim part number for DC-DC regulator. Corrected Transient Protection section.
Changed temperature rating; updated Typical Operating Circuits, Functional Diagram, and Figures 9, 11, and 12; updated TOCs 1, 2, and 16; changed parameters in Electrical Characteristics; updated Detailed Description and
Application Information
PAGES
CHANGED
4, 19, 25
1, 2, 3, 23, 24
1-7, 11, 13-17, 20, 23, 24, 24,
25, 27
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 28
©
2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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