Maxim MAX1478C-D, MAX1478AAE Datasheet

General Description

The MAX1478 highly integrated, analog sensor signal
processor is optimized for piezoresistive sensor calibra­tion and compensation without any external compo­nents. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-bit internal EEPROM, and four 12-bit digi­tal-to-analog converters (DACs). Achieving a total error
factor within 1% of the sensor’s repeatability errors, the
MAX1478 compensates offset, offset temperature coeffi­cient, full-span output (FSO), FSO temperature coeffi­cient (FSO TC), and FSO nonlinearity of silicon
piezoresistive sensors.

The MAX1478 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal via DACs, thereby eliminating the quan­tization noise associated with digital signal path solu­tions. Built-in testability features on the MAX1478 result
in the integration of three traditional sensor-manufactur­ing operations into one automated process:

• Pretest: Data acquisition of sensor performance

under the control of a host test computer.

• Calibration and compensation: Computation and

storage (in an internal EEPROM) of calibration and
compensation coefficients computed by the test
computer and downloaded to the MAX1478.

• Final test operation: Verification of transducer cali-

bration and compensation without removal from the
pretest socket.

Although optimized for use with piezoresistive sensors,
the MAX1478 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.

______________________Customization

For high-volume applications, Maxim can customize the
MAX1478 for unique requirements. With a dedicated
cell library consisting of more than 90 sensor-specific
functional blocks, Maxim can quickly provide cus­tomized MAX1478 solutions.

________________________Applications

Piezoresistive Pressure and Acceleration
Transducers and Transmitters
Manifold Absolute Pressure (MAP) Sensors
Automotive Systems
Hydraulic Systems
Industrial Pressure Sensors
Strain-Gauge Sensors
Industrial Temperature Sensors

Features

♦ Medium Accuracy (±1%), Single-Chip Sensor

Signal Conditioning

♦ Rail-to-Rail®Output

♦ Sensor Errors Trimmed Using Correction

Coefficients Stored in Internal EEPROM—
Eliminates Laser Trimming and Potentiometers

♦ Compensates Offset, Offset TC, FSO, FSO TC,

and FSO Linearity

♦ Programmable Current Source (0.1mA to 2.0mA)

for Sensor Excitation

♦ Fast Signal-Path Settling Time (<1ms)

♦ +5V Single Supply

♦ Accepts Sensor Outputs from +10mV/V to

+40mV/V

♦ Fully Analog Signal Path

Pilot Production System

To simplify your pressure sensor design, Maxim has
developed a fully automated pilot production system
that will smooth the difficult transition from prototype to
production. Details appear at the end of this data sheet.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

________________________________________________________________ Maxim Integrated Products 1

19-1538; Rev 0; 9/99

*Dice are tested at TA= +25°C, DC parameters only.

Functional Diagram appears at end of data sheet.

Pin Configuration

Ordering Information

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

PART

MAX1478C/D

MAX1478AAE -40°C to +125°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

Dice*

16 SSOP

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

EVALUATION KIT

AVAILABLE

TOP VIEW

1

SCLK I.C.

CS

2

I.C.

3

MAX1478

4

TEMP

FSOTC

5

DIO

6

WE

7

V

8

SS

SSOP

16

15

14

13

12

11

10

9

V

DD

INM

BDRIVE

INP

I.C.

OUT

ISRC

MAX1478

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage, VDDto VSS......................................-0.3V to +6V

All Other Pins ...................................(V

SS

- 0.3V) to (VDD+ 0.3V)

Short-Circuit Duration, FSOTC, OUT, BDRIVE ...........Continuous

Continuous Power Dissipation (T

A

= +70°C)

16-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW

Operating Temperature Range

MAX1478AAE .................................................-40°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

PARAMETER

SYMBOL MIN TYP MAX UNITS

Amplifier Gain Nonlinearity 0.01 %V

DD

Input-Referred Offset Tempco ±0.5 µV/°C

Input Impedance R

IN

1 MΩ

Output Step Response 1 ms

Common-Mode Rejection Ratio CMRR 90 dB

Input-Referred Adjustable Offset
Range

±150 mV

Supply Voltage V

DD

4.5 5.0 5.5 V

Supply Current I

DD

36mA

Input-Referred Adjustable FSO
Range

10 to 40 mV/V

Differential-Signal Gain Range 41 to 230 V/V

Minimum Differential Signal Gain 36 41 45 V/V

Differential-Signal Gain Tempco ±50 ppm/°C

Output Current Range

-0.45 0.45

(sink) (source)

mA

Output Noise 500 µV

RMS

CONDITIONS

(Note 5)

(Notes 2, 3)

63% of final value

Selectable in eight steps

TA= T

MIN

to T

MAX

From VSSto V

DD

At minimum gain (Note 4)

V

OUT

= (VSS+ 0.25V) to (VDD- 0.25V)

DC to 10Hz (gain = 41, source
impedance = 5kΩ)

(Note 1)

Output Voltage Swing VSS+ 0.05 V

DD -

0.05 VNo load

GENERAL CHARACTERISTICS

ANALOG INPUT (PGA)

ANALOG OUTPUT (PGA)

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)

Note 1: Excludes the sensor or load current.
Note 2: All electronics temperature errors are compensated together with sensor errors.
Note 3: The sensor and the MAX1478 must always be at the same temperature during calibration and use.
Note 4: This is the maximum allowable sensor offset.
Note 5: This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge

voltage of 2.5V.

Note 6: Bit weight is ratiometric to V

DD

.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

_______________________________________________________________________________________ 3

Typically 4600ppm/°C tempco

V

FSOTC

= 2.5V

No load

Input referred, VDD= 5V (Note 6)

CONDITIONS

kΩ100R

TEMP

Temperature-Dependent
Resistor

kΩ75R

FTC

FSO Trim Resistor

kΩ75R

ISRC

Current-Source Reference
Resistor

VV

SS

+ 1.3 VDD- 1.3V

BDRIVE

Bridge Voltage Swing

mA0.1 0.5 2.0I

BDRIVE

Bridge Current Range

µA-20 20Current Drive

VV

SS

+ 0.3 VDD- 1.3Output Voltage Swing

Bits3DAC Resolution

mV/bit9DAC Bit Weight

UNITSMIN TYP MAXSYMBOLPARAMETER

LSB±1.5DNLDifferential Nonlinearity

Bits12DAC Resolution

VV

SS

+ 1.3 VDD- 1.3V

ISRC

Reference Input Voltage Range
(ISRC)

DAC reference = V

BDRIVE

= 2.5V

DAC reference = VDD= 5.0V

mV/bit1.4

∆V

OUT

∆Code

Offset TC DAC Bit Weight

mV/bit2.8

∆V

OUT

∆Code

Offset DAC Bit Weight

DAC reference = V

BDRIVE

= 2.5V

DAC reference = VDD= 5.0V

mV/bit0.6

∆V

FSOTC

∆Code

FSO TC DAC Bit Weight

mV/bit1.22

∆V

ISRC

∆Code

FSO DAC Bit Weight

CURRENT SOURCE

DIGITAL-TO-ANALOG CONVERTERS

IRO DAC

FSOTC BUFFER

INTERNAL RESISTORS

_______________Detailed Description

The MAX1478 provides an analog amplification path for
the sensor signal. Calibration and temperature com­pensation are achieved by varying the offset and gain
of a programmable-gain amplifier (PGA) and by varying
the sensor bridge current. The PGA uses a switched­capacitor CMOS technology, with an input-referred
coarse offset trimming range of approximately ±63mV
(9mV steps). An additional output-referred fine offset
trim is provided by the Offset DAC (approximately

2.8mV steps). The PGA provides eight gain values from
+41V/V to +230V/V. The bridge current source is pro­grammable from 0.1mA to 2mA.

The MAX1478 uses four 12-bit DACs and one 3-bit
DAC, with calibration coefficients stored by the user in

an internal 128-bit EEPROM. This memory contains the
following information as 12-bit-wide words:

• Configuration register

• Offset calibration coefficient

• Offset temperature error-compensation coefficient

• FSO (full-span output) calibration coefficient

• FSO temperature error-compensation coefficient

• 24 user-defined bits for customer programming of

manufacturing data (e.g., serial number and date)

Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and FSO values as a func­tion of voltage.

MAX1478

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

4 _______________________________________________________________________________________

Pin Description

Positive Power-Supply Input. Connect a 0.1µF capacitor from VDDto V

SS.

V

DD

15

Current-Source Reference. An internal 75kΩ resistor (R

ISRC

) connects ISRC to VSS(see Functional

Diagram). Optionally, external resistors can be used in place of or in parallel with R

FTC

and R

ISRC

.

ISRC9

PGA Output VoltageOUT10
Positive Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.INP12

Sensor Excitation Current Output. This current source drives the bridge.BDRIVE13
Negative Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.INM14

Buffered FSOTC DAC Output. An internal 75kΩ resistor (R

FTC

) connects FSOTC to ISRC (see Functional

Diagram). Optionally, external resistors can be used in place of or in parallel with R

FTC

and R

ISRC

.

FSOTC5

Data Input/Output. Used only during programming/testing. Internally pulled to VSSwith a 1MΩ (typical)
resistor. High impedance when CS is low.

DIO6

Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set the DAC refresh­rate mode. Internally pulled to V

DD

with a 1MΩ (typical) resistor. See the Chip-Select (CS) and Write-Enable

(WE) section.

WE7

Negative Power-Supply InputV

SS

8

Temperature Sensor Output. An internal temperature sensor (a 100kΩ, 4600ppm/°C TC resistor) that can
provide a temperature-dependent voltage.

TEMP4

Internally Connected. Leave unconnected.I.C.

3, 11,

16

PIN

Chip-Select Input. The MAX1478 is selected when this pin is high. When low, OUT and DIO become high
impedance. Internally pulled to V

DD

with a 1MΩ (typical) resistor. Leave unconnected for normal operation.

CS2

Data Clock Input. Used only during programming/testing. Internally pulled to VSSwith a 1MΩ (typical) resis­tor. Data is clocked in on the rising edge of the clock. The maximum SCLK frequency is 10kHz.

SCLK1

FUNCTIONNAME

FSO TC Compensation

Silicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
(V

BDRIVE

) increases with temperature. This depen-

dence of V

BDRIVE

on the sensor temperature can be
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensi­tivity tempco (TCS) so that, with constant voltage exci­tation, FSO will decrease with temperature, causing a
full-span output temperature coefficient (FSO TC) error.
However, if the bridge voltage can be made to increase
with temperature at the same rate that TCS decreases
with temperature, the FSO will remain constant.

FSO TC compensation is accomplished by resistor
R

FTC

and the FSOTC DAC, which modulate the excita­tion reference current at ISRC as a function of tempera­ture (Figure 3). FSO DAC sets V

ISRC

and remains
constant with temperature, while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The reference DAC voltage is
V

BDRIVE

, which is temperature dependent. The FSOTC
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSO TC errors are
compensated and FSO will be constant with tempera­ture.

Offset TC Compensation

Compensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
the percentage of the temperature-dependent voltage
V

BDRIVE

that must be added to the output summing

junction to correct the error. Use the Offset TC DAC to
adjust the amount of BDRIVE voltage that is added to
the output summing junction (Figure 2).

Analog Signal Path

The fully differential analog signal path consists of four
stages:

• Front-end summing junction for coarse offset correction

• 3-bit PGA with eight selectable gains ranging from

41 through 230

• Three-input-channel summing junction

• Differential to single-ended output buffer (Figure 2)

Coarse Offset Correction

The sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR >90dB, an input impedance of approxi­mately 1MΩ, and a common-mode input voltage range
from VSSto VDD. At this summing junction, a coarse off­set-correction voltage is added, and the resultant volt­age is fed into the PGA. The 3-bit (plus sign)
input-referred Offset DAC (IRO DAC) generates the
coarse offset-correction voltage. The DAC voltage ref­erence is 1.25% of V

DD

; thus, a VDDof 5V results in a
front-end offset-correction voltage ranging from -63mV
to +63mV, in 9mV steps (Table 1). To add an offset to
the input signal, set the IRO sign bit high; to subtract an
offset from the input signal, set the IRO sign bit low.
The IRO DAC bits (C2, C1, C0, and IRO sign bit) are
programmed in the configuration register (see Internal
EEPROM section).

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

_______________________________________________________________________________________ 5

Figure 1. Typical Pressure-Sensor Output

Figure 2. Signal-Path Block Diagram

4.5

FULL-SPAN OUTPUT (FSO)

VOLTAGE (V)

0.5

OFFSET

P

MIN

P

MAX

PRESSURE

FULL SCALE (FS)

1.25% V

DD

IRO

DAC

INP

INM

BDRIVE

A2

V

A1 A0

PGA

DD

OFFTC

DAC

OFFSET

DAC

A = 2.3

A = 2.3

SOTC

±

OUT

ΣΣ

A = 1

±

SOFF

MAX1478

Table 1. Input-Referred Offset DAC
Correction Values

Programmable-Gain Amplifier

The PGA, which is used to set the coarse FSO, uses a
switched-capacitor CMOS technology and contains
eight selectable gain levels from 41 to 230, in incre­ments of 27 (Table 2). The output of the PGA is fed to
the output summing junction. The three PGA gain bits
A2, A1, and A0 are stored in the configuration register.

Output Summing Junction

The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and offset TC correction. Both the offset and the offset
TC correction voltages are multiplied by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset
sign bit and offset TC sign bit are stored in the configu­ration register. The offset sign bit determines if the off­set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the
offset TC sign bit. Alternately, positive offset TC errors
dictate a logic low for the offset TC sign bit. The output
of the summing junction is fed to the output buffer.

Output Buffer

OUT can drive 0.1µF of capacitance. The output is cur­rent limited and can be shorted to either V

DD

or V

SS

indefinitely. OUT can both source and sink current. A
load can be driven to either rail. The output can swing

very close to either supply while maintaining its
accuracy and stability. Maxim recommends putting a

0.1µF capacitor on the OUT pin in noisy environments.

Bridge Drive

Fine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 3). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor R

ISRC

and by the voltage at node ISRC (con­trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (current
mirror gain AA ≅ 14) and then made available at
BDRIVE for sensor excitation. Modulation of this current
with respect to temperature can be used to correct
FSOTC errors, while modulation with respect to the out­put voltage (V

OUT

) can be used to correct FSO linearity

errors.

Digital-to-Analog Converters

The four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.

Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from VDDand controls V

ISRC

which, in conjunction with R

ISRC

, sets the baseline sen­sor excitation current. The Offset DAC also takes its ref­erence from VDDand provides a 1.22mV resolution with

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

6 _______________________________________________________________________________________

+7 1 1 1

IRO DAC

1

OFFSET

CORREC-

TION

% of V

DD

(%)

+1.25

OFFSET

CORREC-

TION AT

V

DD

= 5V

(mV)

+63

SIGN C1C2 C0VALUE

+6 1 1 1 0 +1.08 +54

+5 1 1 0 1 +0.90 +45

+4 1 1 0 0 +0.72 +36

+3 1 0 1 1 +0.54 +27

+2 1 0 1 0 +0.36 +18

+1 1 0 0 1 +0.18 +9

+0 1 0 0 0

0

0

-0 0 0 0 0

-1 0 0 0 1 -0.18 -9

-2 0 0 1 0 -0.36 -18

-3 0 0 1 1 -0.54 -27

-4 0 1 0 0 -0.72 -36

-5 0 1 0 1 -0.90 -45

-6 0 1 1 0 -1.08 -54

-7 0 1 1 1 -1.25 -63

A1

0 0 0

A2 A0

PGA

VALUE

0

PGA

GAIN

(V/V)

41

OUTPUT­REFERRED IRO
DAC STEP SIZE

(V

DD

= 5V) (V)

0.369

1 0 0 1 68 0.612

2 0 1 0 95 0.855

3 0 1 1 122 1.098

4 1 0 0 149 1.341

5 1 0 1 176 1.584

6 1 1 0 203 1.827

7 1 1 1 230 2.070

Table 2. PGA Gain Settings and IRO DAC
Step Size

0

0