General Description
The MAX1473 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz
frequency range. Its signal range is from -114dBm to
0dBm. With few external components and a low-current
power-down mode, it is ideal for cost- and power-sensitive applications typical in the automotive and consumer
markets. The chip consists of a low-noise amplifier
(LNA), a fully differential image-rejection mixer, an onchip phase-locked-loop (PLL) with integrated voltagecontrolled oscillator (VCO), a 10.7MHz IF limiting
amplifier stage with received-signal-strength indicator
(RSSI), and analog baseband data-recovery circuitry.
The MAX1473 also has a discrete one-step automatic
gain control (AGC) that drops the LNA gain by 35dB
when the RF input signal is greater than -57dBm.
The MAX1473 is available in 28-pin TSSOP and 32-pin
thin QFN packages. Both versions are specified for the
extended (-40°C to +85°C) temperature range.
Applications
Automotive Remote Keyless Entry Security Systems
Garage Door Openers Home Automation
Remote Controls Local Telemetry
Wireless Sensors
Systems
Features
o Optimized for 315MHz or 433MHz ISM Band
o Operates from Single 3.3V or 5.0V Supplies
o High Dynamic Range with On-Chip AGC
o Selectable Image-Rejection Center Frequency
o Selectable x64 or x32 fLO/f
XTAL
Ratio
o Low 5.2mA Operating Supply Current
o < 2.5µA Low-Current Power-Down Mode for
Efficient Power Cycling
o 250µs Startup Time
o Built-In 50dB RF Image Rejection
o Receive Sensitivity of -114dBm
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
________________________________________________________________
Maxim Integrated Products
1
Pin Configurations
Ordering Information
19-2748; Rev 6; 1/12
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX1473EUI+ -40°C to +85°C 28 TSSOP
MAX1473ETJ+ -40°C to +85°C 32 Thin QFN-EP*
TOP VIEW
XTAL1
AVDD
LNAIN
LNASRC
AGND
LNAOUT
AVDD
MIXIN1
MIXIN2
AGND
IRSEL
MIXOUT
DGND
DVDD
+
1
2
3
4
5
MAX1473
6
7
8
9
10
11
12
13
14
TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTAL2
PWRDN
PDOUT
DATAOUT
V
DD5
DSP
DFFB
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
AGCDIS
AGND
LNAOUT
AVDD
MIXIN1
MIXIN2
AGND
IRSEL
AVDD
XTAL1
30
29
MAX1473
11
12
DVDD
AGCDIS
XTAL2
28
13
N.C.
LNASRC
LNAIN
32
9
MIXOUT
31
10
DGND
+
1N.C.
2
3
4
5
6
7
8
THIN QFN
PWRDN
PDOUT
25 N.C.
27
26
24 DATAOUT
23
V
DD5
22
DSP
21
N.C.
20
DFFB
19
OPP
18
DSN
17
DFO
16IFIN2
14
15
IFIN1
XTALSEL
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS (3.3V OPERATION)
(
Typical Application Circuit
, VDD= 3.0V to 3.6V, no RF signal applied, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at V
DD
= 3.3V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD5
to AGND.......................................................-0.3V to +6.0V
AVDD to AGND .....................................................-0.3V to +4.0V
DVDD to DGND .....................................................-0.3V to +4.0V
AGND to DGND.....................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL, AGCDIS,
PWRDN to AGND .....................................-0.3V to (V
DD5
+ 0.3V)
All Other Pins to AGND ..............................-0.3V to (V
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .1025.6mW
32-Pin Thin QFN (derate 21.3mW/°C
above +70°C).........................................................1702.1mW
Operating Temperature Ranges
MAX1473E__ ..................................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Supply Voltage V
Supply Current I
Shutdown Supply Current I
Input Voltage Low V
Input Voltage High V
Input Logic Current High I
DATAOUT Voltage Output Low V
DATAOUT Voltage Output High V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DD
DD
PWRDN
IH
OL
OH
3.3V nominal supply 3.0 3.3 3.6 V
fRF = 315MHz 5.2 6.23
DD
fRF = 433MHz 5.8 6.88
fRF = 315MHz 1.6
f
= 433MHz 2.5 5.3
RF
VDD - 0.4 V
= V
IRSEL
IRSEL
IRSEL
DD
= VDD/2 1.1 VDD - 1.5Image Reject Select (Note 2)
= 0V 0.4
V
DD
- 0.4 V
IL
IH
V
V
V
fRF = 433MHz, V
fRF = 375MHz, V
f
RL = 5kΩ
= V
P WRDN
= 0V,
P WRDN
= 0V
XTALSEL
= 315MHz, V
RF
0.4 V
10 µA
VDD - 0.4
0.4 V
mA
µA
V
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (5.0V OPERATION)
(
Typical Application Circuit
, VDD= 4.5V to 5.5V, no RF signal applied, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at V
DD
= 5.0V and TA= +25°C.) (Note 1)
AC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, VDD= 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF= 315MHz, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at V
DD
= 3.3V and TA= +25°C.) (Note 1).
Supply Voltage V
Supply Current I
Shutdown Supply Current I
Input Voltage Low V
Input Voltage High V
Input Logic Current High I
DATAOUT Voltage Output Low V
DATAOUT Voltage Output High V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DD
DD
PWRDN
IH
OL
OH
5.0V nominal supply 4.5 5.0 5.5 V
fRF = 315MHz 5.2 6.04
DD
fRF = 433MHz 5.7 6.76
fRF = 315MHz 2.3
f
= 433MHz 2.8 6.2
RF
VDD - 0.4 V
= V
IRSEL
IRSEL
IRSEL
DD
= VDD/2 1.1 VDD - 1.5Image Reject Select (Note 2)
= 0V 0.4
VDD - 0.4
- 0.4 V
V
DD
10 µA
IL
IH
V
V
V
fRF = 433MHz, V
fRF = 375MHz, V
f
RL = 5kΩ
= V
P WRDN
= 0V,
P WRDN
XTALSEL
RF
= 0V
= 315MHz, V
0.4 V
0.4 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL CHARACTERISTICS
Startup Time t
Receiver Input Frequency f
Maximum Receiver Input Level P
Sensitivity (Note 3) P
AGC Hysteresis LNA gain from low to high
LNA IN HIGH-GAIN MODE
Power Gain 16 dB
1dB Compression Point P1dB
Input-Referred 3rd-Order
Intercept
ON
RF
RFIN_MAX
RFIN_MIN
IN_LNA
IIP3
Time for valid signal detection after
P WRDN
= V
OH
V
Modulation depth > 18dB 0 dBm
Peak power level -114 dBm
Normalized to
50Ω
LNA
LNA
250 µs
300 450 MHz
8dB
150 ms
fRF = 433MHz 1 - j3.4
fRF = 375MHz 1 - j3.9Input Impedance (Note 4) Z
= 315MHz 1 - j4.7
f
RF
-22 dBm
-12 dBm
mA
µA
V
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, VDD= 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF= 315MHz, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at V
DD
= 3.3V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LO Signal Feedthrough to
Antenna
Noise Figure NF
LNA IN LOW-GAIN MODE
1dB Compression Point P1dB
Input-Referred 3rd-Order
Intercept
LO Signal Feedthrough to
Antenna
Noise Figure NF
Power Gain 0dB
Voltage Gain Reduction AGC enabled (depends on tank Q) 35 dB
MIXER
Input-Referred 3rd-Order
Intercept
Output Impedance Z
Noise Figure NF
Image Rejection
(not Including LNA Tank)
Conversion Gain 330Ω IF filter load 13 dB
INTERMEDIATE FREQUENCY (IF)
Input Impedance Z
Operating Frequency f
3dB Bandwidth 20 MHz
RSSI Linearity ±0.5 dB
RSSI Dynamic Range 80 dB
RSSI Level
RSSI Gain 14.2 mV/dB
AGC Threshold
LNA
IN_LNA
IIP3
LNA
IIP3
OUT_MIX
IN_IF
IF
Normalized to
50Ω
LNA
LNA
MIX
MIX
fRF = 433MHz, V
fRF = 375MHz, V
= 315MHz, V
f
RF
Bandpass response 10.7 MHz
P
< -120dBm 1.15
RFIN
> 0dBm, AGC enabled 2.35
P
RFIN
LNA gain from low to high 1.45
LNA gain from high to low 2.05
fRF = 433MHz 1 - j3.4
fRF = 375MHz 1 - j3.9Input Impedance (Note 4) Z
= 315MHz 1 - j4.7
f
RF
= V
IRSEL
IRSEL
IRSEL
DD
= VDD/2 44
= 0V 44
-80 dBm
2dB
-10 dBm
-7 dBm
-80 dBm
2dB
-18 dBm
330 Ω
16 dB
42
dB
330 Ω
V
V
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
_______________________________________________________________________________________ 5
Note 1: 100% tested at TA= +25°C. Guaranteed by design and characterization over temperature.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image rejection setting is desired. A 1nF
capacitor is recommended in noisy environments.
Note 3: BER = 2 x 10
-3
, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration con-
nected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (f
RF
- 10.7MHz)/64 for
XTALSEL = 0V, and (f
RF
- 10.7MHz)/32 for XTALSEL = VDD.
AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, VDD= 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF= 315MHz, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at V
DD
= 3.3V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DATA FILTER
Maximum Bandwidth BW
DATA SLICER
Comparator Bandwidth BW
Output High Voltage V
Output Low Voltage 0V
CRYSTAL OSCILLATOR
Crystal Frequency (Note 5) f
Crystal Tolerance 50 ppm
Input Capacitance From each pin to ground 6.2 pF
Recommended Crystal Load
Capacitance
Maximum Crystal Load
Capacitance
DF
CMP
fRF = 433MHz
XTAL
fRF = 315MHz
C
LOAD
C
LOAD
V
XTALSEL
V
XTALSEL
V
XTALSEL
V
XTALSEL
100 kHz
100 kHz
DD5
= 0V 6.6128
= V
DD
= 0V 4.7547
= V
DD
13.2256
9.5094
3pF
10 pF
V
MHz
MHz
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
6 _______________________________________________________________________________________
Typical Operating Characteristics
(
Typical Application Circuit
, VDD= 3.3V, fRF= 315MHz, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1473 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.53.43.33.23.1
5.0
5.1
5.2
5.3
5.4
5.5
5.6
4.9
3.0 3.6
+105°C
+85°C
+25°C
-40°C
SUPPLY CURRENT
vs. RF FREQUENCY
MAX1473 toc02
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
450400350300
5.0
5.5
6.0
6.5
7.0
4.5
250 500
+105°C
+25°C
+85°C
-40°C
100
0.01
-121
-118
-120 -119
-117 -116
-114
BIT-ERROR RATE
vs. AVERAGE RF INPUT POWER
0.1
1
10
MAX1473 toc03
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE (%)
-115
fRF = 433MHz
fRF = 315MHz
RSSI vs. RF INPUT POWER
MAX1473 toc05
RF INPUT POWER (dBm)
RSSI (V)
-20-40-60-80-100-120
1.2
1.4
1.6
1.8
2.0
2.2
2.4
1.0
-140 0
IF BANDWIDTH = 280kHz
V
AGCDIS
= 0V
V
AGCDIS
= V
DD
RSSI AND DELTA
vs. IF INPUT POWER
MAX1473 toc06
IF INPUT POWER (dBm)
RSSI (V)
-10-30-50-70
1.2
1.4
1.6
1.8
2.0
2.2
2.4
1.0
DELTA (dB)
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-3.5
-90 10
DELTA
RSSI
SYSTEM GAIN vs. FREQUENCY
MAX1473 toc07
IF FREQUENCY (MHz)
SYSTEM GAIN (dB)
252015105
-20
-10
0
10
20
30
-30
030
UPPER
SIDEBAND
LOWER
SIDEBAND
FROM RFIN TO
MIXOUT
f
RF
= 315MHz
50dB IMAGE
REJECTION
IMAGE REJECTION
vs. RF FREQUENCY
MAX1473 toc08
RF FREQUENCY (MHz)
IMAGE REJECTION (dB)
430380330
35
40
45
50
55
30
280 480
fRF = 433MHz
fRF = 375MHz
fRF = 315MHz
IMAGE REJECTION
vs. TEMPERATURE
MAX1473 toc09
TEMPERATURE (°C)
IMAGE REJECTION (dB)
603510-15
41
42
42
43
43
44
44
45
45
41
-40 85
fRF = 315MHz
fRF = 375MHz
fRF = 433MHz
SENSITIVITY vs. TEMPERATURE
-100
PEAK RF INPUT POWER
-102
0.2% BER
IF BANDWIDTH = 280kHz
-104
-106
-108
-110
SENSITIVITY (dBm)
-112
-114
-116
-118
-40 120
fRF = 433MHz
40
TEMPERATURE (°C)
fRF = 315MHz
60
10080-20 0 20
MAX1473 toc04
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VDD= 3.3V, fRF= 315MHz, TA= +25°C, unless otherwise noted.)
NORMALIZED IF GAIN
vs. IF FREQUENCY
5
0
-5
-10
NORMALIZED IF GAIN (dB)
-15
-20
110100
IF FREQUENCY (MHz)
REGULATOR VOLTAGE
vs. REGULATOR CURRENT
3.1
3.0
-40°C
2.9
2.8
2.7
REGULATOR VOLTAGE (V)
2.6
VDD = 5.0V
2.5
545
+25°C
REGULATOR CURRENT (mA)
S11 MAGNITUDE-LOG PLOT OF RFIN
30
20
MAX1473 toc10
10
0
-10
-20
-30
+85°C
+105°C
352515
MAGNITUDE (dB)
-40
-50
-60
-70
0
-20
MAX1473 toc13
-40
-60
-80
-100
PHASE NOISE (dBc/Hz)
-120
-140
1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01
10 1000
315MHz
-34dB
RF FREQUENCY (MHz)
PHASE NOISE
vs. OFFSET FREQUENCY
fRF = 315MHz
OFFSET FREQUENCY (MHz)
901802604 703208 307 406 505109
MAX1473 toc11
0
-20
MAX1473 toc14
-40
-60
-80
-100
PHASE NOISE (dBc/Hz)
-120
-140
S11 SMITH PLOT OF RFIN
600MHz
MAX1473 toc12
100MHz
PHASE NOISE
vs. OFFSET FREQUENCY
fRF = 433MHz
1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01
OFFSET FREQUENCY (MHz)
MAX1473 toc15
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
8 _______________________________________________________________________________________
Pin Description
p
)
p
)
PIN
TSSOP TQFN
1 29 XTAL1 1st Crystal Input. (See the Phase-Locked Loop section.)
2, 7 4, 30 AVDD
3 31 LNAIN Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
4 32 LNASRC
5 2 AGND Analog Ground
6 3 LNAOUT
8 5 MIXIN1 1st Differential Mixer Input. Connect through a 100pF capacitor to V
9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
10 7 AGND Analog Ground
11 8 IRSEL
12 9 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 10 DGND Digital Ground
14 11 DVDD
15 12 AGCDIS AGC Control Pin. Pull high to disable AGC.
16 14 XTALSEL
17 15 IFIN1
18 16 IFIN2
19 17 DFO Data Filter Output
20 18 DSN Negative Data Slicer Input
21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 20 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 22 DSP Positive Data Slicer Input
24 23 V
25 24 DATAOUT Digital Baseband Data Output
26 26 PDOUT Peak Detector Output
27 27 PWRDN Power-Down Select Input. Drive this pin with a logic high to power on the IC.
28 28 XTAL2 2nd Crystal Input
1, 13,
—
21, 25
— — EP Exposed Pad (TQFN Only). Connect EP to GND.
NAME FUNCTION
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close as
possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section
and the Typical Application Circuit).
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA in
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise
Am
Im ag e Rej ecti on S el ect P i n. S et V
unconnected to center i m ag e r ej ecti on at 375M H z. S et V
Positive Digital Supply Voltage. Connect to both of the AVDD pins.
capacitor as close as possible to the pin (see the Typical Application Circuit).
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
high to select divider ratio of 32.
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
capacitor.
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
DD5
N.C. No Connection
+5V operation, V
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
ut impedance. (See the Low-Noise Amplifier section.
lifier section.
= 0V to center i m ag e r ej ecti on at 315M H z. Leave IRS E L
I RS E L
is the input to an on-chip voltage regulator whose +3.2V output appears at the
DD5
IRS E L
= V
side of the LC tank.
DD3
to center i m ag e r ej ecti on at 433M H z.
D D
Bypass to DGND with a 0.01µF
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
_______________________________________________________________________________________ 9
Detailed Description
The MAX1473 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 100kbps can be achieved.
The MAX1473 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
Voltage Regulator
For operation with a single +3.0V to +3.6V supply voltage, connect AVDD, DVDD, and V
DD5
to the supply
voltage. For operation with a single +4.5V to +5.5V
supply voltage, connect V
DD5
to the supply voltage. An
on-chip voltage regulator drives one of the AVDD pins
to approximately +3.2V. For proper operation, DVDD
and both the AVDD pins must be connected together.
Bypass V
DD5
, DVDD, and the pin 7 AVDD pin to AGND
with 0.01µF capacitors, and the pin 2 AVDD pin to
AGND with a 0.1µF capacitor, all placed as close as
possible to the pins.
Low-Noise Amplifier
The LNA is an NMOS cascode amplifier with off-chip
inductive degeneration that achieves approximately
16dB of power gain with a 2.0dB noise figure and an
IIP3 of -12dBm. The gain and noise figure are dependent on both the antenna matching network at the LNA
input and the LC tank network between the LNA output
and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical PCB trace antenna. A nominal
value for this inductor with a 50Ω input impedance is
15nH, but is affected by PCB trace. See the
Typical
Operating Characteristics
for the relationship between
the inductance and the LNA input impedance.
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an
RF input level of approximately -57dBm, the AGC
switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing
the RSSI output by about 500mV. The LNA resumes
high-gain mode when the RSSI level drops back below
1.45V (approximately -65dBm at RF input) for 150ms.
The AGC has a hysteresis of ~8dB. With the AGC func-
tion, the MAX1473 can reliably produce an ASK output
for RF input levels up to 0dBm with a modulation depth
of 18dB.
The LC tank filter connected to LNAOUT comprises L3
and C2 (see the
Typical Application Circuit
). Select L3
and C2 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where:
L
TOTAL
= L3 + L
PARASITICS
C
TOTAL =
C2 + C
PARASITICS
L
PARASITICS
and C
PARASITICS
include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. These
parasitics at high frequencies cannot be ignored, and
can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank.
Mixer
A unique feature of the MAX1473 is the integrated
image rejection of the mixer. This device eliminates the
need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are
increased sensitivity, simplified antenna matching, less
board space, and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., fLO= fRFf
IF
). The image-rejection circuit then combines these
signals to achieve a minimum 45dB of image rejection
over the full temperature range. Low-side injection is
required due to the on-chip image rejection architecture. The IF output is driven by a source-follower biased
to create a driving impedance of 330Ω; this provides a
good match to the off-chip 330Ω ceramic IF filter. The
voltage conversion gain is approximately 13dB when
the mixer is driving a 330Ω load.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When
V
IRSEL
= 0V, the image rejection is tuned to 315MHz.
V
IRSEL
= VDD/2 tunes the image rejection to 375MHz,
and when V
IRSEL
= VDD, the image rejection is tuned to
433MHz. The IRSEL pin is internally set to VDD/2 (image
rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external VDD/2 voltage.
f
2π
1
LC
TOTAL TOTAL
=×
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
10 ______________________________________________________________________________________
Phase-Locked Loop
The PLL block contains a phase detector, charge
pump/integrated loop filter, VCO, asynchronous 64x
clock divider, and crystal oscillator driver. Besides the
crystal, this PLL does not require any external components. The VCO generates a low-side local oscillator
(LO). The relationship between the RF, IF, and crystal
reference frequencies is given by:
f
XTAL
= (fRF- fIF)/(32 M)
where:
M = 1 (V
XTALSEL
= VDD) or 2 (V
XTALSEL
= 0V)
To allow the smallest possible IF bandwidth (for best sensitivity), the tolerance of the reference must be minimized.
Intermediate Frequency/RSSI
The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately
11.5MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB (see
the
Typical Operating Characteristics
).
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an RF
input level of approximately -57dBm, the AGC switches
on the LNA gain reduction resistor. The resistor reduces
the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode
when the RSSI level drops back below 1.45V (approximately -65dBm at RF input) for 150ms. The AGC has a
hysteresis of ~8dB. With the AGC function, the
MAX1473 can reliably produce an ASK output for RF
input levels up to 0dBm with modulation depth of 18dB.
Applications Information
Crystal Oscillator
The XTAL oscillator in the MAX1473 is designed to present a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals
designed to operate with higher differential load capacitance always pull the reference frequency higher. For
example, a 4.7547MHz crystal designed to operate
with a 10pF load capacitance oscillates at 4.7563MHz
with the MAX1473, causing the receiver to be tuned to
315.1MHz rather than 315.0MHz, an error of about
100kHz, or 320ppm.
In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
f
p
is the amount the crystal frequency pulled in ppm.
Cmis the motional capacitance of the crystal.
C
case
is the case capacitance.
C
spec
is the specified load capacitance.
C
load
is the actual load capacitance.
When the crystal is loaded as specified, i.e., C
load
=
C
spec
, the frequency pulling equals zero.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set
to approximately 1.5 times the fastest expected data
rate from the transmitter. Keeping the corner frequency
near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of C7 and C6, use the following equations along
with the coefficients in Table 1:
Table 1. Coefficents to Calculate C7 and C6
⎛
C
m
f
p
⎜
=
⎜
2
⎝
11
CCC C
++
case load case spec
-
⎞
6
⎟
×
10
⎟
⎠
FILTER TYPE a b
Butterworth (Q = 0.707) 1.414 1.000
Bessel (Q = 0.577) 1.3617 0.618
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
______________________________________________________________________________________ 11
where fCis the desired 3dB corner frequency.
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
Choosing standard capacitor values changes C7 to
470pF and C6 to 220pF, as shown in the
Typical
Application Circuit
.
Data Slicer
The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal.
This is achieved by using a comparator and comparing
the analog input to a threshold voltage. One input is
supplied by the data filter output. Both comparator
inputs are accessible off chip to allow for different
methods of generating the slicing threshold, which is
applied to the second comparator input.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor (C8) from DSN to DGND (Figure 2). This configuration averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The sizes of R1 and C8
affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC
circuit much lower than the lowest expected data rate.
Note that a long string of zeros or 1’s can cause the
threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an
equal number of zeros and 1’s, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, hysteresis can
be added to the data slicer as shown in Figure 3.
For further information on Data Slicer options, please
refer to Maxim Application Note 3671,
Data Slicing
Techniques for UHF ASK Receivers
.
Figure 1. Sallen-Key Lowpass Data Filter
Figure 2. Generating Data Slicer Threshold
Figure 3. Generating Data Slicer Hysteresis
C
7
=
=
6
C
b
100
ak f
()()
π
()
c
a
4 100
()()
π
kf
()
c
1 000
C
=
1 414 100 3 14 5
..
()( )()()
.
kkHz
Ω
pF7
≈
450
19
DFO
MAX1473
RSSI
22
DFFB
R
DF1
100kΩ
R
DF2
100kΩ
21
OPP
C6
C7
MAX1473
DATA
SLICER
25
DATAOUT
20
DSN
C8
23
DSP
R1
19
DFO
MAX1473
DATA
SLICER
25
DATAOUT
R2
*OPTIONAL
R*
23
DSP
20
DSN
R3
C8
19
DFO
R1
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
12 ______________________________________________________________________________________
Peak Detector
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data filter output voltage. For faster receiver startup,
the circuit shown in Figure 4 can be used.
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all power-supply pins.
Control Interface Considerations
When operating the MAX1473 with a +4.5V to +5.5V
supply voltage, the PWRDN and AGCDIS pins may be
driven by a microcontroller with either 3V or 5V interface logic levels. When operating the MAX1473 with a
+3.0V to +3.6V supply, the microcontroller must produce logic levels which conform to the VIHand V
IL
specifications in the DC Electrical Characteristics Table
for the MAX1473.
Figure 4. Using PDOUT for Faster Startup
25
DATAOUT
47nF
MAX1473
DATA
SLICER
20
DSN
DSP
25kΩ
19
23
DFO
26
PDOUT
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
______________________________________________________________________________________ 13
Table 2. Component Values for Typical Application Circuit
*Crystal frequencies shown are for÷64 (V
XTALSEL
= 0V) and ÷32 (V
XTALSEL
= VDD).
**Wirewound recommended.
COMPONENT VALUE FOR fRF = 433MHz VALUE FOR fRF = 315MHz DESCRIPTION
C1 100pF 100pF 5%
C2 2.7pF 4.7pF ±0.1pF
C3 100pF 100pF 5%
C4 100pF 100pF 5%
C5 1500pF 1500pF 10%
C6 220pF 220pF 5%
C7 470pF 470pF 5%
C8 0.47µF 0.47µF 20%
C9 220pF 220pF 10%
C10 0.01µF 0.01µF 20%
C11 0.1µF 0.1µF 20%
C12 15pF 15pF Depends on XTAL
C13 15pF 15pF Depends on XTAL
C14 0.01µF 0.01µF 20%
C15 0.01µF 0.01µF 20%
L1 56nH 120nH 5% or better**
L2 15nH 15nH 5% or better**
L3 15nH 27nH 5% or better**
R1 5.1kΩ 5.1kΩ 5%
R2 Open Open —
R3 Short Short —
X1(÷64) 6.6128MHz* 4.7547MHz* Crystek or Hong Kong X’tal
X1 (÷32) 13.2256MHz* 9.5094MHz* Crystek or Hong Kong X’tal
Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
14 ______________________________________________________________________________________
Typical Application Circuit
Chip Information
PROCESS: CMOS
IF V
DD
3.0V TO 3.6V
4.5V TO 5.5V
THEN V
IS
CONNECTED TO V
CREATED BY LDO,
AVAILABLE AT AVDD
DD3
(PIN 2)
RF INPUT
C1
V
DD3
L3
C2
C9
COMPONENT VALUES
IN TABLE 2
V
C3
C14
C4
C10
C11
DD3
(SEE TABLE)
X1
C13
1
XTAL1 XTAL2
2
AVDD
3
LNAIN
4
LNASRC
5
AGND
6
LNAOUT
7
AVDD
8
MIXIN1
9
MIXIN2
10
AGND
11
IRSEL
12
MIXOUT
13
DGND
14
DVDD
MAX1473
IF FILTER
IN OUT
GND
C12
28
27
PWRDN
26
PDOUT
V
DD5
DSP
DFFB
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
AGCDIS
25
24
23
22
21
20
19
18
17
16
15
*
DATAOUT
Y1
IS
DD
L1
L2
**
V
DD
TO/FROM µP
POWER DOWN
DATA OUT
R2
C15
R3
C7
R1
FROM µP
C6C5
C8
** SEE MIXER SECTION * SEE PHASE-LOCKED LOOP SECTION
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
______________________________________________________________________________________ 15
PACKAGE TYPE PACKAGE CODE OUTLINE NO.
LAND
PATTERN NO.
28 TSSOP U28+1
21-0066
90-0171
32 Thin QFN-EP T3255+3
21-0140
90-0001
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Functional Diagram
LNAIN
AVDD
V
DD5
AVDD
DVDD
DGND
AGND
5,10
AGCDIS
LNASRC
4 15 6 8 9 11 12 17 18
3
LNA
2
3.2V REG
24
7
14
13
DIVIDE
BY 64
PHASE
DETECTOR
÷1
÷2
XTALSEL16XTAL11XTAL228PWRDN27DATAOUT
LNAOUT MIXIN1 MIXIN2
AUTOMATIC
GAIN
CONTROL
VCO
LOOP
FILTER
CRYSTAL
DRIVER
POWER
DOWN
IRSEL
0˚
Q
IMAGE
REJECTION
I
DATA
SLICER
25
∑
90˚
MAX1473
19
DSN20DSP23DFO
IFIN1MIXOUT IFIN2
IF LIMITING
AMPS
RSSI
DATA
FILTER
21
PDOUT26OPP
R
DF2
100kΩ
22
DFFB
R
DF1
100kΩ
MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
4 5/10
5 1/11
6 1/12
REVISION
DATE
DESCRIPTION
Added lead-free parts and exposed pad in Ordering Information and Pin
Description tables
Updated Absolute Maximum Ratings, AC Electrical Characteristics, Pin
Description, Layout Cons ideration s, Typical Application Circuit, Functional
Diagram, and Package Information; added Voltage Regulator section to the
Detai led De scription section
Updated DC Electrical and AC Electr ical Characteristics tables, replaced TOC 4,
updated Tables 1 and 2 and Figure 1; updated Phase-Locked Loop, Data Filter,
Data Slicer, and Layout Con sideration s sections
PAGES
CHANGED
1, 8
2, 3, 4, 8, 9, 12,
13, 14
3, 5, 6, 10–13
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