The MAX1471 low-power, CMOS, superheterodyne, RF
dual-channel receiver is designed to receive both amplitude-shift-keyed (ASK) and frequency-shift-keyed (FSK)
data without reconfiguring the device or introducing any
time delay normally associated with changing modulation schemes. The MAX1471 requires few external components to realize a complete wireless RF digital data
receiver for the 300MHz to 450MHz ISM bands.
The MAX1471 includes all the active components
required in a superheterodyne receiver including: a lownoise amplifier (LNA), an image-reject (IR) mixer, a fully
integrated phase-locked loop (PLL), local oscillator
(LO), 10.7MHz IF limiting amplifier with received-signalstrength indicator (RSSI), low-noise FM demodulator,
and a 3V voltage regulator. Differential peak-detecting
data demodulators are included for both the FSK and
ASK analog baseband data recovery. The MAX1471
includes a discontinuous receive (DRX) mode for lowpower operation, which is configured through a serial
interface bus.
The MAX1471 is available in a 32-pin thin QFN package
and is specified over the automotive -40°C to +125°C
temperature range.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
High-Voltage Supply, HVIN to DGND ......................-0.3V, +6.0V
Low-Voltage Supply, AVDD and DVDD to AGND ....-0.3V, +4.0V
SCLK, DIO, CS, ADATA,
FDATA ...................................(DGND - 0.3V) to (HVIN + 0.3V)
All Other Pins............................(AGND - 0.3V) to (AVDD + 0.3V)
Note 1: Production tested at TA= +85°C. Guaranteed by design and characterization over entire temperature range.
Note 2: Guaranteed by design and characterization. Not production tested.
Note 3: The oscillator register (0x3) is set to the nearest integer result of f
XTAL
/ 100kHz (see the
Oscillator Frequency Register
section).
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degeneration
from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA
source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. The voltage conversion gain is measured with the
LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF filter insertion loss.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG BASEBAND
Maximum Data Filter BandwidthBW
Maximum Data Slicer BandwidthBW
Maximum Peak Detector
Bandwidth
Maximum Data Rate
CRYSTAL OSCILLATOR
Crystal Frequencyf
Frequency Pulling by V
Crystal Load Capacitance3pF
DIGITAL INTERFACE TIMING (see Figure 8)
Minimum SCLK Setup to Falling
Edge of CS
Minimum CS Falling Edge to
SCLK Rising-Edge Setup Time
Minimum CS Idle Timet
Minimum CS Periodt
Maximum SCLK Falling Edge to
Data Valid Delay
Minimum Data Valid to SCLK
Rising-Edge Setup Time
Minimum Data Valid to SCLK
Rising-Edge Hold Time
Minimum SCLK High Pulse Widtht
Minimum SCLK Low Pulse Widtht
Minimum CS Rising Edge to
10LNAOUTLow-Noise Amplifier Output. Connect to mixer through an LC tank filter.
11MIXIN+Differential Mixer Input. Must be AC-coupled to driving input.
12MIXIN-Differential Mixer Input. Bypass to AGND with a capacitor.
13MIXOUT330Ω Mixer Output. Connect to the input of the 10.7MHz IF filter.
14AGNDAnalog Ground
15IFIN-Differential 330Ω IF Limiter Amplifier Input. Bypass to AGND with a capacitor.
16IFIN+Differential 330Ω IF Limiter Amplifier Input. Connect to output of the 10.7MHz IF filter.
17PDMINF
18PDMAXF
19DSF-Inverting Data Slicer Input for FSK Data
20DSF+Noninverting Data Slicer Input for FSK Data
21OPF+Noninverting Op-Amp Input for the FSK Sallen-Key Data Filter
22DFFData-Filter Feedback Node. Input for the feedback of the FSK Sallen-Key data filter.
23DGNDDigital Ground
24DVDD
25FDATADigital Baseband FSK Demodulator Data Output
26CSActive-Low Chip-Select Input
27DIOSerial Data Input/Output
28SCLKSerial Interface Clock Input
29HVINHigh-Voltage Supply Input. For 3V operation, connect HVIN to AVDD and DVDD.
30ADATADigital Baseband ASK Demod Data Output
31PDMINA
32PDMAXA
—EPExposed Pad. Connect to ground.
Analog Power-Supply Voltage for RF Sections. AVDD is connected to an on-chip +3.0V low-dropout
regulator. Decouple to AGND with a 0.1µF capacitor.
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to AGND to set
LNA input impedance.
Minimum-Level Peak Detector for FSK Data. Connect to ground if peak detector is not used. See the
Peak Detectors section.
Maximum-Level Peak Detector for FSK Data. Connect to ground if peak detector is not used. See the
Peak Detectors section.
Digital Power-Supply Voltage for Digital Sections. Connect to AVDD. Decouple to DGND with a 10nF
capacitor.
Minimum-Level Peak Detector for ASK Output. Connect to ground if peak detector is not used. See the
Peak Detectors section.
Maximum-Level Peak Detector for ASK Output. Connect to ground if peak detector is not used. See the
Peak Detectors section.
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