MAXIM MAX14611 Technical data
EVALUATION KIT AVAILABLE
19-6276; Rev 0; 4/12
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
General Description
The MAX14611 is a quad bidirectional logic-level translator that provides the level shifting necessary to allow data
transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of
the device. A low-voltage logic signal present on the VL
side of the device appears as a high-voltage logic signal
on the VCC side of the device, and vice-versa.
The device is ideal for I2C bus as well as MDIO bus applications where open-drain operation is often required. The
device features a three-state output mode (TS). Drive TS
high to connect the pullup to the powered I/O port. This
allows for continuous, undisrupted I2C operation on the
powered side of the device while the level translation
function is off. The MAX14611 is a pin-to-pin compatible
upgrade to the MAX3378E in the TDFN package.
The MAX14611 features enhanced high-electrostaticdischarge (ESD) protection on all I/OVCC_ ports up to
±6kV HBM. The device operates over the -40NC to +85NC
extended temperature range and is available in 3mm x
3mm, 14-pin TDFN and 4.9mm x 5.1mm, 14-pin TSSOP
packages.
Applications
SPI, I2C, and MDIO
Level Translation
Low-Voltage ASIC
Level Translation
Portable Electronics
Mobile Phones
POS Systems
Telecommunications
Equipment
Benefits and Features
S Improved Interoperability
Meets I2C Specifications
10kI Internal Pullup Resistor
Pin-to-Pin Compatible with the MAX3377E and
the MAX3378E
0.9V Operation on Low Voltage Supply
S Robust Logic-Level Translation
±0.5V Tolerances on All Pins
±6kV Human Body Model ESD Protection on
I/OVCC� Lines
Thermal Short-Circuit Protection
Short to Ground Fault Protection on All Pins
-40NC to +85NC Operating Temperature Range
S Increased Design Flexibility
Ultra-Low Supply Current
Pullup Resistor Enabled with a Single Power
Supply when TS = High
10I (max) Transmission Gate FET
Small, 14-Pin, 3.0mm x 3.0mm TDFN Package
and 14-Pin, 4.9mm x 5.1mm TSSOP Package
Ordering Information appears at end of data sheet.
Typical Operating Circuit
+1.8V +3.3V
+1.8V SYSTEM
CONTROLLER
For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX14611.related.
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
0.1µF 1µF
V
TS
I/OVL_DATA
L
MAX14611
V
CC
I/OVCC_
+3.3V
SYSTEM
DATA
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
VCC .......................................................................... -0.5V to +6V
VL .......................................................................... -0.5V to +5.5V
TS ............................................................................-0.5V to +6V
I/OVCC_ .................................................... -0.5V to (VCC + 0.5V)
I/OVL_ .......................................................... -0.5V to (VL + 0.5V)
Short-Circuit Duration I/OVL_, I/OVCC_ to GND .......Continuous
Continuous Current ......................................................... Q50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN-EP
Junction-to-Ambient Thermal Resistance (qJA) ...........41°C/W
Junction-to-Case Thermal Resistance (qJC) ..................8°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Continuous Power Dissipation (TA = +70NC)
TDFN (derate 24.4mW/NC above +70NC) ...............1951.2mW
TSSOP (derate 10mW/NC above +70NC) ................. 796.8mW
Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) .....................................+260NC
TSSOP
Junction-to-Ambient Thermal Resistance (qJA ) ......100.4°C/W
Junction-to-Case Thermal Resistance (qJC) ................30°C/W
ELECTRICAL CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of V
values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
VL Supply Range V
VCC Supply Range V
VL Supply Current I
VCC Supply Current I
VCC Shutdown Mode Supply
Current
VL Shutdown Mode Supply
Current
I/OVCC_, I/OVL_, TS Leakage
Current
TS Input Leakage Current
VL Shutdown Threshold V
VCC Shutdown Threshold V
I/OVL_ Pullup Resistor R
I/OVCC_ Pullup Resistor R
L
CC
VL
VCC
I
SHDN_VCC
I
SHDN_VL
I
LEAK
I
LEAK_TS
TH_VL
TH_VCC
VL_PU
VCC_PU
+ 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical
CC
I/OVCC_ = VCC, I/OVL_ = VL, TS = V
I/OVCC_ = VCC, I/OVL_ = VL, TS = V
TS = GND, I/OVCC = unconnected
TS = VCC, VL = GND,
I/OVCC = unconnected
TS = GND
TS = VL, VCC = GND,
I/OVL_ = unconnected
TA = +25NC, TS = GND
TA = +25NC
0.9 5 V
1.65 5.5 V
L
L
0.1 1
0.1 1
0.1 1
0.1 1
0.1 1
0.3 0.85 V
0.8 1.35 V
10
10
35
1
1
FA
FA
FA
FA
FA
FA
kI
kI
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of V
values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/OVL_ to I/OVCC_ DC
Resistance
I/OVL_ Input-Voltage High V
I/OVL_ Input-Voltage Low V
I/OVCC_ Input-Voltage High V
I/OVCC_ Input-Voltage Low V
I/OVL_ Output-Voltage High V
I/OVL_ Output-Voltage Low V
I/OVCC_ Output-Voltage High V
I/OVCC_ Output Voltage Low V
TS Input-Voltage High Threshold
TS Input-Voltage Low Threshold
Accelerator Pulse Duration Inferred from timing measurements 30 ns
VL Output Accelerator Source
Impedance
VCC Output Accelerator Source
Impedance
Thermal-Shutdown Threshold
ESD PROTECTION
I/OVCC_
All Other Pins Human Body Model
R
IOVL_IOVCC
IHL
ILL
IHC
ILC
OHL
OLL
OHC
OLC
V
IH
V
IL
+ 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical
CC
Inferred from V
I/OVL_ source current = 10FA
I/OVL_ sink current = 2mA,
V
I/OVCC_ source current = 10FA
I/OVCC_ sink current = 2mA,
V
VL > 1.3V 0.2 V
VL = 0.9V 70
VL = 3.3V 15
VCC = 1.65V 50
VCC = 5.0V 10
20NC hysteresis
Human Body Model, C
CVL = 0.1FF
I/OVCC_
I/OVL_
P 50mV
P 150mV
measurements 5 10
OL
VL - 0.2 V
VCC - 0.4
0.7 x V
L
0.7 x V
CC
VL - 0.2 V
+150
= 1FF,
VCC
Q6
Q2
0.15 V
0.2 V
0.4 V
0.4 V
I
V
V
V
I
I
NC
kV
kV
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +0.9V to the lesser of V
C
= 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are VCC = +3.3V, VL = +1.8V, and TA = +25NC.) (Note 4)
I/OVL_
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/OVCC_ Rise Time t
I/OVCC_ Fall Time t
I/OVL_ Rise Time t
I/OVL_ Fall Time t
Propagation Delay
Propagation Delay
Channel-to-Channel Skew t
Maximum Data Rate
Note 2: All units are 100% production tested at TA = +25°C. Specifications over operating temperature range are guaranteed by
design.
Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 4: All timing is 10% to 90% for rise time and 90% to 10% for fall time.
Note 5: Not production tested; guaranteed by design.
Note 6: Requires the external pullup resistor.
I/O
I/O
I/O
I/O
RVCC
FVCC
RVL
FVL
VL-VCC
VL-VCC
VCC-VL
VCC-VL
SKEW
+ 0.3V and 5V, TS = VL, RL = 1Mω, C
CC
Push-pull driving (Figure 1) 40
Open-drain driving (Figure 2, Note 5) 100
Push-pull driving (Figure 1) 40
Open-drain driving (Figure 2, Note 5) 50
Push-pull driving (Figure 3) 30
Open-drain driving (Figure 4, Note 5) 105
Push-pull driving (Figure 3) 30
Open-drain driving (Figure 4, Note 5) 30
Push-pull driving (Figure 1) 40
Open-drain driving (Figure 2, Note 5) 150
Push-pull driving (Figure 3) 30
Open-drain driving (Figure 4, Note 5) 105
Input rise time/fall time < 6ns, push-pull
driving
Input rise time/fall time < 6ns, open-drain
driving
Push-pull operation 20
Open-drain operation (Notes 5, 6) 6
= 1µF, CVL = 0.1µF, C
VCC
I/OVCC_
20
50
= 15pF,
ns
ns
ns
ns
ns
ns
ns
Mbps
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
R
50I
V
V
TS
S
I/OVL_
L
L
MAX14611
GND
V
CC
V
CC
I/OVCC_
Figure 1. Push-Pull Driving I/OVL_
V
L
V
L
1kI
TS
MAX14611
I/OVL_
GND
V
CC
V
CC
I/OVCC_
C
I/OVCC_RL
1kI
C
I/OVCC_RL
50%
10%
t
PDLH
t
RVCC
t
RVCC
90%
50%
90%90%
50%
90%
50%
50%
t
PDHL
50%
t
FVCC
t
FVCC
10%
Figure 2. Open-Drain Driving I/OVL_
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10%
50%
t
PDLH
50%
t
PDHL
10%
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