MAXIM MAX14611 Technical data

EVALUATION KIT AVAILABLE

19-6276; Rev 0; 4/12

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

General Description

The MAX14611 is a quad bidirectional logic-level translator that provides the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. A low-voltage logic signal present on the VL side of the device appears as a high-voltage logic signal on the VCC side of the device, and vice-versa.

The device is ideal for I2C bus as well as MDIO bus applications where open-drain operation is often required. The device features a three-state output mode (TS). Drive TS high to connect the pullup to the powered I/O port. This allows for continuous, undisrupted I2C operation on the powered side of the device while the level translation function is off. The MAX14611 is a pin-to-pin compatible upgrade to the MAX3378E in the TDFN package.

The MAX14611 features enhanced high-electrostaticdischarge (ESD) protection on all I/OVCC_ ports up to ±6kV HBM. The device operates over the -40NC to +85NC extended temperature range and is available in 3mm x 3mm, 14-pin TDFN and 4.9mm x 5.1mm, 14-pin TSSOP packages.

Applications

SPI, I2C, and MDIO Level Translation

Low-Voltage ASIC Level Translation

Portable Electronics

Mobile Phones

POS Systems

Telecommunications Equipment

Benefits and Features

S Improved Interoperability

 Meets I2C Specifications  10kI Internal Pullup Resistor  Pin-to-Pin Compatible with the MAX3377E and

the MAX3378E 0.9V Operation on Low Voltage Supply

S Robust Logic-Level Translation

 ±0.5V Tolerances on All Pins  ±6kV Human Body Model ESD Protection on

I/OVCC� Lines

 Thermal Short-Circuit Protection  Short to Ground Fault Protection on All Pins -40NC to +85NC Operating Temperature Range

S Increased Design Flexibility

 Ultra-Low Supply Current  Pullup Resistor Enabled with a Single Power

Supply when TS = High

 10I (max) Transmission Gate FET Small, 14-Pin, 3.0mm x 3.0mm TDFN Package

and 14-Pin, 4.9mm x 5.1mm TSSOP Package

Ordering Information appears at end of data sheet.

Typical Operating Circuit

+1.8V +3.3V

+1.8V SYSTEM

CONTROLLER

For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX14611.related.

�� Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

0.1µF 1µF V

TS

I/OVL_DATA

L

MAX14611

V

CC

I/OVCC_

+3.3V

SYSTEM

DATA

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND.)

VCC .......................................................................... -0.5V to +6V

VL .......................................................................... -0.5V to +5.5V

TS ............................................................................-0.5V to +6V

I/OVCC_ .................................................... -0.5V to (VCC + 0.5V)

I/OVL_ .......................................................... -0.5V to (VL + 0.5V)

Short-Circuit Duration I/OVL_, I/OVCC_ to GND .......Continuous

Continuous Current ......................................................... Q50mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

TDFN-EP

Junction-to-Ambient Thermal Resistance (qJA) ...........41°C/W

Junction-to-Case Thermal Resistance (qJC) ..................8°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Continuous Power Dissipation (TA = +70NC)

TDFN (derate 24.4mW/NC above +70NC) ...............1951.2mW

TSSOP (derate 10mW/NC above +70NC) ................. 796.8mW

Operating Temperature Range .......................... -40NC to +85NC

Maximum Junction Temperature .....................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) .....................................+260NC

TSSOP

Junction-to-Ambient Thermal Resistance (qJA ) ......100.4°C/W

Junction-to-Case Thermal Resistance (qJC) ................30°C/W

ELECTRICAL CHARACTERISTICS

(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of V values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES

VL Supply Range V

VCC Supply Range V

VL Supply Current I

VCC Supply Current I

VCC Shutdown Mode Supply Current

VL Shutdown Mode Supply Current

I/OVCC_, I/OVL_, TS Leakage Current

TS Input Leakage Current

VL Shutdown Threshold V

VCC Shutdown Threshold V

I/OVL_ Pullup Resistor R

I/OVCC_ Pullup Resistor R

L

CC

VL

VCC

I

SHDN_VCC

I

SHDN_VL

I

LEAK

I

LEAK_TS

TH_VL

TH_VCC

VL_PU

VCC_PU

+ 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical

CC

I/OVCC_ = VCC, I/OVL_ = VL, TS = V

TS = GND, I/OVCC = unconnected TS = VCC, VL = GND,

I/OVCC = unconnected

TS = GND TS = VL, VCC = GND,

I/OVL_ = unconnected

TA = +25NC, TS = GND

TA = +25NC

0.9 5 V

1.65 5.5 V

L

0.1 1

0.3 0.85 V

0.8 1.35 V

10

35

1

FA

kI

�� Maxim Integrated Products 2

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of V values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/OVL_ to I/OVCC_ DC Resistance

I/OVL_ Input-Voltage High V

I/OVL_ Input-Voltage Low V

I/OVCC_ Input-Voltage High V

I/OVCC_ Input-Voltage Low V

I/OVL_ Output-Voltage High V

I/OVL_ Output-Voltage Low V

I/OVCC_ Output-Voltage High V

I/OVCC_ Output Voltage Low V

TS Input-Voltage High Threshold TS Input-Voltage Low Threshold

Accelerator Pulse Duration Inferred from timing measurements 30 ns

VL Output Accelerator Source Impedance

VCC Output Accelerator Source Impedance

Thermal-Shutdown Threshold

ESD PROTECTION

I/OVCC_

All Other Pins Human Body Model

R

IOVL_IOVCC

IHL

ILL

IHC

ILC

OHL

OLL

OHC

OLC

V

IH

V

IL

+ 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical

CC

Inferred from V

I/OVL_ source current = 10FA

I/OVL_ sink current = 2mA, V

I/OVCC_ source current = 10FA

I/OVCC_ sink current = 2mA, V

VL > 1.3V 0.2 V

VL = 0.9V 70

VL = 3.3V 15

VCC = 1.65V 50

VCC = 5.0V 10

20NC hysteresis

Human Body Model, C CVL = 0.1FF

I/OVCC_

I/OVL_

P 50mV

P 150mV

measurements 5 10

OL

VL - 0.2 V

VCC - 0.4

0.7 x V

L

0.7 x V

CC

VL - 0.2 V

+150

= 1FF,

VCC

Q6

Q2

0.15 V

0.2 V

0.4 V

I

V

I

NC

kV

�� Maxim Integrated Products 3

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

TIMING CHARACTERISTICS

(VCC = +1.65V to +5.5V, VL = +0.9V to the lesser of V C

= 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are VCC = +3.3V, VL = +1.8V, and TA = +25NC.) (Note 4)

I/OVL_

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/OVCC_ Rise Time t

I/OVCC_ Fall Time t

I/OVL_ Rise Time t

I/OVL_ Fall Time t

Propagation Delay

Channel-to-Channel Skew t

Maximum Data Rate

Note 2: All units are 100% production tested at TA = +25°C. Specifications over operating temperature range are guaranteed by

design.

Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and

shutdown conditions.

Note 4: All timing is 10% to 90% for rise time and 90% to 10% for fall time. Note 5: Not production tested; guaranteed by design. Note 6: Requires the external pullup resistor.

I/O

RVCC

FVCC

RVL

FVL

VL-VCC

VCC-VL

SKEW

+ 0.3V and 5V, TS = VL, RL = 1Mω, C

CC

Push-pull driving (Figure 1) 40

Open-drain driving (Figure 2, Note 5) 100

Push-pull driving (Figure 1) 40

Open-drain driving (Figure 2, Note 5) 50

Push-pull driving (Figure 3) 30

Open-drain driving (Figure 4, Note 5) 105

Push-pull driving (Figure 3) 30

Open-drain driving (Figure 4, Note 5) 30

Push-pull driving (Figure 1) 40

Open-drain driving (Figure 2, Note 5) 150

Push-pull driving (Figure 3) 30

Open-drain driving (Figure 4, Note 5) 105

Input rise time/fall time < 6ns, push-pull driving

Input rise time/fall time < 6ns, open-drain driving

Push-pull operation 20

Open-drain operation (Notes 5, 6) 6

= 1µF, CVL = 0.1µF, C

VCC

I/OVCC_

20

50

= 15pF,

ns

Mbps

�� Maxim Integrated Products 4

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

R

50I

V

TS

S

I/OVL_

L

MAX14611

GND

V

CC

V

CC

I/OVCC_

Figure 1. Push-Pull Driving I/OVL_

V

L

V

L

1kI

TS

MAX14611

I/OVL_

GND

V

CC

V

CC

I/OVCC_

C

I/OVCC_RL

1kI

C

I/OVCC_RL

50%

10%

t

PDLH

t

RVCC

t

RVCC

90%

50%

90%90%

50%

90%

50%

t

PDHL

50%

t

FVCC

t

FVCC

10%

Figure 2. Open-Drain Driving I/OVL_

�� Maxim Integrated Products 5

10%

50%

t

PDLH

50%

t

PDHL

10%

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

V

L

V

L

TS

MAX14611

I/OVL_

C

R

I/OVL_

L

GND

Figure 3. Push-Pull Driving I/OVCC_

V

CC

V

CC

I/OVCC_

V

L

t

RVL

R

S

50I

V

CC

50%

t

PDLH

10%

50%

90%

t

RVL

50%

t

PDHL

50%

t

FVL

90%

10%

t

FVL

V

1kI

C

R

I/OVL_

L

TS

I/OVL_

Figure 4. Open-Drain Driving I/OVCC_

�� Maxim Integrated Products 6

L

MAX14611

GND

V

CC

I/OVCC_

1kI

10%

t

PDLH

50%

90%

50%

90%

t

50%

10%

PDHL

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Typical Operating Characteristics

(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull operation, unless otherwise noted.)

VL SUPPLY CURRENT vs. SUPPLY VOLTAGE

200

DRIVING I/OVL_

175

= 1.8V

V

L

150

125

100

SUPPLY CURRENT (µA)

8Mbps,

PUSH-PULL

75

50

25

0

1.65 5.50 VCC (V)

500kbps,

OPEN-DRAIN

VCC SUPPLY CURRENT

vs. TEMPERATURE

400

DRIVING I/OVCC_

350

300

250

200

150

SUPPLY CURRENT (µA)

100

50

0

TEMPERATURE (°C)

VCC SUPPLY CURRENT

vs. CAPACITIVE LOAD

1000

DRIVING I/OVL_

900

800

700

600

500

400

300

SUPPLY CURRENT (µA)

200

100

0

500kbps,

OPEN-DRAIN

CAPACITIVE LOAD (pF)

4.954.402.20 2.75 3.30 3.85

500kbps,

OPEN-DRAIN

MAX14611 toc01

8Mbps,

PUSH-PULL

8Mbps,

PUSH-PULL

1200

1000

800

600

400

SUPPLY CURRENT (µA)

200

0

1.65 5.50

603510-15-40 85

4540353025 50

VCC SUPPLY CURRENT

vs. SUPPLY VOLTAGE

DRIVING I/OVL_

= 1.8V

V

L

8Mbps,

PUSH-PULL

MAX14611 toc04

MAX14611 toc06

VCC (V)

500kbps,

OPEN-DRAIN

4.954.402.20 2.75 3.30 3.85

SUPPLY CURRENT (µA)

RISE/FALL TIME (ns)

MAX14611 toc02

200

DRIVING I/OVL_

180

160

140

120

100

80

60

40

20

0

100

DRIVING I/OVL_

90

500kbps, OPEN-DRAIN

80

70

60

50

40

30

20

10

0

VL SUPPLY CURRENT

vs. TEMPERATURE

200

DRIVING I/OVCC_

175

150

125

100

75

SUPPLY CURRENT (µA)

50

25

0

VL SUPPLY CURRENT

vs. CAPACITIVE LOAD

8Mbps,

PUSH-PULL

500kbps,

OPEN-DRAIN

CAPACITIVE LOAD (pF)

RISE/ FALL TIME

vs. CAPACITIVE LOAD

t

HL

CAPACITIVE LOAD (pF)

8Mbps,

PUSH-PULL

500kbps,

OPEN-DRAIN

TEMPERATURE (°C)

4540353025 50

t

LH

4540353025 50

603510-15-40 85

MAX14611 toc05

MAX14611 toc07

MAX14611 toc03

�� Maxim Integrated Products 7

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Typical Operating Characteristics (continued)

(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull operation, unless otherwise noted.)

20

DRIVING I/OVL_

18

8Mbps, PUSH-PULL

16

14

12

10

8

RISE/FALL TIME (ns)

6

4

2

0

RISE/ FALL TIME

vs. CAPACITIVE LOAD

t

LH

t

HI

CAPACITIVE LOAD (pF)

RISE/FALL TIME

vs. CAPACITIVE LOAD

150

DRIVING I/OVCC_ 500kbps, OPEN-DRAIN

125

100

75

50

RISE/FALL TIME (ns)

25

0

t

HL

CAPACITIVE LOAD (pF)

PROPAGATION DELAY vs. CAPACITIVE LOAD

6

DRIVING I/OVCC_ 500kbps, OPEN-DRAIN

5

4

3

2

PROPAGATION DELAY (ns)

1

0

t

PHL

CAPACITIVE LOAD (pF)

4540353025 50

t

PLH

8

MAX14611 toc08

t

7

6

5

4

3

PROPAGATION DELAY (ns)

2

1

0

LH

4540353025 50

PROPAGATION DELAY

vs. CAPACITIVE LOAD

DRIVING I/OVL_ 500kbps, OPEN-DRAIN

CAPACITIVE LOAD (pF)

MAX14611 toc11

MAX14611 toc13

PROPAGATION DELAY vs. CAPACITIVE LOAD

6

DRIVING I/OVL_ 8Mbps, PUSH-PULL

MAX14611 toc09

t

PHL

t

PLH

4540353025 50

5

4

3

2

PROPAGATION DELAY (ns)

1

0

t

PHL

t

PLH

CAPACITIVE LOAD (pF)

4540353025 50

RISE/ FALL TIME

vs. CAPACITIVE LOAD

10

DRIVING I/OVCC_

9

8Mbps, PUSH-PULL

8

7

6

5

4

RISE/FALL TIME (ns)

3

2

1

0

t

HL

CAPACITIVE LOAD (pF)

t

LH

4540353025 50

MAX14611 toc12

PROPAGATION DELAY

vs. CAPACITIVE LOAD

4.0

DRIVING I/OVCC_

3.5

8Mbps, PUSH-PULL

3.0

2.5

2.0

1.5

PROPAGATION DELAY (ns)

1.0

0.5

0

CAPACITIVE LOAD (pF)

t

PHL

t

PLH

4540353025 50

MAX14611 toc14

MAX14611 toc10

�� Maxim Integrated Products 8

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Typical Operating Characteristics (continued)

(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull operation, unless otherwise noted.)

50

DRIVING I/OVCC_

45

4Mbps, OPEN-DRAIN 1kI EXTERNAL PULLUP

40

35

30

25

20

RISE/FALL TIME (ns)

15

10

5

0

50

DRIVING I/OVL_

45

4Mbps, OPEN-DRAIN 1kI EXTERNAL PULLUP

40

35

30

25

20

RISE/FALL TIME (ns)

15

10

5

0

RISE/ FALL TIME

vs. CAPACITIVE LOAD

t

LH

t

HL

4540353025 50

CAPACITIVE LOAD (pF)

RISE/ FALL TIME

vs. CAPACITIVE LOAD

t

LH

t

HL

4540353025 50

CAPACITIVE LOAD (pF)

LOW-TO-HIGH TRANSITION,

OPEN-DRAIN ZOOM

MAX14611 toc19

MAX14611 toc15

MAX14611 toc17

20

16

12

8

PROPAGATION DELAY (ns)

4

0

6

4

2

0

-2

SUPPLY CURRENT (µA)

-4

-6

-8

ENTERING AND EXITING THREE-STATE MODE

PROPAGATION DELAY

vs. CAPACITIVE LOAD

DRIVING I/OVL_ 4Mbps, OPEN-DRAIN 1kI EXTERNAL PULLUP

t

PLH

t

PHL

4540353025 50

CAPACITIVE LOAD (pF)

PROPAGATION DELAY

vs. CAPACITIVE LOAD

DRIVING I/OVCC_ 4Mbps, OPEN-DRAIN 1kI EXTERNAL PULLUP

t

PHL

t

PLH

50% I/O VCC_ TO 50% I/OVL_ (SEE TOC19)

4540353025 50

CAPACITIVE LOAD (pF)

(DRIVING I/OVCC_, C

LOAD

= 50pF)

MAX14611 toc20

MAX14611 toc16

MAX14611 toc18

4ns/div

10ms/div

�� Maxim Integrated Products 9

TOP VIEW

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Pin Configurations

I/OVL1

I/OVL2

N.C.

I/OVL3

1

+

2

3

4

5

6

7

MAX14611

*EP

14

13

12

11

10

9

8

V

CC

I/OVCC1

I/OVCC2TS

N.C.

V

L

I/OVCC3I/OVL4

I/OVCC4GND

TDFN

*CONNECT EXPOSED PAD TO GND.

TDFN-EP TSSOP

NAME FUNCTION

1 2 I/OVL1 Input/Output 1. Reference to VL.

2 3 I/OVL2 Input/Output 2. Reference to VL.

Three-State Select Input. Drive TS low to place the device in three-state output mode. I/OVCC_

3 8

TS

and I/OVL_ are high impedance in three-state output mode. Note: Logic referenced to VL (for logic thresholds, see the Electrical Characteristics table).

4, 11 6,9 N.C. No Connection. Not internally connected.

5 4 I/OVL3 Input/Output 3. Reference to VL.

6 5 I/OVL4 Input/Output 4. Reference to VL.

7 7 GND Ground

8 10 I/OVCC4 Input/Output 4. Reference to V

CC.

9 11 I/OVCC3 Input/Output 3. Reference to VCC.

10 1 V

Logic Supply Voltage Input, 0.9V P VL P min (5.0V, (VCC + 0.3V)). Connect a 0.1FF ceramic

L

capacitor as close as possible to the pin.

12 12 I/OVCC2 Input/Output 2. Reference to VCC.

13 13 I/OVCC1 Input/Output 1. Reference to VCC.

14 14 V

— — EP

Power Supply Input. The supply range is 1.65V P VCC P 5.5V. Bypass VCC with a 1FF ceramic

CC

capacitor as close as possible to the pin to achieve higher ESD protection (Q6kV HBM).

Exposed Pad (TDFN Only). EP is internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.

I/OVL1

I/OVL2

I/OVL4

N.C.

+

1

V

L

2

3

MAX14611

4

5

6

7

14

V

CC

13

I/OVCC1

12

I/OVCC2

11

I/OVCC3I/OVL3

10

I/OVCC4

9

N.C.

8

TSGND

TSSOP

Pin Description

�� Maxim Integrated Products 10

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Functional Diagram

V

L

MAX14611

PU1 PU2

I/OVL_

ONE-SHOT

BLOCK

EN CONTROL

BLOCK

Detailed Description

The MAX14611 ESD-protected level translator provides the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. A low-voltage logic signal present on the VL side of the device appears as a high-voltage logic signal on the VCC side of the device, and vice-versa.

The MAX14611 bidirectional level translator utilizes a transmission-gate based design (see the

Functional Diagram) to allow data translation in either

direction (VL ↔ VCC) on any single data line. The device accepts VL from +0.9V to +5.0V and VCC from +1.65V to +5.5V, making it ideal for data transfer between lowvoltage ASICs/PLDs and higher voltage systems.

The device features a three-state output mode, thermal short-circuit protection, and Q6kV ESD protection on the VCC side for greater protection in applications that route signals externally.

TS V

ONE-SHOT

BLOCK

GATE DRIVE

N

CC

I/OVCC_

Level Translation

For proper operation, ensure that +1.65V P VCC P +5.5V,

0.9V P VL P 5.0V, and VL P (VCC + 0.3V). It is permissible for VL to exceed (VCC + 0.3V) during power-up sequencing. During power-supply sequencing, when VCC is disconnected and VL is powered up, a current can be sourced without a latchup or any damage to the device. The maximum data rate of the MAX14611 depends heavily on load capacitance (see the Typical Operating

Characteristics), output impedance of the driver, and

the operational voltage (see the Timing Characteristics table).

Speed-Up Circuitry

The device features a one-shot generator that decreases the rise time of the output. When triggered following a rising edge, MOSFETs PU1 and PU2 turn on for a short time to pull up I/OVL_ and I/OVCC_ to their respective supplies (see the Functional Diagram). This greatly reduces the rise time and propagation delay for the low-to-high transition.

�� Maxim Integrated Products 11

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Rise-Time Accelerators (Figure 5)

The device has internal rise-time accelerators, allowing operation up to 20Mbps. The rise-time accelerators are present on both sides of the device and act to speed up the rise time of the input and output of the device, regardless of the direction of the data. The triggering mechanism for these accelerators is both level and edge sensitive. To prevent false triggering of the rise-time accelerators and to take full advantage of them, signal rise/fall times of less than 2ns/V are recommended for both sides of the device in open-drain driving. The recommendation applies only for fail time. Under less noisy conditions, longer signal fall times can be acceptable.

Three-State Output Mode (TS)

Drive TS low to place the device in three-state output mode. Connect TS to VL (logic-high) for normal operation. Activating the three-state output mode disconnects the internal 10kI pullup resistors on the I/OVCC_ and I/OVL_ lines. This forces the I/O lines to a high-impedance state and decreases the supply current to less than 1FA. The high-impedance I/O lines in three-state output mode allow for use in a multidrop network. When in three-state output mode, keep the I/OVL_ voltage below (VL + 0.3V), and keep the I/OVCC_ voltage below (VCC + 0.3V).

Thermal Short-Circuit Protection

Thermal-overload detection protects the device from short-circuit fault conditions. In the event of a short-circuit fault and when the junction temperature (TJ) reaches +150NC (typ), a thermal sensor signals the three-state output mode logic to force the device into three-state output mode. When TJ has cooled to +130NC (typ), normal operation resumes.

High ESD Protection

As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic

discharges encountered during handling and assembly. The I/OVCC_ lines have extra protection against static electricity. Maxim’s engineers have developed state-ofthe-art structures to protect these pins against ESD of ±6kV without damage.

The ESD structures withstand high ESD in all states: normal operation, three-state output mode, and powered down. After an ESD event, the device keeps working without latchup, whereas competing products can latch and must be powered down to remove latchup. ESD protection can be tested in various ways. The I/OVCC_ lines of this product family are characterized for protection.to ±6kV using the Human Body Model.

ESD Test Conditions

Contact Maxim for a reliability report that documents test setup, test methodology, and test results.

Applications Information

Power-Supply Decoupling

Bypass VL to ground with a 0.1FF capacitor to reduce ripple and ensure correct data transmission. See the

Typical Operating Circuit. To ensure full Q6kV ESD

protection, bypass VCC to ground with a 1FF capacitor. Place all capacitors as close as possible to the powersupply pins (V

The device can be driven in a push-pull configuration. The device includes internal 10kI resistors that pull up I/OVL_ and I/OVCC_ to their respective power supplies, allowing operation of the I/O lines with open-drain devices. See the Timing Characteristics table for maximum data rates when using open-drain drivers (Figure 1,

Figure 2, Figure 3, Figure 4).

and V L).

CC

Push-Pull vs. Open-Drain Driving

�� Maxim Integrated Products 12

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

VL = +1.8V V

+1.8V SYSTEM

CONTROLLER

EN

SDA

SCL

SDA

SCL

Figure 5. Open-Drain Operation

0.1µF 1µF

V

L

V

L

TS

I/OVL1

V

L

V

CC

I/OVCC1

MAX14611

I/OVL2

V

L

I/OVL3

V

L

I/OVL4

I/OVCC2

I/OVCC3

I/OVCC4

GNDGND GND

= +3.3V

CC

+3.3V

SYSTEM

V

CC

V

SDA

CC

SCL

CC

SDA

CC

SCL

Applications Circuit

+1.8V +3.3V

0.1µF 1µF

V

L

TS

V

CC

MAX14611

+1.8V SYSTEM

CONTROLLER

I/OVL1

DATA DATA

I/OVL2

I/OVL3

I/OVL4

I/OVCC1

I/OVCC2

I/OVCC3

I/OVCC4

+3.3V

SYSTEM

�� Maxim Integrated Products 13

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX14611ETD+ MAX14611EUD+**

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product—contact factory for availability.

-40NC to +85NC

14 TDFN-EP* 14 TSSOP

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

14 TDFN-EP T1433+2

14 TSSOP U14+1

PACKAGE

CODE

OUTLINE

NO.

21-0137 90-0063 21-0066 90-0113

LAND

PATTERN NO.

�� Maxim Integrated Products 14

MAX14611

Quad Bidirectional Low-Voltage

Logic-Level Translator

Revision History

REVISION

NUMBER

0 4/12 Initial release —

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 15

©

2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

MAXIM MAX14611 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Applications

Benefits and Features

Typical Operating Circuit

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

TIMING CHARACTERISTICS

Figure 1. Push-Pull Driving I/OVL_

Figure 2. Open-Drain Driving I/OVL_

Figure 3. Push-Pull Driving I/OVCC_

Figure 4. Open-Drain Driving I/OVCC_

Typical Operating Characteristics

Pin Configurations

Pin Description

Functional Diagram

Detailed Description

Level Translation

Speed-Up Circuitry

Rise-Time Accelerators (Figure 5)

Three-State Output Mode (TS)

Thermal Short-Circuit Protection

High ESD Protection

ESD Test Conditions

Applications Information

Power-Supply Decoupling

Push-Pull vs. Open-Drain Driving

Figure 5. Open-Drain Operation

Applications Circuit

Ordering Information

Chip Information

Package Information

Revision History