The MAX14550E is a USB Hi-Speed analog switch with
a USB host charger (dedicated charger) identification
circuit. The MAX14550E supports both the USB Battery
Charging Specification Revision 1.0 and a set resistor
bias for AppleM-compliant devices.
The MAX14550E features a high-performance Hi-Speed
USB switch with low 4pF (typ) on-capacitance and low
4I (typ) on-resistance. In addition, the MAX14550E
features two digital inputs (CB0 and CB1) to switch
between pass-through and charger modes. The USB
host charger identification circuit allows a host USB port
to support USB chargers with shorted D+/D- detection
and to provide support for Apple-compliant devices
using a resistor bias. When an Apple-compliant device
is attached to the port, the MAX14550E provides the
voltage from the resistor-divider. The MAX14550E uses
the internal or external resistor based on the voltage at
RDP. If a USB Revision 1.0-compliant device is attached,
the MAX14550E connects a short across DP and DM to
allow correct charger detection. The MAX14550E autodetection circuit can be disabled and either a DP/DM
short or resistor network is chosen as the default.
The MAX14550E has enhanced high electrostatic discharge (ESD) protection on the DP and DM inputs up to
Q15kV Human Body Model (HBM).
The MAX14550E is available in a 10-pin (3mm x 3mm)
TDFN package and is specified over the -40NC to +85NC
extended temperature range.
Features
S USB 2.0 Hi-Speed Switching
S Low 4.0pF On-Capacitance
S Low 4.0ω On-Resistance
S Ultra-Low 0.1ω On-Resistance Flatness
S +2.8V to +5.5V Supply Range
S Ultra-Low 7µA Supply Current
S Automatic USB Charger Identification Circuit
S Optional External Resistor-Divider with Auto
Selection
S ±15kV High ESD HBM Protection on DP/DM
S 3mm x 3mm, 10-Pin TDFN Package
Applications
Laptops
Netbooks
Cell Phones
Ordering Information
PARTTEMP RANGE
MAX14550EETB+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
-40NC to +85NC
PIN-
PACKAGE
10 TDFN-EP*AWG
TOP
MARK
MAX14550E
Typical Operating Circuit appears at end of data sheet.
Note 1:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
MAX14550E
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VCC = +2.8V to +5.5V, TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC, unless
otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Power-Supply VoltageV
Supply CurrentI
Supply Current Increase
Analog Signal RangeVDP, V
ANALOG SWITCH
On-Resistance TDP/TDM
Switch
On-Resistance Match
Between Channels TDP/TDM
Switch
R
DR
DI
CC
CC
CC
ONT
ONT
VCC = 3.3V
VCC = 5.5V
0V P V
DM
0V P V
P VIL or VIH P V
CB_
P VCC, I
DP/DM
VDP = VDM = 400mV, IDP or IDM = 10mA0.1
Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Soldering Temperature (Reflow) .......................................260NC
2.85.5V
V
= VCB = V
CB0
V
= 0V, VCB = V
CB0
CC
CC
0.72
6.510
External resistors used,
V
= VCB = 0V or
CB0
V
= VCC, VCB = 0V
CB0
712
Internal resistors used,
V
= VCB = 0V or
CB0
V
= VCC, VCB = 0V
CB0
V
= VCB = V
CB0
V
= 0V, VCB = V
CB0
CC
CC
76120
2.57
8.515
External resistors used,
V
= VCB = 0V or
CB0
V
= VCC, VCB = 0V
CB0
916
Internal resistors used,
V
= VCB = 0V or
CB0
V
= VCC, VCB = 0V
CB0
or IDM = 10mA
DP
CB_
P V
CC
0V
125180
2
CC
46.5
FA
FA
V
I
I
2
USB Host Charger Identification Analog Switch
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.8V to +5.5V, TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC, unless
otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
On-Resistance Flatness TDP/
TDM Switch
On-Resistance RDP/RDM
Switch
On-Resistance Flatness RDP/
RDM Switch
On-Resistance of DP/DM
Short
R
FLATT
R
ONR
R
FLATR
R
SHORT
VDP = VDM, 0V P VDP P VCC,
IDP = IDM = 10mA
0.4V P V
RDP/RDM
P VCC, I
RDP
= I
10mA
V
= V
RDP
I
= I
RDP
V
= 0V, VCB = VCC, VDP = VDM,
CB0
RDM
RDM
, 0.4V P V
= 10mA
RDP
P VCC,
0V P VDP P VCC, IDP = IDM = 1mA
RDM
=
0.1
47.5
0.1
5070
I
I
I
I
MAX14550E
TDP/TDM Off-Leakage
Current
DP/DM On-Leakage Current
I
TDPOFF
I
TDMOFF
I
DPON
I
DMON
DYNAMIC PERFORMANCE
Turn-On Timet
Turn-Off Timet
TDP/TDM Switch Propagation
Delay
Output Skew Between
Switches
TDP/TDM Off-CapacitanceC
DP/DM On-Capacitance
(Connected to TD_ )
t
PLH
ON
OFF
, t
t
SK(O)
OFF
C
ON
-3dB BandwidthBW
Off-IsolationV
CrosstalkV
ISO
CT
INTERNAL RESISTORS
DP/DM Short PulldownR
PD
RP1/RP2 RatioRT
RP1 + RP2 ResistanceR
RP
RM1/RM2 RatioRT
RM1 + RM2 ResistanceR
RM
RP
RM
,
VCC = 5.5V, V
VDM = 5.5V to 0V, V
,
VCC = 5.5V, V
= VCC, VCB = 0V, VDP =
CB0
= V
TDP
TDM
= VCB = VCC,
CB0
VDP = VDM = 5.5V to 0V
V
TDP
or V
= 1.5V, RL = 300I,
TDM
CL = 35pF, VIH = VCC, VIL = 0V, Figure 1
V
TDP
or V
= 1.5V, RL = 300I,
TDM
CL = 35pF, VIH = VCC, VIL = 0V, Figure 1
RL = RS = 50I
PHL
Skew between DP and DM when connected
to TDP and TDM, RL = RS = 50I, Figure 2
f = 1MHz, V
BIAS
= 0V, V
SIGNAL
(Note 3)
f = 240MHz, V
V
SIGNAL
= 500mV
BIAS
= 0V,
P-P
RL = RS = 50I
V
, VDP = 0dBm, RL = RS = 50I,
TDP
f = 250MHz, Figure 3
V
, VDP = 0dBm, RL = RS = 50I,
TDP
f = 250MHz, Figure 3
= 0V to 5.5V
= 500mV
P-P
-250+250nA
-250+250nA
20100
2.55
Fs
Fs
60ps
40ps
2.0pF
4.05.5pF
1000MHz
-20dB
-25dB
350500700
kI
1.4851.51.515Ratio
93.75125156.25
kI
0.8540.8630.872Ratio
69.7593116.25
kI
3
USB Host Charger Identification Analog Switch
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.8V to +5.5V, TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC, unless
otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
COMPARATORS
V
> 0.4V, DM falling1.92.12.3V
DM Comparator ThresholdV
DP and RDP Comparator
Threshold
MAX14550E
DM Comparator Hysteresis1%V
V
DMF
DPR
DP and RDP Comparator
Hysteresis
DM Comparator Debounce
Time
DP Comparator Debounce
Time
t
DM
t
DP
DIGITAL I/O (CB0, CB1)
Input Logic Voltage HighV
Input Logic Voltage LowV
Input Logic HysteresisV
Input Leakage CurrentI
IH
IL
HYST
IN
ESD PROTECTION
All PinsHuman Body Model
ESD Protection Level (DP and
DM Only)
RDP
V
< 0.3V, DM falling444546%V
RDP
DP or RDP falling0.30.350.4V
1%V
VDM from 2.8V to 1.5V30100200
VDP from 0.7V to 0V30100200
1.4V
0.4V
100mV
VCC = 5.5V, 0V P V
VIH P V
CB_
P V
CC
Human Body Model
CB_
P VIL or
-250+250nA
Q2
Q15
kV
kV
Fs
Fs
CC
DMF
DPR
Note 2: All devices are 100% production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Guaranteed by design.
Test Circuits/Timing Diagrams
V
CC
tR < 5ns
t
< 5ns
F
t
OFF
0.9 x V
OUT
TD_
V
IN
CB0
LOGIC
INPUT
C
INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
V
OUT
R
Figure 1. Switching Time
4
= V
GND
IN (
R
L
CB1
+ R
V
MAX14550E
L
)
ON
V
CC
D_
R
L
V
OUT
C
L
LOGIC
INPUT
SWITCH
OUTPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
IH
V
IL
0V
50%
V
OUT
0.9 x V
0UT
t
ON
USB Host Charger Identification Analog Switch
Test Circuits/Timing Diagrams (continued)
MAX14550E
IN+
R
S
R
IN-
S
MAX14550E
TDP
TDM
DP
C
L
DM
C
L
V
CC
RISE TIME DELAY = |t
FALL TIME DELAY = |t
RISE TIME TO FALL TIME MISMATCH = |t
OUT+
OUT-
INRISE
INFALL
- t
- t
OUTRISE
OUTFALL
|
|
OUTFALL
- t
OUTRISE
|
CB0CB1
V
CC
t
INFALL
V
CC
V
IN+
0V
V
CC
V
IN-
0V
50%
50%
90%
10%
t
OUTFALL
t
INRISE
10%
t
OUTRISE
90%
V
CC
V
OUT+
0V
V
CC
V
OUT-
0V
Figure 2. Output Signal Skew
t
SK(0)
50%
50%
90%
10%
90%
10%
5
USB Host Charger Identification Analog Switch
TDP/TDM ON-RESISTANCE
Test Circuits/Timing Diagrams (continued)
V
OUT
V
IN
V
OUT
V
IN
0V OR V
CC
CB1
CB0V
MAX14550E
MAX14550E
V
CC
CC
TDP
DP*
V
IN
V
OUT
MEASREF
NETWORK
ANALYZER
50I
50I50I
50I
OFF-ISOLATION = 20log
CROSSTALK = 20log
SWITCH IS ENABLED.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
*FOR CROSSTALK, THIS PIN IS DM.
TDM AND DP ARE OPEN.
Figure 3. Off-Isolation and Crosstalk
Typical Operating Characteristics
(T
= +25°C, unless otherwise noted.)
A
RDP/RDM ON-RESISTANCE
4.5
4.0
3.5
3.0
2.5
(I)
ON
R
2.0
1.5
1.0
0.5
0
05.5
VCC = 2.8V
vs. SUPPLY VOLTAGE
TDP/TDM ON-RESISTANCE vs. V
5.0
4.5
4.0
MAX14550E toc01
3.5
3.0
(I)
2.5
ON
VCC = 5.5V
5.04.53.5 4.01.0 1.5 2.0 2.5 3.00.5
V
(V)
TDP
R
2.0
1.5
1.0
0.5
0
03.3
TA = +85°C
TA = +25°C
TA = -40°C
V
TDP/TDM
(V)
TDP/TDM
VCC = 3.3V
5.0
4.5
4.0
MAX14550E toc02
3.5
3.0
(I)
2.5
ON
R
2.0
1.5
1.0
0.5
3.02.72.1 2.40.6 0.9 1.2 1.5 1.80.3
0
vs. SUPPLY VOLTAGE
VCC = 2.8V
VCC = 5.5V
V
(V)
RDP
5.55.04.0 4.51.0 1.5 2.0 2.5 3.0 3.50.506.0
MAX14550E toc03
6
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