General Description
The MAX1446 10-bit, 3V analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and
wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in
imaging and digital communications. The MAX1446
operates from a single 2.7V to 3.6V supply, consuming
only 90mW while delivering a 59.5dB signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz, -3dB bandwidth and
may be operated with single-ended inputs. In addition
to low operating power, the MAX1446 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is used
to set the ADC full-scale range. A flexible reference
structure allows the user to supply a buffered, direct or
externally derived reference for applications requiring
increased accuracy or a different input voltage range.
Lower and higher speed, pin-compatible versions of
the MAX1446 are also available. Refer to the MAX1444
data sheet for a 40Msps version, the MAX1448 data
sheet for an 80Msps version, and the MAX1449 data
sheet for a 105Msps version.
The MAX1446 has parallel, offset binary, three-state
outputs that can be operated from 1.7V to 3.3V to allow
flexible interfacing. The device is available in a 5mm x
5mm, 32-pin TQFP package and is specified over the
extended industrial (-40°C to +85°C) and automotive
(-40°C to +105°C) temperature ranges.
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
Features
o Single 3.0V Operation
o Excellent Dynamic Performance
59.5dB SNR at f
IN
= 20MHz
73dB SFDR at fIN= 20MHz
o Low Power:
30mA (Normal Operation)
5µA (Shutdown Mode)
o Fully Differential Analog Input
o Wide 2V
P-P
Differential Input Voltage Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o CMOS-Compatible Three-State Outputs
o 32-Pin TQFP Package
o Evaluation Kit Available (MAX1448 EV Kit)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
________________________________________________________________
Maxim Integrated Products
1
Functional Diagram
19-1729; Rev 4; 11/08
EVALUATION KIT
AVAILABLE
Ordering Information
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Pin-Compatible,
Lower/Higher Speed Versions
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE
MAX1446EHJ+ -40°C to +85°C 32 TQFP
MAX1446GHJ+ -40°C to +105°C 32 TQFP
PINPACKAGE
PART SAMPLING SPEED (Msps)
MAX1444 40
MAX1448 80
MAX1449 105
CLK
IN+
MAX1446
CONTROL
10
D
T/H
IN-
PD
REF
PIPELINE ADC
REF SYSTEM +
BIAS
REFINREFOUT REFP COM REFN OE
E
C
OUTPUT
DRIVERS
V
DD
GND
D9–D0
OV
DD
OGND
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= 3.0V, OVDD= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL≈ 10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to V
DD
REFIN, REFOUT, REFP,
REFN, and COM to GND.........................-0.3V to (V
DD
+ 0.3V)
OE, PD, CLK to GND..................................-0.3V to (V
DD
+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW
Operating Temperature Ranges:
MAX1446EHJ+ .................................................-40°C to +85°C
MAX1446GHJ+...............................................-40°C to +105°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL f
Differential Nonlinearity DNL No missing codes, f
Offset Error -1.6 < ±0.1 ±1.9 % FS
Gain Error TA ≥ +25°C 0 ±2.0 % FS
ANALOG INPUT
Input Differential Range V
Common-Mode Voltage Range V
Input Resistance R
Input Capacitance C
CONVERSION RATE
Maximum Clock Frequency f
Data Latency 5.5 Cycles
DYNAMIC CHARACTERISTICS
Signal-to-Noise + Distortion
(Up to 5th Harmonic)
Spurious-Free Dynamic
Range
DIFF
COM
CLK
SINAD
SFDR
= 7.492MHz, TA ≥ +25°C ±0.6 ±1.9 LSB
IN
= 7.492MHz ±0.4 ±1.0 LSB
IN
Differential or single-ended inputs ±1.0 V
Switched capacitor load 33 kΩ
IN
IN
fIN = 7.492MHz 57 59.5
fIN = 19.943MHz 56.5 59.5Signal-to-Noise Ratio SNR
= 39.9MHz (Note 1) 59
f
IN
fIN = 7.492MHz 56.6 59.4
fIN = 19.943MHz 56.2 59
f
= 39.9MHz (Note 1) 58.5
IN
fIN = 7.492MHz 65 74
fIN = 19.943MHz 63 73
f
= 39.9MHz (Note 1) 71
IN
VDD/2
± 0.5
5pF
60 MHz
V
dB
dB
dBc
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL≈ 10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 7.492MHz -74
dBc
Two-Tone Intermodulation
Distortion
Third-Order Intermodulation
Distortion
IMD
IM3
TT
fIN = 19.943MHz -73Third-Harmonic Distortion HD3
= 39.9MHz (Note 1) -71
f
IN
f
= 19MHz at -6.5dBFS,
1
f
= 21MHz at -6.5dBFS (Note 2)
2
f
= 19MHz at -6.5dBFS
1
= 21MHz at -6.5dBFS (Note 2)
f
2
-75 dBc
-75 dBc
fIN = 7.492MHz -70 -64
Total Harmonic Distortion
(First 5 Harmonics)
THD
fIN = 19.943MHz -70 -63
f
= 39.9MHz (Note 1) -69
IN
dBc
Small-Signal Bandwidth Input at -20dBFS, differential inputs 500 MHz
Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs 400 MHz
Aperture Delay t
Aperture Jitter t
AD
AJ
1ns
2 psrms
Overdrive Recovery Time For 1.5 × full-scale input 2 ns
Differential Gain ±1%
Differential Phase ±0.25 °
Output Noise IN+ = IN- = COM 0.2 LSBrms
INTERNAL REFERENCE
Reference Output Voltage REFOUT
Reference Temperature
Coefficient
TC
REF
2.048
±1%
60 ppm/°C
V
Load Regulation 1.25 mV/mA
BUFFERED EXTERNAL REFERENCE (V
REFIN Input Voltage V
P osi ti ve Refer ence Outp ut V ol tag eV
N eg ati ve Refer ence Outp ut
V ol tag e
Common-Mode Level V
Differential Reference Output
Voltage Range
REFIN Resistance R
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
REFIN
REFP
V
REFN
COM
ΔV
REFIN
I
SOURCE
I
SINK
REFIN
REF
= 2.048V)
ΔV
= V
REF
REFP
- V
2.048
2.012 V
0.988 V
VDD/2 V
, TA ≥ +25°C 0.98 1.024 1.07 V
REFN
> 50 MΩ
5mA
-250 µA
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL≈ 10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Maximum REFN Source Current I
Maximum REFN Sink Current I
UNBUFFERED EXTERNAL REFERENCE (V
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
Differential Reference Input
Voltage Range
COM Input Voltage Range V
REFP Input Voltage V
REFN Input Voltage V
DIGITAL OUTPUTS (CLK, PD, OE)
Input High Threshold V
Input Low Threshold V
Input Hysteresis V
Input Leakage
Input Capacitance C
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low V
Output Voltage High V
Three-State Leakage Current I
SOURCE
SINK
= AGND, reference voltage applied to REFP, REFN, and COM)
REFIN
R
,
Measured between REFP and COM and
REFN and COM
IN
ΔV
REF
REF
= V
REFP
- V
REFN
R
ΔV
REFP
REFN
C
COM
REFP
REFN
CLK
IH
PD, OE
CLK
IL
PD, OE
HYST
I
IH
I
IL
OL
OH
LEAK
VIH = V
DD
= OV
DD
VIL = 0 ±5
IN
I
= 200µA 0.2 V
SINK
I
OE = OV
SOURCE
= 200µA
DD
250 µA
-5 mA
4KΩ
15 pF
1.024
±10%
VDD/2
±10%
V
+
COM
/2
ΔV
REF
V
-
COM
/2
ΔV
REF
0.8 x
V
DD
0.8 x
OV
D D
0.2 x
V
0.2 x
OV
0.1 V
±5
5pF
OV
-
DD
0.2
±10 µA
DD
D D
V
V
V
V
V
V
µA
V
Three-State Output Capacitance C
OUT
OE = OV
DD
5pF
MAX1446
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V
IH
, VIL.
Note 4: Wake-up time is defined as the time from complete reference power-down until the ADC performs within 0.3 ENOB of the
final performance for f
IN
= 10MHz at -0.5dBFS input amplitude. V
REFIN
= 2.048V, REFP, REFN, and CML decoupled with
2.3µF.
Note 5: Dynamic characteristics guaranteed at f
IN
= 19.943MHz for the specified duty-cycle range.
Note 6: Guaranteed by design and engineering characterization.
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL≈ 10pF at digital outputs, f
CLK
= 62.5MHz
(50% duty cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage V
Output Supply Voltage OV
Analog Supply Current I
Output Supply Current I
Power-Supply Rejection PSRR
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid t
OE Fall to Output Enable t
OE Rise to Output Disable t
Clock Duty Cycle Figure 6, clock period 16ns (Notes 5, 6) 45 55 %
Wake-Up Time t
DD
VDD
OVDD
DO
ENABLE
DISABLE
WAKE
CL = 10pF 1.7 3.0 3.6 V
DD
Operating, fIN = 19.943MHz at -0.5dBFS 30 37 mA
Shutdown, clock idle, PD = OE = OV
Operating, CL = 15pF, fIN = 19.943MHz at
-0.5dBFS
Shutdown, clock idle, PD = OE = OV
Offset ± 0.1 mV/V
Gain ± 0.1 %/V
Figure 5 (Notes 3, 6) 2 5 8 ns
Figure 5 10 ns
Figure 5 1.5 ns
(Notes 4, 6) 366 520 µs
DD
DD
2.7 3.0 3.6 V
415µA
7mA
120µA
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD= 3.0V, OVDD= 2.7V, internal reference, differential input at -0.5dBFS, f
CLK
= 62.35MHz, CL≈ 10pF, TA= +25°C, unless
otherwise noted.)
MAX1446 toc01
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 7.5MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SFDR = 72.2dBc
SNR = 60.1dB
THD = -71.5dBc
SINAD = 59.8dB
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 13.3MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1446 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SINAD = 59.3dB
SNR = 59.5dB
THD = -72.9dBc
SFDR = 74.3dBc
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 20MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1446 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SINAD = 59.3dB
SNR = 59.6dB
THD = -70.7dBc
SFDR = 72.2dBc
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 26.8MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1446 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SINAD = 59.0dB
SNR = 59.4dB
THD = -70.5dBc
SFDR = 72.9dBc
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 50MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1446 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SFDR = 70dBc
SNR = 59.1dB
THD = -67.1dBc
SINAD = 58.5dB
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 7.5MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
MAX1446 toc06
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SINAD = 59.5dB
SNR = 59.7dB
THD = -73.0dBc
SFDR = 73.6dBc
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
FFT PLOT
(f
IN
= 20MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
MAX1446 toc07
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SINAD = 59.2dB
SNR = 59.5dB
THD = -70.7dBc
SFDR = 71.1dBc
HD2
HD3
-100
-70
-80
-90
-50
-60
-10
-20
-30
-40
0
0 5 10 15 20 25 30 35
TWO-TONE INTERMODULATION
(8192-POINT IMD,
DIFFERENTIAL INPUT)
MAX1446 toc08
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f1 = 19MHz AT -6.5dBFS
f2 = 21MHz AT -6.5dBFS
3RD IMD = -76dBc
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
(A
IN
= -0.5dBFS)
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
MAX1446 toc09
0 102030405060708090
50
55
60
65
70
75
80
DIFFERENTIAL
SINGLE-ENDED
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 2.7V, internal reference, differential input at -0.5dBFS, f
CLK
= 62.35MHz, CL≈ 10pF, TA= +25°C, unless
otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
TEMPERATURE (°C)
SFDR (dBc)
MAX1446 toc17
-40 -15 10 35 60 85
60
64
68
72
76
80
fIN = 19.943MHz, AIN = -0.5dBFS
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
TEMPERATURE (°C)
SNR (dB)
MAX1446 toc18
-40 -15 10 35 60 85
50
54
58
62
66
70
fIN = 19.943MHz, AIN = -0.5dBFS
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
(A
IN
= -0.5dBFS)
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
MAX1446 toc10
0 102030405060708090
55
56
57
58
59
60
DIFFERENTIAL
SINGLE-ENDED
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
(A
IN
= -0.5dBFS)
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
MAX1446 toc11
0 102030405060708090
-80
-75
-70
-65
-60
-55
-50
DIFFERENTIAL
SINGLE-ENDED
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCY
(A
IN
= -0.5dBFS)
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
MAX1446 toc12
0 102030405060708090
52
53
54
55
56
57
58
59
60
DIFFERENTIAL
SINGLE-ENDED
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
(f
IN
= 19.943MHz)
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
MAX1446 toc13
-20 -16 -12 -8 -4 0
50
55
60
65
70
75
80
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
(f
IN
= 19.943MHz)
ANALOG INPUT POWER (dBFS)
SNR (dB)
MAX1446 toc14
-20 -16 -12 -8 -4 0
30
36
42
48
54
60
66
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
(f
IN
= 19.943MHz)
ANALOG INPUT POWER (dBFS)
THD (dBc)
MAX1446 toc15
-20 -16 -12 -8 -4 0
-80
-75
-70
-65
-60
-55
-50
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT POWER
(f
IN
= 19.943MHz)
ANALOG INPUT POWER (dBFS)
SINAD (dB)
MAX1446 toc16
-20 -16 -12 -8 -4 0
30
35
40
45
50
55
60
65
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 2.7V, internal reference, differential input at -0.5dBFS, f
CLK
= 62.35MHz, CL≈ 10pF, TA= +25°C, unless
otherwise noted.)
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
TEMPERATURE (°C)
THD (dBc)
MAX1446 toc19
-40 -15 10 35 60 85 110
-80
-76
-72
-68
-64
-60
fIN = 19.943MHz, AIN = -0.5dBFS
TA = +105°C
SIGNAL-TO-NOISE AND DISTORTION
vs. TEMPERATURE
TEMPERATURE (°C)
SINAD (dB)
MAX1446 toc20
-40 -15 10 35 60 85 110
50
54
58
62
66
70
fIN = 19.943MHz, AIN = -0.5dBFS
TA = +105°C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 400200 600 800 1000 1200
INTEGRAL NONLINEARITY vs. DIGITAL
OUTPUT CODE (BEST STRAIGHT LINE)
MAX1446 toc21
DIGITAL OUTPUT CODE
INL (LSB)
fIN = 7.5MHz
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 400200 600 800 1000 1200
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1446 toc22
DIGITAL OUTPUT CODE
DNL (LSB)
fIN = 7.5MHz
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (V
REFIN
= 2.048V)
TEMPERATURE (°C)
OFFSET ERROR (%FS)
MAX1446 toc24
-40 -15 10 35 60 85 110
-10
-8
-6
-4
-2
0
2
4
6
8
10
TA = +105°C
27
25
31
29
33
35
2.70 3.002.85 3.15 3.30 3.45 3.60
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1446 toc25
VDD (V)
I
VDD
(mA)
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (V
REFIN
= 2.048V)
TEMPERATURE (°C)
GAIN ERROR (%FS)
MAX1446 toc23
-40 -15 10 35 60 85 110
-10
-8
-6
-4
-2
0
2
4
6
8
10
TA = +105°C
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
I
VDD
(mA)
MAX1446 toc26
-40 -15 10 35 60 85 110
10
14
18
22
26
30
34
38
42
46
50
TA = +105°C
4
3
2
6
5
7
8
1.2 2.41.8 3.0 3.6
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1446 toc27
OVDD (V)
I
OVDD
(mA)
fIN = 7.5MHz
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 2.7V, internal reference, differential input at -0.5dBFS, f
CLK
= 62.35MHz, CL≈ 10pF, TA= +25°C, unless
otherwise noted.)
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
I
OVDD
(mA)
MAX1446 toc28
-40 -15 10 35 60 85 110
0
4
8
12
16
20
fIN = 7.5MHz
TA = +105°C
3.0
2.5
2.0
4.0
3.5
4.5
5.0
2.70 3.002.85 3.15 3.30 3.45 3.60
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
MAX1446 toc29
VDD (V)
I
VDD
(μA)
OE = OVDD,
PD = V
DD
2
0
6
4
8
10
1.2 1.8 2.4 3.0 3.6
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL POWER SUPPLY
MAX1446 toc30
OVDD (V)
I
OVDD
(μA)
PD = VDD,
OE = OV
DD
SNR/SINAD, -THD/SFDR vs. CLOCK FREQUENCY
CLOCK FREQUENCY (MHz)
SNR/SINAD, -THD/SFDR (dB, dBc)
MAX1446 toc31
50 54 58 62 66 70
50
56
62
68
74
80
SINAD
SNR
SFDR
-THD
fIN = 20MHz, AIN = -0.5dBFS
2.02
2.00
2.06
2.04
2.08
2.10
2.70 2.85 3.00 3.15 3.30 3.45 3.60
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1446 toc32
VDD (V)
V
REFOUT
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
V
REFOUT
(V)
MAX1446 toc33
-40 -15 10 35 60 85 110
2.00
2.02
2.04
2.06
2.08
2.10
TA = +105°C
0
20000
40000
60000
80000
100000
120000
140000
160000
N-2 N-1 N N+1 N+2
0926
129421
725 0
OUTPUT NOISE HISTOGRAM (DC INPUT)
MAX1446 toc34
DIGITAL OUTPUT CODE
COUNT
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 REFN
2 COM Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor.
3, 9, 10 V
4, 5, 8, 11, 14, 30 GND Analog Ground
6 IN+ Positive Analog Input. For single-ended operation, connect signal source to IN+.
7 IN- Negative Analog Input. For single-ended operation, connect IN- to COM.
12 CLK Conversion Clock Input
13 PD
15 OE
16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB.
21 OV
22 T.P. Test Point. Do not connect.
23 OGND Output Driver Ground
24–28 D4–D0 Three-State Digital Outputs D4–D0. D0 is the LSB.
29 REFOUT
31 REFIN Reference Input. V
32 REFP
DD
DD
Lower Reference. Conversion range is ±(V
capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel
with 0.1µF.
Power-Down Input
High: power-down mode
Low: normal operation
Output Enable Input
High: digital outputs disabled
Low: digital outputs enabled
Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
= 2 × (V
REFIN
Upper Reference. Conversion range is ±(V
capacitor.
REFP
- V
- V
REFP
). Bypass to GND with a > 0.01µF capacitor.
REFN
REFP
). Bypass to GND with a > 0.1µF
REFN
- V
). Bypass to GND with a > 0.1µF
REFN
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 11
Detailed Description
The MAX1446 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input T/H circuit in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuit samples the
input signal onto the two capacitors (C2a and C2b).
S2a and S2b set the common mode for the amplifier
input. The resulting differential voltage is held on C2a
and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are
then opened before S3a, S3b and S4c are closed, connecting capacitors C1a and C1b to the amplifier output,
and S4c is closed. This charges C1a and C1b to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The
wide-input-bandwidth T/H amplifier allows the
MAX1446 to track and sample/hold analog inputs of
high frequencies beyond Nyquist. The analog inputs
(IN+ and IN-) can be driven either differentially or single
ended. It is recommended to match the impedance of
IN+ and IN- and set the common-mode voltage to midsupply (V
DD
/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1446 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + V
REFIN
/4) and REFN (VDD/2 - V
REFIN
/4). The
ADC’s full-scale range is user adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
Figure 1. Pipelined Architecture—Stage Blocks
Figure 2. Internal T/H Circuit
MDAC
V
IN
T/H
FLASH
ADC
Σ
DAC
V
OUT
x2
IN+
INTERNAL
BIAS
S2a
S4a
C2a
S4c
S1
C1a
COM
S5a
S3a
OUT
1.5 bits
V
IN
V
= INPUT VOLTAGE BETWEEN
IN
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
STAGE 1 STAGE 2
DIGITAL CORRECTION LOGIC
10
D9–D0
STAGE 10
IN-
S4b
TRACK TRACK
HOLD HOLD
C2b
INTERNAL
BIAS
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
OUT
C1b
S3b
S5bS2b
COM
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
12 ______________________________________________________________________________________
The MAX1446 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider if an application
requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a
> 10nF capacitor to GND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a > 10kΩ resistor.
In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance and
can be driven by external reference sources.
Clock Input (CLK)
The MAX1446 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the ADC as follows:
where fINrepresents the analog input frequency, and
tAJis the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
The MAX1446 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the
Electrical Character-
istics
. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) vs.
duty cycle.
Output Enable (OE), Power-Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD (power-down) high, the digital output enters a high-impedance state. If OE is held
low with PD high, the outputs are latched at the last
value prior to the power-down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (< 15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1446, degrading its dynamic performance. The use of buffers on the ADC’s digital
outputs can further isolate the digital outputs from
heavy capacitive loads.
To further improve the dynamic performance of the
MAX1446 small series resistors (e.g., 100Ω) may be
added to the digital output paths, close to the ADC.
Figure 5 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid.
System Timing Requirements
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1446
Table 1. MAX1446 Output Code for Differential Inputs
*V
REFIN
= V
REFP
= V
REFN
SNR
20
log
=×
⎛
⎜
⎝
1
2
π
ft
×× ×
IN AJ
⎞
⎟
⎠
DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY
V
× 511/512 +Full Scale -1LSB 11 1111 1111
REF
V
× 510/512 +Full Scale -2LSB 11 1111 1110
REF
V
× 1/512 +1LSB 10 0000 0001
REF
0 Bipolar Zero 10 0000 0000
- V
× 1/512 -1LSB 01 1111 1111
REF
- V
× 511/512 Negative Full Scale + 1LSB 00 0000 0001
REF
- V
× 512/512 Negative Full Scale 00 0000 0000
REF
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 13
Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input)
Figure 3b. SNR vs. Clock Duty Cycle (Differential Input)
Figure 4a. THD vs. Clock Duty Cycle (Differential Input)
Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input)
Figure 5. Output Enable Timing
80
fIN = 12.5MHz AT -0.5dBFS
70
60
SFDR (dBc)
50
40
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
70
fIN = 12.5MHz AT -0.5dBFS
65
60
55
SNR (dB)
50
-40
fIN = 12.5MHz AT -0.5dBFS
-50
-60
THD (dBc)
-70
-80
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
70
fIN = 12.5MHz AT -0.5dBFS
65
60
55
SINAD (dB)
50
45
40
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
OE
t
ENABLE
OUTPUT
DATA D9–D0
45
40
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
t
DISABLE
VALID DATA
HIGH-ZHIGH-Z
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
14 ______________________________________________________________________________________
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting
purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
R
ISO
and CINvalues to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an R
ISO
of 50Ω is placed before the capaci-
tive load to prevent ringing and oscillation. The 22pF
CINcapacitor acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1446 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the overall distortion.
In general, the MAX1446 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Single-Ended AC-Coupled
Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1446 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source. A precision
bandgap reference like the MAX6062 generates an
external DC level of 2.048V (Figure 10), and exhibits a
noise voltage density of 150n√Hz. Its output passes
through a 1-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference
before its output is applied to a second 10Hz lowpass
Figure 6. System and Output Timing Diagram
5.5 CLOCK-CYCLE LATENCY
N
ANALOG INPUT
CLOCK INPUT
t
DO
DATA OUTPUT
N - 6
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N + 5
N - 1
N
N + 6
N + 1
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 15
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
Figure 8. Using a Transformer for AC-Coupling
Figure 9. Single-Ended AC-Coupled Input
INPUT
MAX4108
300Ω
5V
-5V
300Ω
0.1μF
0.1μF
300Ω
300Ω
300Ω
300Ω
600Ω
600Ω
0.1μF
0.1μF
5V
MAX4108
-5V
5V
MAX4108
-5V
600Ω
0.1μF
0.1μF
0.1μF
0.1μF
600Ω
LOWPASS FILTER
R
ISO
50Ω
LOWPASS FILTER
R
ISO
50Ω
C
22pF
C
22pF
IN+
IN
MAX1446
COM
IN-
IN
25Ω
IN+
22pF
0.1μF
V
IN
N.C.
4
3
T1
2
5
2.2μF
61
0.1μF
MAX1446
COM
V
IN
MAX4108
MINI-CIRCUITS
ADT1–1WT
25Ω
R
IN-
22pF
= 50Ω
ISO
= 22pF
C
IN
REFP
1kΩ
0.1μF
100Ω
100Ω
REFN
1kΩ
R
ISO
0.1μF
IN+
C
IN
MAX1446
COM
R
ISO
IN-
C
IN
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
16 ______________________________________________________________________________________
filter. The MAX4250 provides a low offset voltage (for
high-gain accuracy) and a low noise level. The passive
10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This
filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision
ADC operation.
Unbuffered External Reference Drives
Multiple ADCs
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider (Figure 11), the
MAX6066 generates a DC level of 2.500V. The buffered
outputs of this divider are set to 2.0V, 1.5V, and 1.0V,
with an accuracy that depends on the tolerance of the
divider resistors. The three voltages are buffered by the
MAX4252, which provides low noise and low DC offset.
The individual voltage followers are connected to 10Hz
lowpass filters, which filter both the reference voltage
and amplifier noise to a level of 3n√Hz. The 2.0V and
1.0V reference voltages set the differential full-scale
range of the associated ADCs at 2V
P-P
. The 2.0V and
1.0V buffers drive the ADC’s internal ladder resistances
between them. Note that the common power supply for
all active components removes any concern regarding
power-supply sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters can
be replicated to support as many as 32 ADCs. For
applications that require more than 32 matched ADCs,
a voltage reference and divider string common to all
converters is highly recommended.
Figure 10. Buffered External Reference Drives Up to 1000 ADCs
3.3V
1
MAX6062
3
0.1μF
0.1μF
16.2kΩ
2
1μF
10Hz LOWPASS
FILTER 10Hz LOWPASS
3
MAX4250
4
5
3.3V
2.048V
0.1μF
162Ω
1
100μF2
FILTER
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
N.C.
N.C.
0.1μF
0.1μF
29
31
32
29
31
32
1
2
1
2
REFOUT
REFIN
REFP
REFN
COM
REFOUT
REFIN
REFP
REFN
COM
MAX1446
N = 1
MAX1446
N = 1000
0.1μF
2.2μF
10V
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 17
Grounding, Bypassing,
__________________and Board Layout
The MAX1446 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground
planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
Figure 11. Unbuffered External Reference Drives Up to 32 ADCs
3.3V
0.1μF
1
21.5kΩ
2
MAX6066
3
3.3V
0.1μF
MAX4254 POWER-SUPPLY BYPASSING.
PLACE CAPACITOR AS CLOSE AS
POSSIBLE TO THE OP AMP.
1μF
21.5kΩ
21.5kΩ
21.5kΩ
21.5kΩ
2.0V
1.5V
1.0V
3
1/4 MAX4252
2
5
1/4 MAX4252
6
10
1/4 MAX4252
9
N.C.
29
REFOUT
31
REFIN
0.1μF
0.1μF
32
REFP
MAX1446
REFN
COM
REFOUT
REFIN
REFP
REFN
COM
N = 1
MAX1446
N = 32
0.1μF
2.2μF
10V
1
2
29
31
32
1
2
3.3V
4
11
4
11
4
11
2.0V AT 8mA
47Ω
1
10μF
6V
7
10μF
6V
8
1.47kΩ
3.3V
1.5V AT 0mA
47Ω
1.47kΩ
3.3V
1.0V AT -8mA
47Ω
10μF
6V
1.47kΩ
330μF
6V
330μF
330μF
0.1μF
0.1μF
6V
N.C.
6V
0.1μF
0.1μF
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
Figure 12. T/H Aperture Timing
MAX1446
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1446’s static linearity parameters are measured
using the best-straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 12 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 12).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (rms value) to the rms quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR
(MAX)
= 6.02 x N + 1.76
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics,
and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the rms signal
to all spectral components minus the fundamental and
the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
Total Harmonic Distortion (THD)
THD is typically the ratio of the rms sum of the input
signal’s first four harmonics to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the rms
amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale.
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
18 ______________________________________________________________________________________
ENOB
=
SINAD
−(.)
176
.
602
THD
⎛
2222
VVVV
+++
=×
20
log
2345
⎜
⎜
⎝
V
1
⎞
⎟
⎟
⎠
CLK
ANALOG
INPUT
t
AD
SAMPLED
DATA (T/H)
TRACK TRACK
T/H
t
AJ
HOLD
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 19
Pin Configurations (continued)
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
32 TQFP H32-2F
21-0110
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
TOP VIEW
COM
V
DD
GND
GND
IN+
IN-
REFP
32 28
1REFN
2
3
4
5
6
7
8GND
9
DD
V
10
REFIN
DD
V
GND
REFOUT
293031
MAX1446
CLK
GND
TQFP
D0
D1
D2
D3
GND
25
26
24 D4
OGND
23
T.P.
22
OV
21
DD
D5
20
D6
19
D7
18
D8
17
15
1611 12
OE
D9
27
14
13
PD
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
3 11/07
4 11/08 Updates to the Electrical Characteristics table and notes section. 5, 14
REVISION
DATE
DESCRIPTION
Various corrections; updated to extended temperature range for automotive
applications; replaced TOCs 9–20, 23, 24, 26, 30, 31, 33; updated package
outlines.
PAGES
CHANGED
1–9, 15, 18, 20, 21
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