MAXIM MAX1438 Technical data

General Description

The MAX1438 octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1438 operates from a 1.8V single
supply and consumes only 913mW (114mW per chan­nel) while delivering a 69.9dB (typ) signal-to-noise ratio
(SNR) at a 5.3MHz input frequency. In addition to low
operating power, the MAX1438 features a power-down
mode for idle periods.

An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc­ture allows the use of an external reference for applica­tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.

A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip PLL
generates the high-speed serial low-voltage differential
signal (LVDS) clock.

The MAX1438 has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s complement or binary format.

The MAX1438 offers a maximum sample rate of
65Msps. See the

Pin-Compatible Versions

table below
for lower-speed versions. This device is available in a
small, 14mm x 14mm x 1mm, 100-pin TQFP package
with exposed pad and is specified for the extended
industrial (-40°C to +85°C) temperature range.

Applications

Ultrasound and Medical Imaging

Instrumentation

Multichannel Communications

Features

o Excellent Dynamic Performance

69.9dB SNR at 5.3MHz
95dBc SFDR at 5.3MHz
85dB Channel Isolation

o Ultra-Low Power

114mW per Channel (Normal Operation)

o Serial LVDS Outputs

o Pin-Selectable LVDS/SLVS (Scalable Low-Voltage

Signal) Mode

o LVDS Outputs Support Up to 30 Inches FR-4

Backplane Connections

o Test Mode for Digital Signal Integrity

o Fully Differential Analog Inputs

o Wide Differential Input Voltage Range (1.4V

P-P

)

o On-Chip 1.24V Precision Bandgap Reference

o Clock Duty-Cycle Equalizer

o Compact, 100-Pin TQFP Package with Exposed

Pad

o Evaluation Kit Available (Order MAX1438EVKIT)

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC

with Serial LVDS Outputs

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

19-0359; Rev 1; 2/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

EVALUATION KIT

AVAILABLE

Pin-Compatible Versions

+

Denotes a lead(Pb)-free/RoHS-compliant package.

D = Dry pack.

*

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX1438ECQ+D -40°C to +85°C

100 TQFP-EP*
(14mm x 14mm x 1mm)

PART

MAX1434 50 10

MAX1436 40 12

MAX1437 50 12

MAX1438 65 12

SAMPLING RATE

(Msps)

RESOLUTION

(BITS)

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC
with Serial LVDS Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

(Voltages referenced to GND)

AVDD.....................................................................-0.3V to +2.0V

CVDD.....................................................................-0.3V to +3.6V

OVDD ....................................................................-0.3V to +2.0V

IN_P, IN_N ..............................................-0.3V to (V

AVDD

+ 0.3V)

CLK ........................................................-0.3V to (V

CVDD

+ 0.3V)

OUT_P, OUT_N, FRAME_, CLKOUT_ ....-0.3V to (V

OVDD

+ 0.3V)

DT, SLVS/LVDS, LVDSTEST, PLL_, T/B,

REFIO, REFADJ, CMOUT...................-0.3V to (V

AVDD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

TQFP (derate 47.6mW/°C above +70°C)................3809.5mW

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

ELECTRICAL CHARACTERISTICS

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF,

f

CLK

= 65MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

PACKAGE THERMAL CHARACTERISTICS (Note 1)

TQFP

Junction-to-Ambient Thermal Resistance (θ

JA

) ...........21°C/W

Junction-to-Case Thermal Resistance (θ

JC

) ..................2°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 4)

Resolution N 12 Bits

Integral Nonlinearity INL ±0.4 ±2.5 LSB

Differential Nonlinearity DNL No missing codes over temperature ±0.25 ±1 LSB

Offset Error ±0.5 %FS

Gain Error -3.5 +2.0 %FS

ANALOG INPUTS (IN_P, IN_N)

Input Differential Range V

Common-Mode Voltage Range V

Common-Mode Voltage Range
Tolerance

Differential Input Impedance R

Differential Input Capacitance C

CONVERSION RATE

Maximum Conversion Rate f

Minimum Conversion Rate f

Data Latency 6.5 Cycles

DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 4)

Signal-to-Noise Ratio SNR

Signal-to-Noise and Distortion
(First 4 Harmonics)

ID

CMO

IN

IN

SMAX

SMIN

SINAD

Differential input 1.4 V

(Note 5) ±50 mV

Switched capacitor load 2 kΩ

fIN = 5.3MHz at -0.5dBFS 69.9

f

= 19.3MHz at -0.5dBFS 66.5 69.6

IN

fIN = 5.3MHz at -0.5dBFS 69.8

= 19.3MHz at -0.5dBFS 66.5 69.6

f

IN

0.76 V

12.5 pF

65 MHz

4.0 MHz

P-P

dB

dB

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF,

f

CLK

= 65MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Effective Number of Bits ENOB

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Intermodulation Distortion IMD

Third-Order Intermodulation IM3

Aperture Jitter t

Aperture Delay t

Small-Signal Bandwidth SSBW Input at -20dBFS 100 MHz

Full-Power Bandwidth LSBW Input at -0.5dBFS 100 MHz

Output Noise IN_P = IN_N 0.44 LSB

Over-Range Recovery Time t

INTERNAL REFERENCE

REFADJ Internal Reference-Mode
Enable Voltage

REFADJ Low-Leakage Current 1.5 mA

REFIO Output Voltage V

Reference Temperature
Coefficient

EXTERNAL REFERENCE

REFADJ External Reference­Mode Enable Voltage

REFADJ High-Leakage Current 200 µA

REFIO Input Voltage 1.24 V

REFIO Input Voltage Tolerance ±5 %

REFIO Input Current I

COMMON-MODE OUTPUT (CMOUT)

CMOUT Output Voltage V

CLOCK INPUT (CLK)

Input High Voltage V

Input Low Voltage V

Clock Duty Cycle 50 %

Clock Duty-Cycle Tolerance ±30 %

AJ

AD

OR

REFIO

TC

REFIO

REFIO

CMOUT

CLKH

CLKL

fIN = 5.3MHz at -0.5dBFS 11.4

f

= 19.3MHz at -0.5dBFS 11.4

IN

fIN = 5.3MHz at -0.5dBFS 95

f

= 19.3MHz at -0.5dBFS 79 93

IN

fIN = 5.3MHz at -0.5dBFS -98

= 19.3MHz at -0.5dBFS -92 -79

f

IN

f

= 5.3MHz at -6.5dBFS

1

f

= 6.3MHz at -6.5dBFS

2

f

= 5.3MHz at -6.5dBFS

1

f

= 6.3MHz at -6.5dBFS

2

Figure 11 < 0.4 ps

Figure 11 1 ns

RS = 25Ω, CS = 50pF 1

(Note 6) 0.1 V

(Note 6)

1.18 1.24 1.30 V

V

-

AVDD

0.1

0.8 x

V

AVDD

89.3 dBc

97.5 dBc

120 ppm/°C

< 1 µA

0.76 V

0.2 x

V

AVDD

Clock

cycle

dB

dBc

dBc

RMS

RMS

V

V

V

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC
with Serial LVDS Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF,

f

CLK

= 65MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage Current DI

Input Capacitance DC

DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, PD, T/B)

Input Logic-High Voltage V

Input Logic-Low Voltage V

Input Leakage Current DI

Input Capacitance DC

LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0

Differential Output Voltage V

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1

Differential Output Voltage V

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

POWER-DOWN

PD Fall to Output Enable t

PD Rise to Output Disable t

POWER REQUIREMENTS

AVDD Supply Voltage Range V

OVDD Supply Voltage Range V

CVDD Supply Voltage Range V

AVDD Supply Current I

OVDD Supply Current I

CVDD Supply Current I

Power Dissipation P

OHDIFFRTERM

OCMRTERM

RL

FL

OHDIFFRTERM

OCMRTERM

RS

FS

ENABLE

DISABLE

AVDD

OVDD

CVDD

AVDD

OVDD

CVDD

DISSfIN

Input at GND 5

IN

Input at AVDD 80

IN

IH

IL

Input at GND 5

IN

Input at AVDD 80

IN

0.8 x

V

AVDD

= 100Ω 250 450 mV
= 100Ω 1.125 1.375 V

R

TERM

R

TERM

= 100Ω, C
= 100Ω, C

= 5pF 350 ps

LOAD

= 5pF 350 ps

LOAD

= 100Ω 205 mV
= 100Ω 220 mV

R

TERM

R

TERM

= 100Ω, C
= 100Ω, C

= 5pF 320 ps

LOAD

= 5pF 320 ps

LOAD

(Note 7) 100 ms

P D = 0 422 465

fIN = 19.3MHz
at -0.5dBFS

P D = 0, D T = 1 422

P D = 1, p ower - dow n,
no cl ock i np ut

P D = 0 85 110

fIN = 19.3MHz
at -0.5dBFS

P D = 0, D T = 185

P D = 1, p ower - dow n,
no cl ock i np ut

CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2

= 19.3MHz at -0.5dBFS 913 1035 mW

5pF

0.2 x

V

AVDD

5pF

20 ns

1.7 1.8 1.9 V

1.7 1.8 1.9 V

1.7 1.8 3.6 V

mA

1.16 mA

mA

960 µA

0mA

µA

V

V

µA

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, external V

REFIO

= 1.24V, C

REFIO

= 0.1µF, C

REFP

= 10µF, C

REFN

= 10µF,

f

CLK

= 65MHz (50% duty cycle), VDT= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 2, 3)

Note 2: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design

and characterization and not subject to production testing.

Note 3: All capacitances are between the indicated pin and GND, unless otherwise noted.
Note 4: See definition in the

Parameter Definitions

section at the end of this data sheet.

Note 5: See the

Common-Mode Output (CMOUT)

section.

Note 6: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the inter-

nal bandgap reference and enable external reference mode.

Note 7: Measured using C

REFP

to GND = 1µF and C

REFN

to GND = 1µF. t

ENABLE

time may be lowered by using smaller capacitor values.

Note 8: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 9: Guaranteed by design and characterization. Not subject to production testing.

Typical Operating Characteristics

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f

CLK

= 65MHz

(50% duty cycle), V

DT

= 0V, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

FFT PLOT

(16,384-POINT DATA RECORD)

MAX1438 toc01

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110
0 5 10 15 20 25 30

f

CLK

= 65.4966636MHz

f

IN

= 5.304814MHz

A

IN

= -0.5dBFS
SNR = 70.120dB
SINAD = 70.112dB
THD = -97.686dBc
SFDR = 95.406dBc

HD2

HD3

FFT PLOT

(16,384-POINT DATA RECORD)

MAX1438 toc02

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110

f

CLK

= 65.4966637MHz

f

IN

= 30.313794MHz

A

IN

= -0.5dBFS
SNR = 69.584dB
SINAD = 69.516dB
THD = -97.316dBc
SFDR = 94.713dBc

HD2

HD3

0 5 10 15 20 25 30

CROSSTALK

(16,384-POINT DATA RECORD)

MAX1438 toc03

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-110

-90

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
f

IN(IN1)

= 5.304814MHz

f

IN(IN2)

= 30.3189139MHz

CROSSTALK = 85.4dB

f

IN(IN2)

0 5 10 15 20 25 30

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TIMING CHARACTERISTICS (Note 8)

Data Valid to CLKOUT Rise/Fall t

CLKOUT Output-Width High t

CLKOUT Output-Width Low t

FRAME Rise to CLKOUT Rise t

Sample CLK Rise to FRAME Rise t

Crosstalk (Note 4) -85 dB

Gain Matching C

Phase Matching C

OD

CH

CL

CF

SF

GMfIN

PMfIN

Figure 5 (Note 9)

Figure 5 t

Figure 5 t

Figure 4 (Note 9)

Figure 4 (Note 9)

( t

S AM P LE

- 0.15

( t

S AM P LE

- 0.15

( t

S AM P LE

+ 1.1

/24)

( t

S AM P LE

/12 ns

S AM P LE

/12 ns

S AM P LE

/24)

( t

S AM P LE

/2)

( t

S AM P LE

+ 0.15

+ 0.15

+ 2.6

/24)

/24)

/2)

ns

ns

ns

= 5.3MHz (Note 4) ±0.1 dB

= 5.3MHz (Note 4) ±0.25 D eg r ees

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC
with Serial LVDS Outputs

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f

CLK

= 65MHz

(50% duty cycle), V

DT

= 0V, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

MAX1438 toc04

FREQUENCY (MHz)

AMPLITUDE (dBFS)

0

-10

-20

-30

-40

-50

-70

-60

-80

-100

-90

-110

TWO-TONE INTERMODULATION DISTORTION

(16,384-POINT DATA RECORD)

f

IN(IN1)

= 5.296593MHz

f

IN(IN2)

= 6.299991MHz

A

IN1

= -6.5dBFS

A

IN2

= -6.5dBFS
IMD = 89.3dBc
IM3 = 97.5dBc

0 5 10 15 20 25 30

1

-1

-10
1 100 1000

-6

-7

-8

-9

-5

-4

-3

-2

MAX1438 toc05

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

10

BANDWIDTH

vs. ANALOG INPUT FREQUENCY

0

FULL-POWER
BANDWIDTH

-0.5dBFS

SMALL-SIGNAL
BANDWIDTH

-20.5dBFS

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

f

(MHz)

SNR (dB)

1008020 40 60

72

71

70

69

68

67

66

MAX1438 toc06

73

65

0120

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

SINAD (dB)

1008020 40 60

72

71

70

69

68

67

66

MAX1438 toc07

73

65

0120

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

THD (dBc)

1008020 40 60

-95

-90

-85

-75

-70

-80

-65

-60

MAX1438 toc08

-55

-100
0120

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

fIN (MHz)

SFDR (dBc)

1008020 40 60

60

65

70

80

85

75

90

95

MAX1438 toc09

100

55

0120

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

SNR (dB)

-5-10-25 -20 -15

37

42

52

57

47

62

67

72

32

-30 0

MAX1438 toc10

fIN = 5.304814MHz

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

SINAD (dB)

-5-10-25 -20 -15

37

42

52

57

47

62

MAX1438 toc11

67

72

32

-30 0

fIN = 5.304814MHz

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT POWER

ANALOG INPUT POWER (dBFS)

THD (dBc)

-5-10-25 -20 -15

-85

-90

-80

-70

-65

-75

-60

-55

-50

-100

-95

-30 0

MAX1438 toc12

fIN = 5.304814MHz

MAX1438

Octal, 12-Bit, 65Msps, 1.8V ADC

with Serial LVDS Outputs

_______________________________________________________________________________________

7

)

)

)

Typical Operating Characteristics (continued)

(V

AVDD

= 1.8V, V

OVDD

= 1.8V, V

CVDD

= 3.3V, V

GND

= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f

CLK

= 65MHz

(50% duty cycle), V

DT

= 0V, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT POWER

95

fIN = 5.304814MHz

90

85

80

75

70

SFDR (dBc)

65

60

55

50

45

-30 0
ANALOG INPUT POWER (dBFS

TOTAL HARMONIC DISTORTION

vs. SAMPLING RATE

-75
fIN = 5.304814MHz

-80

-85

-90

THD (dBc)

-95

-100

-105
10 20 25 3015 35 40 5550 6045 65

f

(MHz)

CLK

SIGNAL-TO-NOISE PLUS DISTORTION

vs. DUTY CYCLE

73

fIN = 5.304814MHz

72

71

70

69

SINAD (dB)

68

67

66

65

30 70

DUTY CYCLE (%)

MAX1438 toc13

-5-10-25 -20 -15

MAX1438 toc16

MAX1438 toc19

60 655540 4535 50

SIGNAL-TO-NOISE RATIO

vs. SAMPLING RATE

73

fIN = 5.304814MHz

72

71

70

69

SNR (dB)

68

67

66

65

10 20 25 3015 35 40 5550 6045 65

f

SPURIOUS-FREE DYNAMIC RANGE

vs. SAMPLING RATE

105

fIN = 5.304814MHz

100

95

90

SFDR (dBc)

85

80

75

10 20 25 3015 35 40 5550 6045 65

f

CLK

TOTAL HARMONIC DISTORTION

vs. DUTY CYCLE

-75
fIN = 5.304814MHz

-80

-85

-90

THD (dBc)

-95

-100

-105
30 70

DUTY CYCLE (%)

(MHz

(MHz)

SIGNAL-TO-NOISE PLUS DISTORTION

vs. SAMPLING RATE

73

fIN = 5.304814MHz

72

MAX1438 toc14

71

70

69

SINAD (dB)

68

67

66

65

10 20 25 3015 35 40 5550 6045 65

f

(MHz

SIGNAL-TO-NOISE RATIO

vs. DUTY CYCLE

73

fIN = 5.304814MHz

72

MAX1438 toc17

71

70

69

SNR (dB)

68

67

66

65

30 70

DUTY CYCLE (%)

60 655540 4535 50

SPURIOUS-FREE DYNAMIC RANGE

vs. DUTY CYCLE

100

fIN = 5.304814MHz

95

MAX1438 toc20

90

85

SFDR (dBc)

80

75

70

60 655540 4535 50

30 70

DUTY CYCLE (%)

60 655540 4535 50

MAX1438 toc15

MAX1438 toc18

MAX1438 toc21