The MAX1437B octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1437B operates from a 1.8V single supply and consumes only 768mW (96mW per
channel) while delivering a 70.2dB (typ) signal-to-noise
ratio (SNR) at a 5.3MHz input frequency. In addition to
low operating power, the MAX1437B features a lowpower standby mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip
phase-locked loop (PLL) generates the high-speed serial low-voltage differential signal (LVDS) clock.
The MAX1437B has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s complement format.
The MAX1437B offers a maximum sample rate of
50Msps. This device is available in a small, 10mm x
10mm x 0.8mm, 68-pin TQFN package with exposed
pad and is specified for the extended industrial (-40°C
to +85°C) temperature range.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
Features
o Excellent Dynamic Performance
70.2dB SNR at 5.3MHz
98dBc SFDR at 5.3MHz
82dB Channel Isolation at 5.3MHz
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to GND)
AVDD.....................................................................-0.3V to +2.0V
CVDD.....................................................................-0.3V to +3.6V
OVDD ....................................................................-0.3V to +2.0V
IN_P, IN_N ..............................................-0.3V to (V
AVDD
+ 0.3V)
CLK ........................................................-0.3V to (V
CVDD
+ 0.3V)
OUT_P, OUT_N, FRAME_, CLKOUT_ ......-0.3V to (V
OVDD
+ 0.3V)
DT, SLVS/LVDS, LVDSTEST, PLL_,
REFIO, REFADJ, CMOUT...................-0.3V to (V
, unless otherwise noted. Typical values are at TA= +25°C.)
(Notes 2, 3)
Note 2: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 3: All capacitances are between the indicated pin and GND, unless otherwise noted.
Note 4: See the
Common-Mode Output (CMOUT)
section.
Note 5: See definition in the
Parameter Definitions
section at the end of this data sheet.
Note 6: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal
bandgap reference and enable external reference mode.
Note 7: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 8: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f
9, 18, 68GNDGround. Connect all GND pins to the same potential.
12IN4PChannel 4 Positive Input
13IN4NChannel 4 Negative Input
14IN5PChannel 5 Positive Input
15IN5NChannel 5 Negative Input
16IN6PChannel 6 Positive Input
17IN6NChannel 6 Negative Input
19IN7PChannel 7 Positive Input
20IN7NChannel 7 Negative Input
21DT
22SLVS/LVDS
23CVDD
24CLKSingle-Ended CMOS Clock Input
28, 31, 34, 39,
44, 49, 52
29OUT7NChannel 7 Negative LVDS/SLVS Output
30OUT7PChannel 7 Positive LVDS/SLVS Output
32OUT6NChannel 6 Negative LVDS/SLVS Output
33OUT6PChannel 6 Positive LVDS/SLVS Output
35OUT5NChannel 5 Negative LVDS/SLVS Output
36OUT5PChannel 5 Positive LVDS/SLVS Output
37OUT4NChannel 4 Negative LVDS/SLVS Output
38OUT4PChannel 4 Positive LVDS/SLVS Output
40FRAMEN
41FRAMEP
42CLKOUTNNegative LVDS/SLVS Serial Clock Output
AVDD
OVDD
Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass AVDD to GND with a
0.1µF capacitor as close as possible to the device. Bypass the AVDD power plane to the GND plane
with a bulk capacitor of at least 2.2µF. Connect all AVDD pins to the same potential.
Double Termination Select. Force DT high to select the internal 100Ω termination between the
differential output pairs. Force DT low to select no internal output termination.
Differential Output Signal Format Select Input. Force SLVS/LVDS high to select SLVS outputs. Force
SLVS/LVDS low to select LVDS outputs.
Clock Power Input. Connect CVDD to a 1.7V to 3.5V power supply. Bypass CVDD to GND with a
0.1µF capacitor in parallel with a capacitor of at least 2.2µF. Install the bypass capacitors as close
as possible to the device.
Output Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass OVDD to GND
with a 0.1µF capacitor as close as possible to the device. Bypass the OVDD power plane to the
GND plane with a bulk capacitor of at least 2.2µF. Connect all OVDD pins to the same potential.
Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.
Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.
LVDS Test Pattern Enable. Force LVDSTEST high to enable the output test pattern, 0000 1011 1101.
55LVDSTEST
56STBY
57PLL3PLL Control Input 3. See Table 1 for details.
58PLL2PLL Control Input 2. See Table 1 for details.
59PLL1PLL Control Input 1. See Table 1 for details.
61REFN
62REFP
63REFIO
64REFADJ
65CMOUT
66IN0PChannel 0 Positive Input
67IN0NChannel 0 Negative Input
—EP
As with the analog conversion results, the test pattern data are output LSB first. Force LVDSTEST
low for normal operation.
Standby Input. Force STBY high to put the MAX1437B into standby mode. In standby, the reference
circuitry remains active. Force STBY low for normal operation.
Negative Reference Bypass Output. Connect a capacitor of at least 1µF (10µF typ) between REFP
and REFN, and connect a capacitor of at least 1µF (10µF typ) between REFN and GND. Place the
capacitors as close as possible to the device on the same side of the PCB as the MAX1437B.
Positive Reference Bypass Output. Connect a capacitor of at least 1µF (10µF typ) between REFP
and REFN, and connect a capacitor of at least 1µF (10µF typical) between REFN and GND. Place
the capacitors as close as possible to the device on the same side of the PCB as the MAX1437B.
Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output
voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable reference
voltage at REFIO. Bypass to GND with a capacitor of at least 0.1µF.
Internal/External Reference Mode Select and Reference Adjust Input. For internal reference, connect
REFADJ to GND. For external reference, connect REFADJ to AVDD. For adjusting the reference, see
the Full-Scale Range Adjustments Using the Internal Reference section.
Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage for DCcoupled applications. Bypass CMOUT to GND with a capacitor of at least 0.1µF.
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane for maximum
thermal performance. Must be connected to GND.
MAX1437B
Detailed Description
The MAX1437B ADC features fully differential inputs, a
pipelined architecture, and digital error correction for
high-speed signal conversion. The ADC pipeline architecture moves the samples taken at the inputs through
the pipeline stages every half clock cycle. The converted digital results are serialized and sent through the
LVDS/SLVS output drivers. The total clock-cycle latency
from input to output is 6.5 clock cycles.
The MAX1437B offers 8 separate fully differential channels with synchronized inputs and outputs. Global
standby minimizes power consumption.
Input Circuit
Figure 1 displays a simplified diagram of the input T/H
circuits. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the operational transconductance amplifier (OTA), and open simultaneously with S1,
sampling the input waveform. Switches S4a, S4b, S5a,
and S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The
amplifiers charge capacitors C1a and C1b to the same
values originally held on C2a and C2b. These values are
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED).
PLL3PLL1PLL2
GND
then presented to the first-stage quantizers and isolate
the pipelines from the fast-changing inputs. Analog
inputs, IN_P to IN_N, are driven differentially. For differential inputs, balance the input impedance of IN_P and
IN_N for optimum performance.
Reference Configurations (REFIO,
REFADJ, REFP, and REFN)
The MAX1437B provides an internal 1.24V bandgap
reference or can be driven with an external reference
voltage. The full-scale analog differential input range is
±FSR. FSR (full-scale range) is given by the following
equation:
where V
REFIO
is the voltage at REFIO, generated inter-
nally or externally. For a V
REFIO
= 1.24V, the full-scale
input range is ±700mV (1.4V
P-P
).
Internal Reference Mode
Connect REFADJ to GND to use the internal bandgap
reference directly. The internal bandgap reference generates V
REFIO
to be 1.24V with a 120ppm/°C temperature coefficient in internal reference mode. Connect an
external ≥ 0.1µF bypass capacitor from REFIO to GND
for stability. REFIO sources up to 200µA and sinks up to
200µA for external circuits, and REFIO has a 75mV/mA
load regulation. Putting the MAX1437B into standby
mode turns off all circuitry except the reference circuit,
allowing the converter to power up faster when the ADC
exits standby with a high-to-low transitional signal on
STBY. The internal circuits of the MAX1437B require
200µs to power up and settle when the converter exits
standby mode.
To compensate for gain errors or to decrease or
increase the ADC’s FSR, add an external resistor
between REFADJ and GND or REFADJ and REFIO.
This adjusts the internal reference value of the
MAX1437B by up to ±5% of its nominal value. See the
Full-Scale Range Adjustments Using the Internal
Reference
Connect ≥1µF (10µF typ) capacitors to GND from REFP
and REFN and a ≥1µF (10µF typ) capacitor between
REFP and REFN as close to the device as possible on
the same side of the PCB.
External Reference Mode
The external reference mode allows for more control
over the MAX1437B reference voltage and allows multiple converters to use a common reference. Connect
REFADJ to AVDD to disable the internal reference.
Apply a stable 1.18V to 1.30V source at REFIO. Bypass
REFIO to GND with a ≥ 0.1µF capacitor. The REFIO
input impedance is >1MΩ.
Clock Input (CLK)
The MAX1437B accepts a CMOS-compatible clock signal with a wide 20% to 80% input clock duty cycle.
Drive CLK with an external single-ended clock signal.
Figure 2 shows the simplified clock input diagram.
Low clock jitter is required for the specified SNR performance of the MAX1437B. Analog input sampling
occurs on the rising edge of CLK, requiring this edge to
provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the
following relationship:
where fINrepresents the analog input frequency and t
J
is the total system clock jitter.
PLL Inputs (PLL1, PLL2, PLL3)
The MAX1437B features a PLL that generates an output
clock signal with six times the frequency of the input
clock. The output clock signal is used to clock data out
of the MAX1437B (see the
System Timing Requirements
section). Set the PLL1, PLL2, and PLL3 pins according
to the input clock range provided in Table 1.
System Timing Requirements
Figure 3 shows the relationship between the analog
inputs, input clock, frame-alignment output, serial-clock
output, and serial-data output. The differential analog
input (IN_P and IN_N) is sampled on the rising edge of
the CLK signal and the resulting data appears at the
digital outputs 6.5 clock cycles later. Figure 4 provides
a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs.
Clock Output (CLKOUTP, CLKOUTN)
The MAX1437B provides a differential clock output that
consists of CLKOUTP and CLKOUTN. As shown in Figure
4, the serial output data is clocked out of the MAX1437B
on both edges of the clock output. The frequency of the
output clock is six times the frequency of CLK.
Frame-Alignment Output (FRAMEP, FRAMEN)
The MAX1437B provides a differential frame-alignment
signal that consists of FRAMEP and FRAMEN. As
shown in Figure 4, the rising edge of the frame-alignment signal corresponds to the first bit (D0) of the 12bit serial data stream. The frequency of the framealignment signal is identical to the frequency of the
input clock.
Serial Output Data (OUT_P, OUT_N)
The MAX1437B provides its conversion results through
individual differential outputs consisting of OUT_P and
OUT_N. The results are valid 6.5 input clock cycles
after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output
clock, LSB (D0) first. Figure 5 provides the detailed serial-output timing diagram.
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
The MAX1437B output data format is two’s complement. The following equation, Table 2, and Figure 6
define the relationship between the digital output and
the analog input:
where CODE10is the decimal equivalent of the digital
output code as shown in Table 2.
Keep the capacitive load on the MAX1437B digital outputs as low as possible.
LVDS and SLVS Selection (SLVS/
LVDS
)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high
for SLVS levels at the MAX1437B outputs (OUT_P,
OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN).
For SLVS levels, enable double-termination by driving DT
high. See the
Electrical Characteristics
table for LVDS
and SLVS output voltage levels.
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0000 1011 1101. Drive LVDSTEST low for normal operation (test pattern disabled).
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DCcoupled analog inputs. If the input is DC-coupled,
match the output common-mode voltage of the circuit
driving the MAX1437B to the output voltage at V
CMOUT
to within ±50mV. It is recommended that the output
common-mode voltage of the driving circuit be derived
from CMOUT.
Double Termination (DT)
The MAX1437B offers an optional, internal 100Ω termi-
nation between the differential output pairs (OUT_P and
OUT_N, CLKOUTP and CLKOUTN, FRAMEP and
FRAMEN). In addition to the termination at the end of
the line, a second termination directly at the outputs
helps eliminate unwanted reflections down the line. This
feature is useful in applications where trace lengths are
long (> 5in) or with mismatched impedance. Drive DT
high to select double-termination, or drive DT low to
disconnect the internal termination resistor (single-termination). Selecting double-termination increases the
OVDD supply current (see Figure 7).
Standby Mode
The MAX1437B offers a standby mode to efficiently use
power by transitioning to a low-power state when conversions are not required. STBY controls the standby
mode of all channels and the internal reference circuitry.
The reference does not power down in standby mode.
Drive STBY high to enable standby. In standby mode,
the output impedance of all of the LVDS/SLVS outputs is
approximately 342Ω, if DT is low. The output impedance
of the differential LVDS/SLVS outputs is 100Ω when DT
is high. See the
Electrical Characteristics
table for typical supply currents during standby. The following list
shows the state of the analog inputs and digital outputs
in standby mode:
•IN_P, IN_N analog inputs are disconnected from the
internal input amplifier
•Reference circuit remains active
•OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 342Ω between the
output pairs when DT is low. When DT is high, the differential output pairs have 100Ω between each pair.
When operating in internal reference mode, the
MAX1437B requires 200µs to power up and settle when
the converter exits standby mode. To exit standby mode,
STBY, the applied control signal must transition from
high to low. When using an external reference, the wakeup time is dependent on the external reference drivers.
Applications Information
Full-Scale Range Adjustments
Using the Internal Reference
The MAX1437B supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, add a 25kΩ
to 250kΩ external resistor or potentiometer (R
ADJ
) between
REFADJ and GND. To increase the full-scale range, add a
25kΩ to 250kΩ resistor between REFADJ and REFIO.
Figure 8 shows the two possible configurations.
The following equations provide the relationship between
R
SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.
CLKOUTN/
FRAMEN
= 50
Z
Ω
0
100
Ω
Z
= 50
Ω
0
⎛
FSRV
=+
07 1
FSRV
=
07 1
⎜
⎝
⎛
⎜
⎝
125..Ω
125..Ω
−
R
R
ADJ
ADJ
k
⎞
k
⎟
⎠
⎞
⎟
⎠
MAX1437B
Using Transformer Coupling
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal. The MAX1437B input common-mode voltage is internally biased to 0.76V (typ)
with f
CLK
= 50MHz. Although a 1:1 transformer is
shown, a step-up transformer can be selected to
reduce the drive requirements. A reduced signal swing
from the input driver, such as an op amp, can also
improve the overall distortion.
Grounding, Bypassing, and Board Layout
The MAX1437B requires high-speed board layout
design techniques. Refer to the MAX1437B EV kit data
sheet for a board layout reference. Locate all bypass
capacitors as close as possible to the device, preferably on the same side as the ADC, using surface-mount
devices for minimum inductance. Bypass AVDD to GND
with a 0.1µF ceramic capacitor in parallel with a 0.1µF
ceramic capacitor. Bypass OVDD to GND with a 0.1µF
ceramic capacitor in parallel with a ≥ 2.2µF ceramic
capacitor. Bypass CVDD to GND with a 0.1µF ceramic
capacitor in parallel with a ≥ 2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. Connect
the MAX1437B ground pins and the exposed backside
pad to the same ground plane. The MAX1437B relies
on the exposed-backside-pad connection for a lowinductance ground connection. Isolate the ground
plane from any noisy digital system ground planes.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equally. Refer to the MAX1437B EV kit data sheet for an
example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX1437B, this
straight line is between the end points of the transfer
function, once offset and gain errors have been nullified. INL deviations are measured at every step and the
worst-case deviation is reported in the
Electrical
Characteristics
table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX1437B, DNL
deviations are measured at every step and the worstcase deviation is reported in the
Electrical
Characteristics
table.
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
Figure 8. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
Figure 9. Transformer-Coupled Input Drive
ADC FULL-SCALE = REFT - REFB
REFERENCE-
SCALING
REFT
REFB
REFERENCE
BUFFER
1V
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
MAX1437B
AMPLIFIER
G
REFADJ
AVDDAVDD/2
REFIO
0.1µF
25kΩ
TO 250k
25kΩ
TO 250k
Ω
Ω
0.1µF
V
IN
N.C.
MINICIRCUITS
1
T1
2
3
ADT1-1WT
10
Ω
6
5
4
39pF
0.1µF
10
Ω
39pF
IN_P
MAX1437B
IN_N
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. For the MAX1437B, the ideal
midscale digital output transition occurs when there is
-1/2 LSBs across the analog inputs (Figure 6). Bipolar
offset error is the amount of deviation between the measured midscale transition point and the ideal midscale
transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1437B, the
gain error is the difference of the measured full-scale
and zero-scale transition points minus the difference of
the ideal full-scale and zero-scale transition points.
For the bipolar device (MAX1437B), the full-scale transition point is from 0x7FE to 0x7FF and the zero-scale
transition point is from 0x800 to 0x801.
Crosstalk
Crosstalk indicates how well each analog input is
isolated from the others. For the MAX1437B, a 5.3MHz,
-0.5dBFS analog signal is applied to 1 channel while a
24.1MHz, -0.5dBFS analog signal is applied to another
channel. An FFT is taken on the channel with the 5.3MHz
analog signal. From this FFT, the crosstalk is measured
as the difference in the 5.3MHz and 24.1MHz amplitudes.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken. See Figure 10.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the aperture delay. See Figure 10.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
dB[max]
= 6.02dBx N + 1.76
dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc.
For the MAX1437B, SNR is computed by taking the
ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is
expressed as:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious
component, excluding DC offset. SFDR is specified in
decibels relative to the carrier (dBc).
IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones f1and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows:
•3rd-order intermodulation products (IM3): 2 x f1- f2,
2 x f2- f1, 2 x f1+ f2, 2 x f2+ f
1
•4th-order intermodulation products (IM4): 3 x f1- f2,
3 x f2- f1, 3 x f1+ f2, 3 x f2+ f
1
•5th-order intermodulation products (IM5): 3 x f1- 2
x f2, 3 x f2- 2 x f1, 3 x f1+ 2 x f2, 3 x f2+ 2 x f
1
Third-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation
product to the Nyquist frequency relative to the total
input power of the two input tones f1and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order
intermodulation products are 2 x f1- f2, 2 x f2- f1, 2 x f
1
+ f2, 2 x f2+ f1.
Small-Signal Bandwidth
A small -20.5dBFS analog input signal is applied to an
ADC so that the signal’s slew rate does not limit the
ADC’s performance. The input frequency is then swept
up to the point where the amplitude of the digitized
conversion result has decreased by -3dB.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Gain Matching
Gain matching is a figure of merit that indicates how
well the gain of all 8 ADC channels is matched to each
other. For the MAX1437B, gain matching is measured
by applying the same 5.3MHz, -0.5dBFS analog signal
to all analog input channels. These analog inputs are
sampled at 50Msps and the maximum deviation in
amplitude is reported in dB as gain matching in the
Electrical Characteristics
table.
Phase Matching
Phase matching is a figure of merit that indicates how
well the phases of all 8 ADC channels are matched to
each other. For the MAX1437B, phase matching is
measured by applying the same 5.3MHz, -0.5dBFS
analog signal to all analog input channels. These analog inputs are sampled at 50Msps and the maximum
deviation in phase is reported in degrees as phase
matching in the
Electrical Characteristics
table.
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600