MAXIM MAX1437B User Manual

General Description
The MAX1437B octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1437B operates from a 1.8V sin­gle supply and consumes only 768mW (96mW per channel) while delivering a 70.2dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1437B features a low­power standby mode for idle periods.
An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference struc­ture allows the use of an external reference for applica­tions requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise.
A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed ser­ial low-voltage differential signal (LVDS) clock.
The MAX1437B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two’s complement format.
The MAX1437B offers a maximum sample rate of 50Msps. This device is available in a small, 10mm x 10mm x 0.8mm, 68-pin TQFN package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
Features
o Excellent Dynamic Performance
70.2dB SNR at 5.3MHz 98dBc SFDR at 5.3MHz 82dB Channel Isolation at 5.3MHz
o Ultra-Low Power
96mW per Channel (Normal Operation)
o Serial LVDS Outputs
o Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
o LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
o Test Mode for Digital Signal Integrity
o Fully Differential Analog Inputs
o Wide Differential Input Voltage Range (1.4V
P-P
)
o On-Chip 1.24V Precision Bandgap Reference
o Clock Duty-Cycle Equalizer
o Compact, 68-Pin TQFN Package with Exposed
Pad
o Evaluation Kit Available (Order MAX1437BEVKIT)
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4204; Rev 2; 2/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX1437BETK+ -40°C to +85°C 68 TQFN-EP*
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to GND)
AVDD.....................................................................-0.3V to +2.0V
CVDD.....................................................................-0.3V to +3.6V
OVDD ....................................................................-0.3V to +2.0V
IN_P, IN_N ..............................................-0.3V to (V
AVDD
+ 0.3V)
CLK ........................................................-0.3V to (V
CVDD
+ 0.3V)
OUT_P, OUT_N, FRAME_, CLKOUT_ ......-0.3V to (V
OVDD
+ 0.3V)
DT, SLVS/LVDS, LVDSTEST, PLL_,
REFIO, REFADJ, CMOUT...................-0.3V to (V
AVDD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
TQFN (derate 70mW/°C above +70°C) .....................4000mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ...........20°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............0.5°C/W
ELECTRICAL CHARACTERISTICS
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF || 1.0µF, C
REFP
= 10µF, C
REFN
=
10µF, f
CLK
= 50MHz (50% duty cycle), VDT= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Notes 2, 3)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.
DC ACCURACY (Note 2)
Resolution N 12 Bits
Integral Nonlinearity INL ±0.3 ±2.5 LSB
Differential Nonlinearity DNL No missing codes over temperature ±0.25 ±1 LSB
Offset Error ±0.5 %FS
Gain Error -3 ±0.5 +2 %FS
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range V
Common-Mode Voltage Range V
Common-Mode Voltage Range Tolerance
Differential Input Impedance R
Differential Input Capacitance C
CONVERSION RATE
Maximum Conversion Rate f
Minimum Conversion Rate f
Data Latency 6.5 Cycles
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 5)
Signal-to-Noise Ratio SNR
Signal-to-Noise and Distortion SINAD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ID
CMO
IN
IN
SMAX
SMIN
Differential input 1.4 V
(Note 4) ±50 mV
Switched capacitor load 2 kΩ
fIN = 5.3MHz at -0.5dBFS 70.2
f
IN
fIN = 5.3MHz at -0.5dBFS 70.2
f
IN
= 20MHz at -0.5dBFS 67 70.2
= 20MHz at -0.5dBFS 67 70.1
0.76 V
12.5 pF
50 MHz
4.0 MHz
P-P
dB
dB
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF || 1.0µF, C
REFP
= 10µF, C
REFN
=
10µF, f
CLK
= 50MHz (50% duty cycle), VDT= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Notes 2, 3)
Effective Number of Bits ENOB
Spurious-Free Dynamic Range SFDR
Total Harmonic Distortion THD
Intermodulation Distortion IMD
Third-Order Intermodulation IM3
Aperture Jitter t
Aperture Delay t
Small-Signal Bandwidth SSBW Input at -20dBFS 100 MHz
Full-Power Bandwidth LSBW Input at -0.5dBFS 100 MHz
Output Noise IN_P = IN_N 0.44 LSB
Overrange Recovery Time t
INTERNAL REFERENCE
REFADJ Internal Reference-Mode Enable Voltage
REFADJ Low-Leakage Current 1.5 mA
REFIO Output Voltage V
Reference Temperature Coefficient
EXTERNAL REFERENCE
REFADJ External Reference­Mode Enable Voltage
REFADJ High-Leakage Current 200 µA
REFIO Input Voltage 1.24 V
REFIO Input Voltage Tolerance ±5 %
REFIO Input Current I
COMMON-MODE OUTPUT (CMOUT)
CMOUT Output Voltage V
CLOCK INPUT (CLK)
Input High Voltage V
Input Low Voltage V
Clock Duty Cycle 50 %
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AJ
AD
OR
REFIO
TC
REFIO
REFIO
CMOUT
CLKH
CLKL
fIN = 5.3MHz at -0.5dBFS 11.4
f
= 20MHz at -0.5dBFS 10.8 11.4
IN
fIN = 5.3MHz at –0.5dBFS 98
f
= 20MHz at -0.5dBFS 79 93
IN
fIN = 5.3MHz at -0.5dBFS -96
= 20MHz at -0.5dBFS -93 -78
f
IN
= 5.3MHz at -6.5dBFS
f
1
f
= 6.3MHz at -6.5dBFS
2
= 5.3MHz at -6.5dBFS
f
1
f
= 6.3MHz at -6.5dBFS
2
Figure 10 < 0.4 ps
Figure 10 1 ns
RS = 25Ω, CS = 50pF 1
(Note 6) 0.1 V
(Note 6)
1.18 1.24 1.30 V
V
AVDD
0.1
0.8 x
V
AVDD
90.7 dBc
98.7 dBc
120 ppm/°C
-
< 1 µA
0.76 V
0.2 x
V
AVDD
Bits
dBc
dBc
RMS
RMS
Clock
cycle
V
V
V
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF || 1.0µF, C
REFP
= 10µF, C
REFN
=
10µF, f
CLK
= 50MHz (50% duty cycle), VDT= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Clock Duty-Cycle Tolerance ±30 %
Input Leakage Current DI
Input Capacitance DC
Input at GND 5
IN
Input at V
IN
AVDD
80
5pF
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY)
Input Logic-High Voltage V
Input Logic-Low Voltage V
Input Leakage Current DI
Input Capacitance DC
IH
IL
Input at GND 5
IN
Input at V
IN
AVDD
0.8 x
V
AVDD
0.2 x
V
AVDD
80
5pF
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = LOW
Differential Output Voltage V
Output Common-Mode Voltage V
Rise Time (20% to 80%) t
Fall Time (80% to 20%) t
OHDIFFRTERM
OCMRTERM
RL
FL
= 100 250 450 mV = 100 1.125 1.375 V
R
R
TERM
TERM
= 100, C = 100, C
= 5pF 350 ps
LOAD
= 5pF 350 ps
LOAD
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = HIGH, DT = HIGH
Differential Output Voltage V
Output Common-Mode Voltage V
Rise Time (20% to 80%) t
Fall Time (80% to 20%) t
OHDIFFRTERM
OCMRTERM
RS
FS
= 100 205 mV = 100 220 mV
R
R
TERM
TERM
= 100, C = 100, C
= 5pF 320 ps
LOAD
= 5pF 320 ps
LOAD
STANDBY MODE (STBY)
STBY Fall to Output Enable t
STBY Rise to Output Disable t
ENABLE
DISABLE
200 µs
60 ns
POWER REQUIREMENTS
AVDD Supply Voltage Range V
OVDD Supply Voltage Range V
CVDD Supply Voltage Range V
AVDD
OVDD
CVDD
1.7 1.8 1.9 V
1.7 1.8 1.9 V
1.7 1.8 3.5 V
STBY = low, DT = low 348 390
AVDD Supply Current I
AVDD
fIN = 20MHz at -0.5dBFS
STBY = low, DT = high 348
S TBY = hi g h, n o cl ock
37 mA
STBY = low 74 100
OVDD Supply Current I
CVDD Supply Current I
Power Dissipation P
OVDD
CVDD
DISSfIN
fIN = 20MHz at -0.5dBFS
CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2
STBY = low, DT = high 103
S TBY = hi g h, no cl ock inp ut 16 µA
0mA
= 20MHz at -0.5dBFS 759 882 mW
µA
V
V
µA
mA
mA
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, external V
REFIO
= 1.24V, C
REFIO
= 0.1µF || 1.0µF, C
REFP
= 10µF, C
REFN
=
10µF, f
CLK
= 50MHz (50% duty cycle), VDT= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Notes 2, 3)
Note 2: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 3: All capacitances are between the indicated pin and GND, unless otherwise noted. Note 4: See the
Common-Mode Output (CMOUT)
section.
Note 5: See definition in the
Parameter Definitions
section at the end of this data sheet.
Note 6: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the internal
bandgap reference and enable external reference mode.
Note 7: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 8: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f
CLK
=
50MHz (50% duty cycle), VDT= 0V, C
LOAD
= 10pF, TA= +25°C, unless otherwise noted.)
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1437B toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
-110 5101502025
HD2
HD3
f
CLK
= 50.1523789MHz
f
IN
= 5.304814MHz
A
IN
= -0.5dBFS SNR = 69.959dB SINAD = 69.950dB THD = -96.635dBc SFDR = 96.503dBc
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1437B toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
-110
f
CLK
= 50.1523789MHz
f
IN
= 24.0997118MHz
A
IN
= -0.5dBFS SNR = 69.707dB SINAD = 69.672dB THD = -90.672dBc SFDR = 93.694dBc
51015020
25
HD2
HD3
CROSSTALK
(16,384-POINT DATA RECORD)
MAX1437B toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
10
-30
-10
-50
-90
-110
-70
5101502025
f
IN(IN2)
MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2 f
IN(IN1)
= 5.304814MHz
f
IN(IN2)
= 24.0997118MHz
CROSSTALK = -76dB
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Note 7)
Data Valid to CLKOUT Rise/Fall t
CLKOUT Output-Width High t
CLKOUT Output-Width Low t
FRAME Rise to CLKOUT Rise t
Sample CLK Rise to FRAME Rise t
Figure 5 (Note 8)
OD
Figure 5 t
CH
Figure 5 t
CL
Figure 4 (Note 8)
CF
Figure 4 (Note 8)
SF
(t
SAMPL E
- 0.15
(t
SAMPL E
- 0.15
( t
S AM P LE
+ 1.1
/24)
S AM P LE
S AM P LE
/24)
/2)
(t
/24)
SAMPL E
+ 0.15
ns
/12 ns
/12 ns
(t
/24)
SAMPL E
+ 0.15
( t
S AM P LE
+ 2.6
/2)
ns
ns
Crosstalk (Note 5) -75 dB
Gain Matching C
Phase Matching C
GMfIN
PMfIN
= 5.3MHz (Note 5) ±0.1 dB
= 5.3MHz (Note 5) ±0.25 D eg r ees
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f
CLK
=
50MHz (50% duty cycle), V
DT
= 0V, C
LOAD
= 10pF, TA= +25°C, unless otherwise noted.)
MAX1437B toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
-110
TWO-TONE INTERMODULATION DISTORTION
(16,384-POINT DATA RECORD)
f
IN(IN1)
= 5.299375MHz
f
IN(IN2)
= 6.299775MHz
A
IN1
= -6.5dBFS
A
IN2
= -6.5dBFS IMD = 90.7dBc IM3 = 98.7dBc
0 5 10 15 20 25
1
-1
-10 1 100 1000
-6
-7
-8
-9
-5
-4
-3
-2
MAX1437B toc05
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10
BANDWIDTH
vs. ANALOG INPUT FREQUENCY
0
FULL-POWER BANDWIDTH
-0.5dBFS
SMALL-SIGNAL BANDWIDTH
-20.5dBFS
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
f
(MHz)
SNR (dB)
1008020 40 60
63
64
65
67
69
66
68
70
71
MAX1437B toc06
72
62
0120
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
fIN (MHz)
SINAD (dB)
1008020 40 60
63
64
65
67
69
66
68
70
71
MAX1437B toc07
72
62
0120
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
fIN (MHz)
THD (dBc)
1008020 40 60
-95
-90
-85
-75
-70
-80
-65
-60
MAX1437B toc08
-55
-100 0 120
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
fIN (MHz)
SFDR (dBc)
1008020 40 60
60
65
70
80
85
75
90
95
MAX1437B toc09
100
55
0120
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
ANALOG INPUT POWER (dBFS)
SNR (dB)
-5-10-25 -20 -15
37
42
52
57
47
62
67
72
32
-30 0
MAX1437B toc10
fIN = 5.304814MHz
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER
ANALOG INPUT POWER (dBFS)
SINAD (dB)
-5-10-25 -20 -15
37
42
52
57
47
62
MAX1437B toc11
67
72
32
-30 0
fIN = 5.304814MHz
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
ANALOG INPUT POWER (dBFS)
THD (dBc)
-5-10-25 -20 -15
-90
-95
-85
-75
-70
-80
-65
-60
-55
-105
-100
-30 0
MAX1437B toc12
fIN = 5.304814MHz
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
_______________________________________________________________________________________ 7
)
C
)
C
)
Typical Operating Characteristics (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f
CLK
=
50MHz (50% duty cycle), V
DT
= 0V, C
LOAD
= 10pF, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
105
fIN = 5.304814MHz
100
95
90
85
80
SFDR (dBc)
75
70
65
60
55
-30 0 ANALOG INPUT POWER (dBFS
TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
-75 fIN = 5.304814MHz
-80
-85
-90
THD (dBc)
-95
-100
-105
f
(MHz)
CLK
SIGNAL-TO-NOISE PLUS DISTORTION
vs. DUTY CYCLE
73
fIN = 5.304814MHz
72
71
70
69
SINAD (dB)
68
67
66
65
30 70
DUTY CYCLE (%)
353015 20 2510 5040 45
60 655540 4535 50
-5-10-25 -20 -15
MAX1437B toc13
MAX1437B toc16
MAX1437B toc19
SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
72
fIN = 5.304814MHz
71
70
69
68
67
SNR (dB)
66
65
64
63
62
10 5040 45
353015 20 25
f
(MHz
LK
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
105
fIN = 5.304814MHz
100
95
90
SFDR (dBc)
85
80
75
f
CLK
353015 20 2510 5040 45
(MHz)
TOTAL HARMONIC DISTORTION
vs. DUTY CYCLE
-75 fIN = 5.304814MHz
-80
-85
-90
THD (dBc)
-95
-100
-105 30 70
DUTY CYCLE (%)
SIGNAL-TO-NOISE PLUS DISTORTION
72
71
MAX1437B toc14
70
69
68
67
66
SINAD (dB)
65
64
63
62
10 5040 45
73
72
MAX1437B toc17
71
70
69
SNR (dB)
68
67
66
65
30 70
100
95
MAX1437B toc20
90
85
SFDR (dBc)
80
75
70
60 655540 4535 50
30 70
vs. SAMPLING RATE
fIN = 5.304814MHz
353015 20 25
f
(MHz
LK
SIGNAL-TO-NOISE RATIO
vs. DUTY CYCLE
fIN = 5.304814MHz
60 655540 4535 50
DUTY CYCLE (%)
SPURIOUS-FREE DYNAMIC RANGE
vs. DUTY CYCLE
fIN = 5.304814MHz
60 655540 4535 50
DUTY CYCLE (%)
MAX1437B toc15
MAX1437B toc18
MAX1437B toc21
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f
CLK
=
50MHz (50% duty cycle), V
DT
= 0V, C
LOAD
= 10pF, TA= +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
TEMPERATURE (°C)
SNR (dB)
-15 10 6035
68
70
69
67
66
72
71
73
65
-40 85
MAX1437B toc22
f
CLK
= 50MHz
f
IN
= 19.8MHz
4096-POINT DATA RECORD
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
TEMPERATURE (°C)
SINAD (dB)
-15 10 6035
68
70
69
67
66
72
71
73
65
-40 85
MAX1437B toc23
f
CLK
= 50MHz
f
IN
= 19.8MHz
4096-POINT DATA RECORD
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
TEMPERATURE (°C)
THD (dBc)
-15 10 6035
-93
-91
-92
-94
-97
-95
-96
-89
-90
-88
-98
-40 85
MAX1437B toc24
f
CLK
= 50MHz
f
IN
= 19.8MHz
4096-POINT DATA RECORD
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
TEMPERATURE (°C)
SFDR (dBc)
-15 10 6035
95
96
94
91
93
92
97
90
-40 85
MAX1437B toc25
f
CLK
= 50MHz
f
IN
= 19.8MHz
4096-POINT DATA RECORD
280
300
290
320
310
330
340
350
360
0102030 5040
SUPPLY CURRENT
vs. SAMPLING RATE (AVDD)
MAX1437B toc26
f
CLK
(MHz)
I
AVDD
(mA)
55
60
70
65
75
80
85
0 102030 5040
SUPPLY CURRENT
vs. SAMPLING RATE (0VDD)
MAX1437B toc27
f
CLK
(MHz)
I
OVDD
(mA)
OFFSET ERROR
vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET ERROR (%FS)
-15 10 6035
0
-0.01
0.01
0.02
-0.03
-0.02
0.03
0.04
-0.04
-40 85
MAX1437B toc28
GAIN ERROR
vs. TEMPERATURE
TEMPERATURE (°C)
GAIN ERROR (%FS)
-15 10 6035
-0.2
0.2
-0.6
-1.0
-0.4
0
-0.8
-1.2
0.4
0.6
-1.4
-40 85
MAX1437B toc29
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1437B toc30
DIGITAL OUTPUT CODE
INL (LSB)
1024 30722048512 2560 35841536
-0.3
0
-0.4
0.4
-0.2
0.2
-0.1
0.3
0.1
0.5
-0.5 0 4096
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, V
CVDD
= 3.3V, V
GND
= 0V, internal reference, differential input at -0.5dBFS, fIN= 5.3MHz, f
CLK
=
50MHz (50% duty cycle), V
DT
= 0V, C
LOAD
= 10pF, TA= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.3
0.2
0.1
0
DNL (LSB)
-0.1
-0.2
-0.3 1024 30722048512 2560 35841536
0 4096
DIGITAL OUTPUT CODE
INTERNAL REFERENCE VOLTAGE
vs. REFERENCE LOAD CURRENT
1.40
1.35
1.30
1.25
(V)
1.20
REFIO
V
1.15
1.10
1.05
1.00
-250 -150 50 250150-50
-350 350 I
(µA)
REFIO
MAX1437B toc31
MAX1437B toc34
(V)
V
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.251 V
= V
AVDD
OVDD
1.250
(V)
1.249
REFIO
V
1.248
1.247
1.7 2.1 SUPPLY VOLTAGE (V)
CMOUT VOLTAGE
vs. SUPPLY VOLTAGE
0.770 V
= V
AVDD
OVDD
0.768
0.766
CMOUT
0.764
0.762
0.760
1.7 2.1 SUPPLY VOLTAGE (V)
CMOUT VOLTAGE
vs. LOAD CURRENT
1.8
1.6
1.4
1.2
(V)
1.0
0.8
CMOUT
V
0.6
0.4
0.2
0
0 2000
I
(µA)
CMOUT
INTERNAL REFERENCE VOLTAGE
V
V
AVDD
AVDD
= V
= V
vs. TEMPERATURE
OVDD
MAX1437B toc33
603510-15
TEMPERATURE (°C)
CMOUT VOLTAGE
vs. TEMPERATURE
OVDD
MAX1437B toc36
603510-15
TEMPERATURE (°C)
1.26
MAX1437B toc32
1.25
(V)
1.24
REFIO
V
1.23
1.22
2.01.91.8
MAX1437B toc35
2.01.91.8
MAX1437B toc37
15001000500
-40 85
0.770
0.768
0.766
(V)
CMOUT
0.764
V
0.762
0.760
-40 85
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 IN1P Channel 1 Positive Input
2 IN1N Channel 1 Negative Input
3 IN2P Channel 2 Positive Input
4 IN2N Channel 2 Negative Input
5 IN3P Channel 3 Positive Input
6 IN3N Channel 3 Negative Input
7, 8, 10, 11,
25, 26, 27, 60
9, 18, 68 GND Ground. Connect all GND pins to the same potential.
12 IN4P Channel 4 Positive Input
13 IN4N Channel 4 Negative Input
14 IN5P Channel 5 Positive Input
15 IN5N Channel 5 Negative Input
16 IN6P Channel 6 Positive Input
17 IN6N Channel 6 Negative Input
19 IN7P Channel 7 Positive Input
20 IN7N Channel 7 Negative Input
21 DT
22 SLVS/LVDS
23 CVDD
24 CLK Single-Ended CMOS Clock Input
28, 31, 34, 39,
44, 49, 52
29 OUT7N Channel 7 Negative LVDS/SLVS Output
30 OUT7P Channel 7 Positive LVDS/SLVS Output
32 OUT6N Channel 6 Negative LVDS/SLVS Output
33 OUT6P Channel 6 Positive LVDS/SLVS Output
35 OUT5N Channel 5 Negative LVDS/SLVS Output
36 OUT5P Channel 5 Positive LVDS/SLVS Output
37 OUT4N Channel 4 Negative LVDS/SLVS Output
38 OUT4P Channel 4 Positive LVDS/SLVS Output
40 FRAMEN
41 FRAMEP
42 CLKOUTN Negative LVDS/SLVS Serial Clock Output
AVDD
OVDD
Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass AVDD to GND with a
0.1µF capacitor as close as possible to the device. Bypass the AVDD power plane to the GND plane with a bulk capacitor of at least 2.2µF. Connect all AVDD pins to the same potential.
Double Termination Select. Force DT high to select the internal 100 termination between the differential output pairs. Force DT low to select no internal output termination.
Differential Output Signal Format Select Input. Force SLVS/LVDS high to select SLVS outputs. Force SLVS/LVDS low to select LVDS outputs.
Clock Power Input. Connect CVDD to a 1.7V to 3.5V power supply. Bypass CVDD to GND with a
0.1µF capacitor in parallel with a capacitor of at least 2.2µF. Install the bypass capacitors as close as possible to the device.
Output Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass OVDD to GND with a 0.1µF capacitor as close as possible to the device. Bypass the OVDD power plane to the GND plane with a bulk capacitor of at least 2.2µF. Connect all OVDD pins to the same potential.
Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream.
Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream.
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________ 11
Pin Description (continued)
PIN NAME FUNCTION
43 CLKOUTP Positive LVDS/SLVS Serial Clock Output
45 OUT3N Channel 3 Negative LVDS/SLVS Output
46 OUT3P Channel 3 Positive LVDS/SLVS Output
47 OUT2N Channel 2 Negative LVDS/SLVS Output
48 OUT2P Channel 2 Positive LVDS/SLVS Output
50 OUT1N Channel 1 Negative LVDS/SLVS Output
51 OUT1P Channel 1 Positive LVDS/SLVS Output
53 OUT0N Channel 0 Negative LVDS/SLVS Output
54 OUT0P Channel 0 Positive LVDS/SLVS Output
LVDS Test Pattern Enable. Force LVDSTEST high to enable the output test pattern, 0000 1011 1101.
55 LVDSTEST
56 STBY
57 PLL3 PLL Control Input 3. See Table 1 for details.
58 PLL2 PLL Control Input 2. See Table 1 for details.
59 PLL1 PLL Control Input 1. See Table 1 for details.
61 REFN
62 REFP
63 REFIO
64 REFADJ
65 CMOUT
66 IN0P Channel 0 Positive Input
67 IN0N Channel 0 Negative Input
—EP
As with the analog conversion results, the test pattern data are output LSB first. Force LVDSTEST low for normal operation.
Standby Input. Force STBY high to put the MAX1437B into standby mode. In standby, the reference circuitry remains active. Force STBY low for normal operation.
Negative Reference Bypass Output. Connect a capacitor of at least 1µF (10µF typ) between REFP and REFN, and connect a capacitor of at least 1µF (10µF typ) between REFN and GND. Place the capacitors as close as possible to the device on the same side of the PCB as the MAX1437B.
Positive Reference Bypass Output. Connect a capacitor of at least 1µF (10µF typ) between REFP and REFN, and connect a capacitor of at least 1µF (10µF typical) between REFN and GND. Place the capacitors as close as possible to the device on the same side of the PCB as the MAX1437B.
Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable reference voltage at REFIO. Bypass to GND with a capacitor of at least 0.1µF.
Internal/External Reference Mode Select and Reference Adjust Input. For internal reference, connect REFADJ to GND. For external reference, connect REFADJ to AVDD. For adjusting the reference, see the Full-Scale Range Adjustments Using the Internal Reference section.
Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage for DC­coupled applications. Bypass CMOUT to GND with a capacitor of at least 0.1µF.
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane for maximum thermal performance. Must be connected to GND.
MAX1437B
Detailed Description
The MAX1437B ADC features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. The ADC pipeline archi­tecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. The convert­ed digital results are serialized and sent through the LVDS/SLVS output drivers. The total clock-cycle latency from input to output is 6.5 clock cycles.
The MAX1437B offers 8 separate fully differential chan­nels with synchronized inputs and outputs. Global standby minimizes power consumption.
Input Circuit
Figure 1 displays a simplified diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transconduc­tance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differ­ential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
12 ______________________________________________________________________________________
Functional Diagram
CMOUT
IN0P
IN0N
IN1P
IN1N
IN7P
IN7N
CLK
CLOCK
CIRCUITRY
REFADJ REFIO REFP REFN
REFERENCE SYSTEM
ICMV*
T/H
T/H
T/H
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
12-BIT
PIPELINE
ADC
PLL
6x
STBY
POWER
CONTROL
OVDDAVDD
MAX1437B
12:1
SERIALIZER
12:1
SERIALIZER
12:1
SERIALIZER
DT
OUTPUT
CONTROL
LVDS/SLVS
OUTPUT
DRIVERS
SLVS/LVDS
LVDSTEST
OUT0P
OUT0N
OUT1P
OUT1N
OUT7P
OUT7N
FRAMEP
FRAMEN
CLKOUTP
CLKOUTN
CVDD
*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED).
PLL3PLL1 PLL2
GND
then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. Analog inputs, IN_P to IN_N, are driven differentially. For differ­ential inputs, balance the input impedance of IN_P and IN_N for optimum performance.
Reference Configurations (REFIO,
REFADJ, REFP, and REFN)
The MAX1437B provides an internal 1.24V bandgap reference or can be driven with an external reference voltage. The full-scale analog differential input range is ±FSR. FSR (full-scale range) is given by the following equation:
where V
REFIO
is the voltage at REFIO, generated inter-
nally or externally. For a V
REFIO
= 1.24V, the full-scale
input range is ±700mV (1.4V
P-P
).
Internal Reference Mode
Connect REFADJ to GND to use the internal bandgap reference directly. The internal bandgap reference gen­erates V
REFIO
to be 1.24V with a 120ppm/°C tempera­ture coefficient in internal reference mode. Connect an external 0.1µF bypass capacitor from REFIO to GND for stability. REFIO sources up to 200µA and sinks up to 200µA for external circuits, and REFIO has a 75mV/mA load regulation. Putting the MAX1437B into standby mode turns off all circuitry except the reference circuit, allowing the converter to power up faster when the ADC exits standby with a high-to-low transitional signal on STBY. The internal circuits of the MAX1437B require 200µs to power up and settle when the converter exits standby mode.
To compensate for gain errors or to decrease or increase the ADC’s FSR, add an external resistor between REFADJ and GND or REFADJ and REFIO. This adjusts the internal reference value of the MAX1437B by up to ±5% of its nominal value. See the
Full-Scale Range Adjustments Using the Internal Reference
section.
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________________________ 13
Figure 1. Internal Input Circuit
SWITCHES SHOWN IN TRACK MODE
INTERNALLY
INTERNAL
COMMON-MODE
BIAS*
INTERNAL
BIAS*
GENERATED
COMMON-MODE
LEVEL*
AVDD
IN_P
IN_N
GND
*NOT EXTERNALLY ACCESSIBLE.
INTERNAL
COMMON-MODE
BIAS*
MAX1437B
S4a
S4c S1
S4b
C2a
C2b
V
×(. )
=
0 700
FSR
REFIO
V
.
124
S2a
S2b
INTERNAL
BIAS*
OTA
C1a
C1b
S5a
S5b
INTERNALLY GENERATED
COMMON-MODE
LEVEL*
S3a
OUT
OUT
S3b
MAX1437B
Connect 1µF (10µF typ) capacitors to GND from REFP and REFN and a 1µF (10µF typ) capacitor between REFP and REFN as close to the device as possible on the same side of the PCB.
External Reference Mode
The external reference mode allows for more control over the MAX1437B reference voltage and allows multi­ple converters to use a common reference. Connect REFADJ to AVDD to disable the internal reference. Apply a stable 1.18V to 1.30V source at REFIO. Bypass REFIO to GND with a 0.1µF capacitor. The REFIO input impedance is >1MΩ.
Clock Input (CLK)
The MAX1437B accepts a CMOS-compatible clock sig­nal with a wide 20% to 80% input clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram.
Low clock jitter is required for the specified SNR perfor­mance of the MAX1437B. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maxi­mum SNR performance of any ADC according to the following relationship:
where fINrepresents the analog input frequency and t
J
is the total system clock jitter.
PLL Inputs (PLL1, PLL2, PLL3)
The MAX1437B features a PLL that generates an output clock signal with six times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1437B (see the
System Timing Requirements
section). Set the PLL1, PLL2, and PLL3 pins according to the input clock range provided in Table 1.
System Timing Requirements
Figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the rela­tionship between the inputs and the outputs.
Clock Output (CLKOUTP, CLKOUTN)
The MAX1437B provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1437B on both edges of the clock output. The frequency of the output clock is six times the frequency of CLK.
Frame-Alignment Output (FRAMEP, FRAMEN)
The MAX1437B provides a differential frame-alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame-align­ment signal corresponds to the first bit (D0) of the 12­bit serial data stream. The frequency of the frame­alignment signal is identical to the frequency of the input clock.
Serial Output Data (OUT_P, OUT_N)
The MAX1437B provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the out­put data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed ser­ial-output timing diagram.
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
14 ______________________________________________________________________________________
Figure 2. Clock Input Circuitry
Table 1. PLL1, PLL2, and PLL3 Configuration Table
SNR
20
log
⎛ ⎜
×× ×
2
π
1
⎞ ⎟
ft
IN J
AVDD
CVDD
CLK
GND
MAX1437B
DUTY-CYCLE
EQUALIZER
INPUT CLOCK RANGE
PLL1 PLL2 PLL3
0 0 0 45.0 50.0
0 0 1 32.5 45.0
0 1 0 22.5 32.5
0 1 1 16.3 22.5
1 0 0 11.3 16.3
1 0 1 8.1 11.3
1 1 0 5.6 8.1
1 1 1 4.0 5.6
(MHz)
MIN MAX
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________ 15
Figure 3. Global Timing Diagram
Figure 4. Detailed Two-Conversion Timing Diagram
Figure 5. Serialized-Output Detailed Timing Diagram
N
(V
-
IN_P
)
V
IN_N
CLK
(V
-
FRAMEP
)*
V
FRAMEN
(V
-
CLKOUTP
)
V
CLKOUTN
-
(V
OUT_P
)
V
OUT_N
*DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY.
t
SAMPLE
N + 1
OUTPUT
DATA FOR
SAMPLE
N - 6
N + 2
N + 3
6.5 CLOCK-CYCLE DATA LATENCY
N + 4
N + 5
N + 6
N + 7
OUTPUT
DATA FOR
SAMPLE N
N + 8
N + 9
N
(V
- V
)
IN_P
IN_N
t
SAMPLE
CLK
-
(V
V
(V
CLKOUTP
V
(V
FRAMEP
)*
FRAMEN
­)
CLKOUTN
-
OUT_P
D5
N-7D6N-7D7N-7D8N-7D9N-7
)
V
OUT_N
*DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY.
D10
N-7
t
CF
D11
N-7D0N-6D1N-6D2N-6D3N-6D4N-6D5N-6D6N-6D7N-6D8N-6D9N-6
(V
CLKOUTP
V
(V
CLKOUTN
OUT_P
V
OUT_N
t
CH
­)
-
D0 D1 D2 D3
)
t
CL
t
OD
t
OD
N + 1
N + 2
t
SF
D10
D11
N-6
N-6D0N-5D1N-5D2N-5D3N-5D4N-5D5N-5D6N-5
MAX1437B
Output Data Transfer Function
The MAX1437B output data format is two’s comple­ment. The following equation, Table 2, and Figure 6 define the relationship between the digital output and the analog input:
where CODE10is the decimal equivalent of the digital output code as shown in Table 2.
Keep the capacitive load on the MAX1437B digital out­puts as low as possible.
LVDS and SLVS Selection (SLVS/
LVDS
)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for SLVS levels at the MAX1437B outputs (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For SLVS levels, enable double-termination by driving DT high. See the
Electrical Characteristics
table for LVDS
and SLVS output voltage levels.
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
16 ______________________________________________________________________________________
Table 2. Output Code Table (V
REFIO
= 1.24V)
Figure 6. Two’s-Complement Transfer Function
TWO’S-COMPLEMENT DIGITAL OUTPUT CODE
BINARY
D11 D0
0111 1111 1111 0x7FF +2047 +699.66
0111 1111 1110 0x7FE +2046 +699.32
0000 0000 0001 0x001 +1 +0.34
0000 0000 0000 0x000 0 0
1111 1111 1111 0xFFF -1 -0.34
1000 0000 0001 0x801 -2047 -699.66
1000 0000 0000 0x800 -2048 -700.00
HEXADECIMAL EQUIVALENT
OF D11 → D0
0x7FF 0x7FE 0x7FD
0x001 0x000 0xFFF
2 x FSR
1 LSB =
4096
FSR FSR
DECIMAL EQUIVALENT
OF D11 → D0
V
FSR = 700mV x
REFIO
1.24V
V
IN_P
(V
REFIO
- VIN_N (mV) = 1.24V)
0x803 0x802 0x801
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
0x800
-2045 +2047+2045-1 0 +1-2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
CODE
V V FSR
−=××2
IN P IN N__
10
4096
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101. Drive LVDSTEST low for nor­mal operation (test pattern disabled).
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DC­coupled analog inputs. If the input is DC-coupled, match the output common-mode voltage of the circuit driving the MAX1437B to the output voltage at V
CMOUT
to within ±50mV. It is recommended that the output common-mode voltage of the driving circuit be derived from CMOUT.
Double Termination (DT)
The MAX1437B offers an optional, internal 100Ω termi- nation between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (> 5in) or with mismatched impedance. Drive DT high to select double-termination, or drive DT low to disconnect the internal termination resistor (single-ter­mination). Selecting double-termination increases the OVDD supply current (see Figure 7).
Standby Mode
The MAX1437B offers a standby mode to efficiently use power by transitioning to a low-power state when con­versions are not required. STBY controls the standby mode of all channels and the internal reference circuitry. The reference does not power down in standby mode. Drive STBY high to enable standby. In standby mode, the output impedance of all of the LVDS/SLVS outputs is approximately 342, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100when DT is high. See the
Electrical Characteristics
table for typi­cal supply currents during standby. The following list shows the state of the analog inputs and digital outputs in standby mode:
IN_P, IN_N analog inputs are disconnected from the
internal input amplifier
Reference circuit remains active
OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 342between the output pairs when DT is low. When DT is high, the dif­ferential output pairs have 100between each pair.
When operating in internal reference mode, the MAX1437B requires 200µs to power up and settle when
the converter exits standby mode. To exit standby mode, STBY, the applied control signal must transition from high to low. When using an external reference, the wake­up time is dependent on the external reference drivers.
Applications Information
Full-Scale Range Adjustments
Using the Internal Reference
The MAX1437B supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, add a 25k to 250kexternal resistor or potentiometer (R
ADJ
) between REFADJ and GND. To increase the full-scale range, add a 25kto 250kresistor between REFADJ and REFIO. Figure 8 shows the two possible configurations.
The following equations provide the relationship between R
ADJ
and the change in the analog full-scale range:
for R
ADJ
connected between REFADJ and REFIO, and:
for R
ADJ
connected between REFADJ and GND.
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________________________ 17
Figure 7. Double Termination
DT
OUT_P/ CLKOUTP/ FRAMEP
100
OUT_N/
MAX1437B
SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW.
CLKOUTN/ FRAMEN
= 50
Z
0
100
Z
= 50
0
FSR V
=+
07 1
FSR V
=
07 1
⎜ ⎝
⎛ ⎜
125..
125..
R
R
ADJ
ADJ
k
k
⎟ ⎠
⎞ ⎟
MAX1437B
Using Transformer Coupling
An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. The MAX1437B input com­mon-mode voltage is internally biased to 0.76V (typ) with f
CLK
= 50MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.
Grounding, Bypassing, and Board Layout
The MAX1437B requires high-speed board layout design techniques. Refer to the MAX1437B EV kit data sheet for a board layout reference. Locate all bypass capacitors as close as possible to the device, prefer­ably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD to GND with a 0.1µF ceramic capacitor in parallel with a 0.1µF ceramic capacitor. Bypass OVDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass CVDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect
the MAX1437B ground pins and the exposed backside pad to the same ground plane. The MAX1437B relies on the exposed-backside-pad connection for a low­inductance ground connection. Isolate the ground plane from any noisy digital system ground planes.
Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns.
Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equal­ly. Refer to the MAX1437B EV kit data sheet for an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer function from a straight line. For the MAX1437B, this straight line is between the end points of the transfer function, once offset and gain errors have been nulli­fied. INL deviations are measured at every step and the worst-case deviation is reported in the
Electrical
Characteristics
table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1437B, DNL deviations are measured at every step and the worst­case deviation is reported in the
Electrical
Characteristics
table.
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
18 ______________________________________________________________________________________
Figure 8. Circuit Suggestions to Adjust the ADC’s Full-Scale Range
Figure 9. Transformer-Coupled Input Drive
ADC FULL-SCALE = REFT - REFB
REFERENCE-
SCALING
REFT
REFB
REFERENCE
BUFFER
1V
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
MAX1437B
AMPLIFIER
G
REFADJ
AVDD AVDD/2
REFIO
0.1µF
25kΩ TO 250k
25kΩ TO 250k
0.1µF
V
IN
N.C.
MINICIRCUITS
1
T1
2
3
ADT1-1WT
10
6
5
4
39pF
0.1µF
10
39pF
IN_P
MAX1437B
IN_N
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1437B, the ideal midscale digital output transition occurs when there is
-1/2 LSBs across the analog inputs (Figure 6). Bipolar offset error is the amount of deviation between the mea­sured midscale transition point and the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1437B, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points.
For the bipolar device (MAX1437B), the full-scale transi­tion point is from 0x7FE to 0x7FF and the zero-scale transition point is from 0x800 to 0x801.
Crosstalk
Crosstalk indicates how well each analog input is isolated from the others. For the MAX1437B, a 5.3MHz,
-0.5dBFS analog signal is applied to 1 channel while a
24.1MHz, -0.5dBFS analog signal is applied to another channel. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 24.1MHz amplitudes.
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 10.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 10.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N bits):
SNR
dB[max]
= 6.02dBx N + 1.76
dB
In reality, there are other noise sources besides quantiza­tion noise: thermal noise, reference noise, clock jitter, etc.
For the MAX1437B, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre­quency excluding the fundamental, the first six harmon­ics (HD2–HD7), and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distor­tion includes all spectral components to the Nyquist fre­quency, excluding the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from:
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon­ics of the input signal to the fundamental itself. This is expressed as:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc).
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________ 19
Figure 10. Aperture Jitter/Delay Specifications
CLK
t
AD
ANALOG
INPUT
t
AJ
SAMPLED
DATA
T/H
HOLD TRACK HOLD
ENOB
SINAD=−
⎛ ⎜
602..
176
⎞ ⎟
THD
log
20
VVVVVV
+++++
22324252627
⎜ ⎜
V
1
2
⎟ ⎟
MAX1437B
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f1and f2. The indi­vidual input tone levels are at -6.5dBFS. The intermodu­lation products are as follows:
2nd-order intermodulation products (IM2): f1+ f2,
f2- f
1
3rd-order intermodulation products (IM3): 2 x f1- f2,
2 x f2- f1, 2 x f1+ f2, 2 x f2+ f
1
4th-order intermodulation products (IM4): 3 x f1- f2,
3 x f2- f1, 3 x f1+ f2, 3 x f2+ f
1
5th-order intermodulation products (IM5): 3 x f1- 2
x f2, 3 x f2- 2 x f1, 3 x f1+ 2 x f2, 3 x f2+ 2 x f
1
Third-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f1and f2. The indi­vidual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1- f2, 2 x f2- f1, 2 x f
1
+ f2, 2 x f2+ f1.
Small-Signal Bandwidth
A small -20.5dBFS analog input signal is applied to an ADC so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as full­power input bandwidth frequency.
Gain Matching
Gain matching is a figure of merit that indicates how well the gain of all 8 ADC channels is matched to each other. For the MAX1437B, gain matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 50Msps and the maximum deviation in amplitude is reported in dB as gain matching in the
Electrical Characteristics
table.
Phase Matching
Phase matching is a figure of merit that indicates how well the phases of all 8 ADC channels are matched to each other. For the MAX1437B, phase matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These ana­log inputs are sampled at 50Msps and the maximum deviation in phase is reported in degrees as phase matching in the
Electrical Characteristics
table.
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
20 ______________________________________________________________________________________
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________ 21
Pin Configuration
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
68 TQFN T6800+4
21-0142
90-0101
Chip Information
PROCESS: BiCMOS
TOP VIEW
IN1P IN1N IN2P IN2N IN3P IN3N
AVDD AVDD
GND
AVDD
AVDD
IN4P IN4N
IN5P
IN5N
IN6P IN6N
AVDD
PLL1
PLL2
PLL3
STBY
OUT7N
OUT7P
LVDSTEST
OVDD
GND
IN0N
IN0P
CMOUT
REFADJ
REFIO
REFP
REFN
6768 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1
2
+
3
4
5
6
7
CLK
CVDD
SLVS/LVDS
MAX1437B
AVDD
AVDD
TQFN
AVDD
OVDD
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
IN7P
IN7N
DT
GND
10mm x 10mm x 0.8mm
OUT0P
*EP
OUT6N
OVDD
OUT0N
OUT6P
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
OVDD
OUT1P OUT1N OVDD OUT2P OUT2N
OUT3P OUT3N OVDD CLKOUTP
CLKOUTN FRAMEP
FRAMEN OVDD OUT4P
OUT4N OUT5P
OUT5N
*CONNECT EP TO GND.
MAX1437B
Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 7/08 Initial release
1 12/08 Corrected errors in the Internal Reference Mode and Gain Error sections. 13, 19
2 2/11
REVISION
DATE
DESCRIPTION
Added new Package Thermal Characteristics section and fixed errors in EC table
PAGES
CHANGED
2–5
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