General Description
The MAX1422 3.3V, 12-bit analog-to-digital converter
(ADC) features a fully differential input, pipelined, 12stage ADC architecture with wideband track-and-hold
(T/H) and digital error correction incorporating a fully-differential signal path. The MAX1422 is optimized for lowpower, high dynamic performance applications in
imaging and digital communications. The converter
operates from a single 3.3V supply, consuming only
137mW while delivering a 67dB (typ) signal-to-noise
ratio (SNR) at a 5MHz input frequency and a 20Msps
sampling frequency. The fully-differential input stage
has a small signal -3dB bandwidth of 400MHz and may
be operated with single-ended inputs.
An internal 2.048V precision bandgap reference sets
the ADCs full-scale range. A flexible reference structure
accommodates an internally or externally applied
buffered or unbuffered reference for applications
requiring increased accuracy or a different input voltage range.
In addition to low operating power, the MAX1422 features
two power-down modes, a reference power-down, and a
shutdown mode. In reference power-down, the internal
bandgap reference is deactivated, resulting in a 2mA
(typ) supply current reduction. For idle periods, a full
shutdown mode is available to maximize power savings.
The MAX1422 provides parallel, offset binary, CMOScompatible three-state outputs.
The MAX1422 is available in a 7mm ✕ 7mm ✕ 1.4mm,
48-pin TQFP package and is specified over the commercial (0°C to +70°C) and extended industrial (-40°C
to +85°C) temperature ranges.
Pin-compatible higher-speed versions of the MAX1422
are also available. Please refer to the MAX1421 data
sheet for 40Msps and the MAX1420 data sheet for
60Msps.
________________________Applications
Medical Ultrasound Imaging
CCD Pixel Processing
Data Acquisition
Radar
IF and Baseband Digitization
Features
♦ Single 3.3V Power Supply
♦ 67dB SNR at f
IN
= 5MHz
♦ Internal 2.048V Precision Bandgap Reference
♦ Differential Wideband Input T/H Amplifier
♦ Power-Down Modes
130mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
♦ Space-Saving 48-Pin TQFP Package
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
________________________________________________________________ Maxim Integrated Products 1
D9
D8
D7
D6
DV
DD
DV
DD
DGND
DGND
D5
D4
D3
D2
AGND
AV
DD
AV
DD
AGND
AGND
INP
INN
AGND
AGND
AV
DD
AV
DD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TQFP
MAX1422
AGND
AV
DDAVDD
AGND
CLK
CLK
AGND
AV
DDDVDD
DGND
D0
D1
1314151617181920212223
24
4847464544434241403938
37
AGND
AVDDCML
REFN
REFP
REFIN
AVDDAGNDPDOE
D11
D10
Pin Configuration
19-1899; Rev 1; 5/04
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX1422CCM
0°C to +70°C 48 TQFP
MAX1422ECM
48 TQFP
Functional Diagram appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
-40°C to +85°C
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dBFS, internal reference, f
CLK
= 20MHz (50%
duty cycle); digital output load C
L
= 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDDto AGND..............................................-0.3V to +4V
DV
DD
, AVDDto DGND..............................................-0.3V to +4V
DGND to AGND.....................................................-0.3V to +0.3V
INP, INN, REFP, REFN, REFIN,
CML,CLK,
CLK, ....................(AGND - 0.3V) to (AVDD+ 0.3V)
D0–D11, OE, PD .......................(DGND - 0.3V) to (DV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP (derate 21.7mW/°C above +70°C)........1739mW
Operating Temperature Ranges
MAX1422CCM ....................................................0°C to +70°C
MAX1422ECM .................................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
Resolution RES 12 Bits
TA = +25°C, no missing codes -1 1
Differential Nonlinearity DNL
T
A
= T
MIN
to T
MAX
LSB
Integral Nonlinearity INL TA = T
MIN
to T
MAX
±2 LSB
Mid-scale Offset MSO -3
3
%FSR
Mid-scale Offset Temperature
Coefficient
%/°C
Internal reference (Note 1) -5
5
-5
5
Gain Error GE
External reference applied to REFP, CML,
and REFN (Note 3)
1.5
%FSR
Gain Error Temperature
Coefficient
GETC
External reference applied to REFP, CML,
and REFN (Note 3)
%/°C
DYNAMIC PERFORMANCE (f
CLK
= 20MHz, 4096-point FFT)
Signal-to-Noise Ratio SNR fIN = 5MHz, TA = +25°C6367dB
Spurious-Free Dynamic Range SFDR fIN = 5MHz, TA = +25°C 64 74 dBc
Total Harmonic Distortion THD fIN = 5MHz, TA = +25°C -72 -63 dBc
Signal-to-Noise and Distortion
fIN = 5MHz, TA = +25°C6065dB
Effective Number of Bits ENOB
f
IN
= 5MHz
Bits
Two-Tone Intermodulation
Distortion
IMD f
IN1
= 7.028MHz, f
IN2
= 8.093MHz (Note 4) -77 dBc
Differential Gain DG ±1%
Differential Phase DP
Degrees
ANALOG INPUTS (INP, INN, CML)
Input Resistance R
IN
Either input to ground 61 kΩ
Input Capacitance C
IN
Either input to ground 4 pF
Common-Mode Input Level
(Note 5)
V
CML
V
AV DD
✕
0.5
V
SYMBOL
MIN TYP MAX
±0.5
15 ✕ 10
±.75
±0.1
±0.2
10.5
±0.25
- 4
- 6
MSOTC 3 ✕ 10
SINAD
External reference applied to REFIN, (Note 2)
-1.5
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 3
PARAMETER
CONDITIONS
UNITS
Common-Mode Input Voltage
Range (Note 5)
V
CML
V
Differential Input Range V
IN
V
INP
- V
INN
(Note 6)
V
Small-Signal Bandwidth
(Note 7)
MHz
Large-Signal Bandwidth
(Note 7)
MHz
Overvoltage Recovery OVR 1.5 ✕ FS input 1
Clock
cycles
INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)
Common-Mode Reference
Voltage
V
CML
At CML V
AVDD
✕ 0.5 V
Positive Reference Voltage V
REFP
At REFP
V
CML
V
Negative Reference Voltage V
REFN
At REFN
V
CML
V
Differential Reference Voltage V
DIFF
(Note 6)
V
Differential Reference
Temperature Coefficient
ppm/°C
EXTERNAL REFERENCE (V
REFIN
= 2.048V)
REFIN Input Resistance R
IN
(Note 8) 5 kΩ
REFIN Input Capacitance C
IN
10 pF
REFIN Reference Input Voltage
Range
2.048
V
Differential Reference Voltage
Range
V
DIFF
(Note 6)
0.92
✕
1.08
✕
V
EXTERNAL REFERENCE (V
REFIN
= 0, reference voltage applied to REFP, REFN, and CML)
REFP, REFN, CML Input Current
I
IN
200 µA
REFP, REFN, CML Input
Capacitance
C
IN
15 pF
Differential Reference Voltage
Range
V
DIFF
(Note 6)
1.024
V
CML Input Voltage Range V
CML
1.65
V
REFP Input Voltage Range V
REFP
V
CML
+
V
DIFF
/2
V
REFN Input Voltage Range V
REFN
V
CML
-
V
DIFF
/2
V
DIGITAL INPUTS (CLK, CLK, PD, OE)
Input Logic High V
IH
0.7
✕
V
DVDD
V
Input Logic Low V
IL
V
DVD
V
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dBFS, internal reference, f
CLK
= 20MHz (50%
duty cycle); digital output load C
L
= 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Typical values are at T
A
= +25°C.)
SYMBOL
V
CMVR
BW
-3dB
FPBW
-3dB
REFTC ±100
MIN TYP MAX
±5%
±V
DIFF
400
150
+ 0.512
- 0.512
1.024
±5%
V
REFIN
V
REFIN
-200
±10%
V
/2
REFIN
/2
±10%
±10%
V
REFIN
0.3
/2
✕
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
4 _______________________________________________________________________________________
PARAMETER
CONDITIONS
UNITS
CLK, CLK
PD -20 20
Input Current
OE -20 20
µA
Input Capacitance 10 pF
DIGITAL OUTPUTS (D0–D11)
Output Logic High V
OH
IOH = 200µA
V
D V DD
- 0.5
V
Output Logic Low V
OL
IOL = -200µA 0 0.5 V
Three-State Leakage -10 10 µA
Three-State Capacitance 2pF
POWER REQUIREMENTS
Analog Supply Voltage
3.3
V
Digital Supply Voltage
2.7 3.3
V
Analog Supply Current I
AVDD
39 46 mA
Analog Supply Current with
Internal Reference in Shutdown
V
REFIN
= 0 37 44 mA
Analog Shutdown Current PD = DV
DD
20 µA
Digital Supply Current I
DVDD
3mA
Digital Shutdown Current PD = DV
DD
20 µA
Power Dissipation P
DISS
Analog power dissipation
152 mW
Power-Supply Rejection Ratio PSRR (Note 9) ±1
mV/V
TIMING CHARACTERISTICS
Maximum Clock Frequency f
CLK
Figure 6 20
MHz
Clock High t
CH
Figure 6, clock period 50ns 25 ns
Clock Low t
CL
Figure 6, clock period 50ns 25 ns
Pipeline Delay (Latency) Figure 6 7
Clock
cycles
Aperture Delay t
AD
Figure 10 2 ns
Aperture Jitter t
AJ
Figure 10 2 ps
Data Output Delay t
OD
Figure 6 5 10 14 ns
Bus Enable Time t
BE
Figure 5 5 ns
Bus Disable Time t
BD
Figure 5 5 ns
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dBFS, internal reference, f
CLK
= 20MHz (50%
duty cycle); digital output load C
L
= 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Typical values are at T
A
= +25°C.)
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External 2.048V reference applied to REFIN.
Note 3: Internal reference disabled. V
REFIN
= 0, V
REFP
= 2.162V, V
CML
= 1.65V, and V
REFN
= 1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1422.
Note 6: V
DIFF
= V
REFP
- V
REFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: V
REFIN
is internally biased to 2.048V through a 10kΩ resistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in V
AVDD
, using the internal reference.
SYMBOL
MIN TYP MAX
±330
V
DVDD
V
AVDD
V
DVDD
3.138
137
3.465
3.63
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 5
-120
-60
-80
-100
-40
-20
0
04312 5678910
FFT PLOT (4096-POINT DATA RECORD)
MAX1422 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
HD2
HD3
fIN = 5.2235MHz
-120
-60
-80
-100
-40
-20
0
04312 5678910
FFT PLOT (4096-POINT DATA RECORD)
MAX1422 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 8.1637MHz
HD2
HD3
-120
-60
-80
-100
-40
-20
0
04312 5678910
FFT PLOT (4096-POINT DATA RECORD)
MAX1422 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 19.8051MHz
HD2
HD3
-120
-60
-80
-100
-40
-20
0
04312 5678910
TWO-TONE IMD PLOT
(4096-POINT DATA RECORD)
MAX1422 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
IMD2
IMD3
f
IN2
f
IN1
f
IN1
= 7.0283MHz
f
IN2
= 8.0931MHz
f
CLK
= 20.0056MHz
A
IN1
= A
IN2
= -6.5dB FS
85
45
110100
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
53
MAX1422 toc05
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
61
69
77
70
50
110100
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
54
MAX1422 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
58
62
66
-50
-80
1 10 100
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
-74
MAX1422 toc07
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
-68
-62
-56
70
50
110100
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
54
MAX1422 toc08
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
58
62
66
20
40
30
60
50
70
80
-60 -40 -30-50 -20 -10 0
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (f
IN
= 5MHz)
MAX1422 toc09
ANALOG INPUT POWER (dB FS)
SFDR (dBc)
10
0
Typical Operating Characteristics
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input drive, AIN= -0.5dBFS, f
CLK
= 20MHz (50% duty
cycle) digital output load CL= 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25 °C.)
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
6 _______________________________________________________________________________________
0
20
40
60
80
100
-60 -40-50 -30 -20 -10 0
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (f
IN
= 5MHz)
MAX1422 toc10
ANALOG INPUT POWER (dB FS)
SNR (dB)
-80
-70
-30
-40
-20
-10
-60 -40-50 -30 -20 -10 0
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER (f
IN
= 5MHz)
MAX1422 toc11
ANALOG INPUT POWER (dB FS)
THD (dBc)
-50
-60
0
60
50
70
80
-60 -40-50 -30 -20 -10 0
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER (f
IN
= 5MHz)
MAX1422 toc12
ANALOG INPUT POWER (dB FS)
SINAD (dB)
20
10
30
40
64
68
76
72
80
84
-40 10-15 35 60 85
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
MAX1422 toc13
TEMPERATURE (°C)
SFDR (dBc)
fIN = 5.5224MHz
60
62
66
64
68
70
-40 10-15 35 60 85
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
MAX1422 toc14
TEMPERATURE (°C)
SNR (dB)
fIN = 5.5224MHz
-77
-75
-71
-73
-69
-67
-40 10-15 35 60 85
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
MAX1422 toc15
TEMPERATURE (°C)
THD (dBc)
fIN = 5.5224MHz
60
62
66
64
68
70
-40 10-15 35 60 85
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
MAX1422 toc16
TEMPERATURE (°C)
SINAD (dB)
fIN = 5.5224MHz
2
1
0
-1
-2
0 20481024 3072 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1422 toc17
DIGITAL OUTPUT CODE
INL (LSB)
0.50
0.25
0
-0.25
-0.50
020481024 3072 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1422 toc18
DIGITAL OUTPUT CODE
DNL (LSB)
Typical Operating Characteristics (continued)
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input drive, AIN= -0.5dBFS, f
CLK
= 20MHz (50% duty
cycle) digital output load CL= 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25 °C.)
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 7
0.5
0.2
-0.1
-0.4
-0.7
-40 10-15 356085
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (V
REFIN
= 2.048V)
MAX1422 toc19
TEMPERATURE (°C)
GAIN ERROR (%FSR)
-1.0
50
46
42
38
34
-40 10-15 356085
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1422 toc20
TEMPERATURE (°C)
I
AVDD
(mA)
30
6
5
4
3
2
-40 10-15 356085
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1422 toc21
TEMPERATURE (°C)
I
DVDD
(mA)
CL = 10pF
1
0
50
60
55
70
65
75
80
5.0 10.0 12.57.5 15.0 17.5 20.0
SNR/SINAD, THD/SFDR
vs. CLOCK FREQUENCY
MAX1422 toc22
CLOCK FREQUENCY (MHz)
SNR/SINAD, THD/SFDR (dB, dBc)
45
40
fIN = 5MHz
SINAD
THDSFDR
SNR
2.05
2.04
2.03
2.02
2.01
3.1 3.33.2 3.4
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1422 toc23
VDD (V)
V
REFIN
(V)
3.5
2.00
2.00
2.02
2.06
2.04
2.08
2.10
-40 10-15 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1422 toc24
TEMPERATURE (°C)
V
REFIN
(V)
0
10,000
5000
20,000
15,000
25,000
30,000
N-1
N+2
OUTPUT NOISE HISTOGRAM (DC-INPUT)
MAX1422 toc25
DIGITAL OUTPUT NOISE
COUNTS
N-4
N-3
N
N+1
N+3
27360
16623
3431
15029
162
22
1
2596
2
310
N-2
N+4
N+5
Typical Operating Characteristics (continued)
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input drive, AIN= -0.5dBFS, f
CLK
= 20MHz (50% duty
cycle) digital output load CL= 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25 °C.)
MAX1422
Detailed Description
The MAX1422 uses a 12-stage, fully differential,
pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle. Including the delay through the
output latch, the latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two and the product is
passed along to the next pipeline stage. This process
is repeated until the signal has been processed by all
12 stages. Each stage provides a 1-bit resolution.
Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no
missing codes.
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 4, 5, 8, 9,
12, 13, 16,
19, 41, 48
AGND Analog Ground. Connect all return paths for analog signals to AGND.
2, 3, 10, 11,
14, 15, 20,
42, 47
AV
DD
Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel
combination of a 0.1µF, and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between AV
DD
and AGND.
6 INP Positive Analog Signal Input
7 INN Negative Analog Signal Input
17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 20MHz.
18 CLK
Complementary Clock Frequency Input. This input is used for differential clock input. If the ADC is
driven with a single-ended clock, bypass CLK with 0.1µF capacitor to AGND.
21, 31, 32 DV
DD
Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel
combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between DVDD and DGND.
22, 29, 30 DGND Digital Ground
23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB.
39 OE
Output Enable Input. A logic "1" on OE places the outputs D0–D11 into a high-impedance state. A
logic "0" allows for the data bits to be read from the outputs.
40 PD Shutdown Input. A logic "1" on PD places the ADC into shutdown mode.
43 REFIN
External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
44 REFP
Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF.
With the internal reference disabled (REFIN = AGND), REFP should be biased toV
CML
+ V
DIFF
/2.
45 REFN
Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to
V
CML
- V
DIFF
/2.
46 CML
Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. With the internal reference disabled (REFIN = AGND), CML accepts an external voltage of
1.65V ±10%.
Input Track-and-Hold
Transconductance Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through-switches (S4a and S4b). Switches S2a
and S2b set the common mode for the transconductance amplifier (OTA) input and open simultaneously
with S1, sampling the input waveform. The resulting
differential voltage is held on capacitors C2a and C2b.
Switches S4a and S4b, are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the
output of the amplifier, and switch S4c is closed. The
OTA is used to charge capacitors, C1a and C1b, to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and isolates
the pipeline from the fast-changing input. The wide input
bandwidth, T/H amplifier allows the MAX1422 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs INP and INN can be
driven either differentially or single-ended. Match the
impedance of INP and INN and set the common-mode
voltage to midsupply (AVDD/2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1422 is determined by the
internally generated voltage difference between REFP
(AVDD/2 + V
REFIN
/4) and REFN (AVDD/2 - V
REFIN
/4). The
MAX1422’s full-scale range is adjustable through REFIN,
which provides a high input impedance for this purpose.
REFP, CML (AVDD/2), and REFN are internally buffered,
low impedance outputs.
The MAX1422 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the on-chip 2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN, left floating. For stability purposes bypass
REFIN, REFP, REFN, and CML with a capacitor network
of 0.22µF, in parallel with a 1nF capacitor to AGND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 9
T/H
V
OUT
x2
Σ
FLASH
ADC
DAC
2 BITS
MDAC
12
V
IN
V
IN
STAGE 1 STAGE 2
D11–D0
DIGITAL CORRECTION LOGIC
STAGE 12
TO NEXT
STAGE
Figure 1. Pipelined Architecture
S3b
S3a
CML
S5bS2b
S5a
IN+
IN-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
OTA
INTERNAL
BIAS
CML
S2a
Figure 2. Internal T/H Circuit
MAX1422
these nodes become high impedance and can be driven
by external reference sources, as shown in Figure 3.
Clock Inputs (CLK,
CLK
)
The MAX1422’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter would limit the SNR
performance of the ADC according to the following
relationship:
where fINrepresents the analog input frequency, and
tAJis the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any analog or digital signal lines.
The MAX1422 clock input operates with a voltage
threshold set to AV
DD
/2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1422 clock input.
Output Enable (OE), Power-Down (PD) and
Output Data (D0–D11)
With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down.
All data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS logic compatible. There is a seven clockcycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF) to avoid
large digital currents that could feed back into the ana-
SNR
t
dB
IN AJ
=×
׃ ×
20
1
2
10
log
π
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
10 ______________________________________________________________________________________
MAX1422
REFIN
REFN
R
50Ω
R
R
R
R
1V
R
50Ω
50Ω
R
R
AV
DD
CML
0.1nF
0.22µF
0.1nF0.22µF
0.1nF0.22µF
AGND
AV
DD
4
MAX4284
MAX4284
REFP
AV
DD
2
AV
DD
4
AV
DD
2
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
log portion of the MAX1421, thereby degrading its
dynamic performance. The use of digital buffers (e.g.
74LVCH16244) on the digital outputs of the ADCs can
further isolate the digital outputs from heavy capacitive
loads. To further improve the MAX1422 dynamic performance, add small 100Ω series resistors to the digital
output paths, close to the ADC. Figure 5 displays the
timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1422
samples the analog input signal on the rising edge of
CLK (falling edge of CLK). and output data is valid
seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for levelshifting purposes. The input is buffered and then split
to a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associated with high-speed op amps. Select the R
ISO
and
CINvalues to optimize the filter performance and to suit
a particular application. For the application in Figure 7,
a R
ISO
of 50Ω is placed before the capacitive load to
prevent ringing and oscillation. The 22pF CINcapacitor
acts as a small bypassing capacitor.Connecting C
IN
from INN to INP may further improve dynamic performance.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended signal to a fully differential signal, required by the MAX1422 for optimum
performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a 1:2 or 1:4
step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1422 provides better SFDR and
THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to singleended mode.
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
______________________________________________________________________________________ 11
D11–D0
10kΩ
10kΩ
10kΩ
10kΩ
A
VDD
ADC
CLK
CLK
INN
INP
AGND
MAX1422
Figure 4. Simplified Clock Input Circuit
OUTPUT
DATA D11–D0
OE
t
BD
t
BE
HIGH-ZHIGH-Z
VALID DATA
Figure 5. Output Enable Timing
DIFFERENTIAL
INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET BINARY
V
REF
✕
2047/2048
+FULL SCALE -
1LSB
1111 1111 1111
V
REF
✕
2046/2048
+FULL SCALE -
2LSB
1111 1111 1110
V
REF
✕ 1/2048 +1 LSB 1000 0000 0001
0 Bipolar Zero 1000 0000 0000
-V
REF
✕
1/2048
-1 LSB 0111 1111 1111
-V
REF
✕
2046/2048
-FULL SCALE
+1 LSB
0000 0000 0001
-V
REF
✕
2047/2048
-FULL SCALE 0000 0000 0000
Table 1. MAX1422 Output Code For
Differential Inputs
*V
REF
= V
REFP
- V
REFN
MAX1422
Single-Ended, AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low
distortion to maintain the integrity of the input signal.
Grounding, Bypassing and
Board Layout
The MAX1422 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side of
the board as the ADC, using surface-mount devices for
minimum inductance. Bypass REFP, REFN, REFIN, and
CML with a parallel network of 0.22µF capacitors and
1nF to AGND. AVDDshould be bypassed with a similar
network of a 10µF bipolar capacitor in parallel with two
ceramic capacitors of 1nF and 0.1µF. Follow the same
rules to bypass the digital supply DVDDto DGND.
Multilayer boards with separate ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arrangement
to match the physical location of the analog ground
(AGND) and the digital output driver ground (DGND)
on the ADCs package. The two ground planes should
be joined at a single point such that the noisy digital
ground currents do not interfere with the analog ground
plane. Alternatively, all ground pins could share the
same ground plane if the ground plane is sufficiently
isolated from any noisy, digital systems ground plane
(e.g., downstream output buffer DSP ground plane).
Route high-speed digital signal traces away from sensitive analog traces, and remove digital ground and
power planes from underneath digital outputs. Keep all
signal lines short and free of 90 degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This
straight-line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1422 are measured using the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
12 ______________________________________________________________________________________
N - 7 N - 8
N
N - 6
N + 1
N - 5
N + 2
N - 4
N + 3
N - 3
N + 4
N - 2
N + 5
N - 1 N
N + 6 N + 7
7 CLOCK-CYCLE LATENCY
ANALOG INPUT
DATA OUTPUT
t
DO
t
CH
t
CL
CLK
CLK
Figure 6. System and Output Timing Diagram
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical,
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-Bits):
SNR
(MAX)
= (6.02 ✕N + 1.76)dB
In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock
jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADCs error consists of quantization noise only. ENOB is
computed from:
ENOB
SINAD
=
-176
602..
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
______________________________________________________________________________________ 13
INPUT
300Ω
-5V
5V
0.1µF
0.1µF
0.1µF
C
IN
*
22pF
C
IN
*
22pF
1nF0.22µF
44pF*
R
ISO
50Ω
R
ISO
50Ω
-5V
600Ω
300Ω
300Ω
INP
INN
LOWPASS FILTER
CML
600Ω
5V
-5V
0.1µF
300Ω
300Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
5V
0.1µF
300Ω
MAX4108
MAX1422
MAX4108
MAX4108
LOWPASS FILTER
*TWO C
IN
(22pF) CAPS MAY BE REPLACED BY
ONE 44pF CAP, TO IMPROVE PERFORMANCE.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
MAX1422
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale.
THD
VVVV
V
=×
+++
20
10
2
2
3
2
4
2
5
2
1
log
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
14 ______________________________________________________________________________________
MAX1422
1nF
1kΩ
100Ω
100Ω
C
IN
22pF
CML
C
IN
22pF
INP
INN
0.1µF
R
ISO
50Ω
R
ISO
50Ω
0.22µF
V
IN
MAX4108
Figure 9. Single-Ended AC-Coupled Input
MAX1422
T1
N.C.
V
IN
6
1
5
2
43
22pF
22pF
1nF
0.1µF
0.22µF
25Ω
25Ω
MINICIRCUITS
T1–1T–KK81
INN
INP
CML
44pF
*
*
*
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN
INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 8. Using a Transformer for AC-Coupling
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLK
CLK
Figure 10. T/H Aperature Timing
CLK
INP
INTERFACE
PIPELINE ADC
OUTPUT
DRIVERS
REFIN REFP CML REFN OE
AV
DD
AGND
DV
DD
DGND
D11–D0
INN
PD
T/H
MAX1422
BANDGAP
REFERENCE
CLK
REF SYSTEM +
BIAS
Functional Diagram
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
32L/48L,TQFP.EPS
E
1
2
21-0054
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
E
2
2
21-0054
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
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