The MAX1407/MAX1408/MAX1409/MAX1414 are lowpower, general-purpose, multichannel data-acquisition
systems (DAS). These devices are optimized for lowpower applications. All the devices operate from a single +2.7V to +3.6V power supply and consume a
maximum of 1.15mA in Run mode and only 2.5µA in
Sleep mode.
The MAX1407/MAX1408/MAX1414 feature a differential
8:1 input multiplexer to the ADC, a programmable
three-state digital output, an output to shutdown an
external power supply, and a data ready output from
the ADC. The MAX1408 has eight auxiliary analog
inputs, while the MAX1407/MAX1414 include four auxiliary analog inputs and two 10-bit force/sense DACs.
The MAX1414 features a 50mV trip threshold for the
signal-detect comparator while the others have a 0mV
trip threshold. The MAX1409 is a 20-pin version of the
DAS family with a differential 4:1 input multiplexer to the
ADC, one auxiliary analog input, and one 10-bit
force/sense DAC.
The MAX1407/MAX1408/MAX1414 are available in
space-saving 28-pin SSOP packages, while the
MAX1409 is available in a 20-pin SSOP package.
Applications
Medical Instruments
Industrial Control Systems
Portable Equipment
Data-Acquisition System
Automatic Testing
Robotics
Features
♦ +2.7V to +3.6V Supply Voltage Range in Standby,
Idle, and Run Mode (Down to 1.8V in Sleep Mode)
♦ 1.15mA Run Mode Supply Current
♦ 2.5µA Sleep Mode Supply Current (Wake-Up, RTC,
and Voltage Monitor Active)
♦ Multichannel 16-Bit Sigma-Delta ADC
±1.5 LSB (typ) Integral Nonlinearity
30Hz or 60Hz Continuous Conversion Rate
Buffered or Unbuffered Mode
Gain of +1/3, +1, or +2V/V
Unipolar or Bipolar Mode
On-Chip Offset Calibration
♦ 10-Bit Force/Sense DACs
♦ Buffered 1.25V, 18ppm/°C (typ) Bandgap
Reference Output
♦ SPI™/QSPI™ or MICROWIRE™-Compatible Serial
Interface
♦ System Support Functions
RTC (Valid til 9999) and Alarm
High-Frequency PLL Clock Output (2.4576MHz)
+1.8V and +2.7V RESET and Power-Supply
Voltage Monitors
Signal Detect Comparator
Interrupt Generator (INT and DRDY)
Three-State Digital Output
Wake-Up Circuitry
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND .........................................................-0.3V to +6V
AV
DD
to DVDD...................................................... -0.3V to +0.3V
Analog Inputs to AGND .........................-0.3V to +(AV
DD
+ 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
Maximum Current Input Into Any Pin ..................................50mA
(DVDD= AVDD= +2.7V to 3.6V, 4.7µF at REF, internal V
REF
, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and
CLKOUT, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Power-Supply Rejection RatioGain = 1, unipolar and buffered mode70dB
Output Update Rate
Turn-On TimeExcluding reference50µs
SIGNAL DETECT COMPARATOR
Differential Input-Detection
Threshold Voltage
Common-Mode Input Voltage
Turn-On Time10µs
ANALOG INPUTS
Differential Input Voltage Range
Absolute Input Voltage Range
Common-Mode Input Voltage
Range
Common-Mode Rejection RatioGain = 1, unipolar and buffered mode90dB
Input Sampling RateFOUT = 2.4576MHz
Input CurrentBuffered mode±0.5nA
Input Capacitance15pF
F O R C E- SEN SE D A C ( al l m easur em ents m ad e w i th FB1( 2) shor ted to O U T1( 2) , unl ess other w i se noted ) .
( M AX 1407/M AX 1409/M AX 1414 onl y)
Note 1: Single conversion.
Note 2: DNL and INL are measured between code 010hex and 3FFhex.
Note 3: Offset error is referenced to code 010hex.
Note 4: Output swing is a function of external gain-setting feedback resistors and REF voltage.
Note 5: Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DV
DD
.
Note 6: SHDN stays high if the PLL is on.
Note 7: Actual worst-case performance is ±2.5LSB. Guaranteed limit of ±3.5LSB is due to production test limitation.
Note 8: Guaranteed by design. Not production tested.
The delay for the sleep voltage monitor
output, RESET, to go high after AV
above the reset threshold (+1.8V when bit
VM = 1 and +2.7V, when bit VM = 0); this is
largely driven by the startup of the 32kHz
oscillator
Minimum pulse width required to detect a
wake-up event
The delay for SHDN to go high after a valid
wake-up event
The turn-on time for the high-frequency
clock; it is gated by an AND function with
three signals—the RESET signal, the internal
low voltage V
assertion of the PLL; the time delay is timed
from when the low-voltage monitor trips or
the RESET going high, whichever happens
later; FOUT always starts in the low state
monitor signal, and the
DD
DD
rises
100µs
1.54s
1µs
1µs
31.25ms
The delay for INT to go low after the FOUT
INT Delayt
FOUT Disable Delayt
SHDN Assertion Delayt
DFI
DFOF
DPD
clock output has been enabled; INT is used
as an interrupt signal to inform the µP the
high-frequency clock has started
The delay after a shutdown command has
asserted and before FOUT is disabled; this
gives the microcontroller time to clean up
and go into Sleep mode properly
The delay after a shutdown command has
asserted and before SHDN is pulled low
(turning off the DC-DC converter) (Note 6)
7.82ms
1.95ms
2.93ms
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
—1—IN7Analog Input. Analog input to the negative mux only.
—— 1FB1Force/Sense DAC1 Feedback Input
22—D0Digital Output. Three-state general-purpose digital output.
3——FB1Force/Sense DAC1 Feedback Input
—3—IN6Analog Input. Analog input to the negative mux only.
4—2OUT1Force/Sense DAC1 Output
—4—IN4Analog Input. Analog input to the positive mux only.
553IN0Analog Input. Analog input to both the positive and negative mux.
664REF
775AGND
886AVDDAnalog Supply Voltage
997CPLL
10108WU1
11119WU2
MAX1408MAX1409PINFUNCTION
1.25V Reference Buffer Output/External Reference Input. Reference voltage
for the ADC and the DAC. Connect a 4.7µF capacitor to REF between REF
and AGND.
Analog Ground. Reference point for the analog circuitry. AGND connects to
the IC substrate.
PLL Capacitor Connection Pin. Connect an 18nF ceramic capacitor between
CPLL and AV
Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from
Sleep mode to Standby mode when WU1 is asserted.
Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from
Sleep mode to Standby mode when WU2 is asserted.
DD
.
Active-Low RESET Output. It remains low while AV
121210RESET
1313—IN1Analog Input. Analog input to both the positive and negative mux.
1414—IN2Analog Input. Analog input to both the positive and negative mux.
1515—SHDNProgrammable Shutdown Output. Goes low in Sleep mode.
1616—DRDY
171711FOUT2.4576MHz Clock Output. FOUT can be used to drive the input clock of a µP.
181812CLKOUT
191913CLKIN32kHz Crystal Input. Connect a 32kHz crystal between CLKIN and CLKOUT.
and stays low for a timeout period after AV
RESET is an open-drain output.
Active-Low Data Ready Output. A logic low indicates that a new conversion
result is available in the Data register. DRDY returns high upon completion of
a full output word read operation. DRDY also signals the end of an ADC
offset-calibration.
32kHz Crystal Output. Connect a 32kHz crystal between CLKIN and
CLKOUT.
The MAX1407/MAX1408/MAX1409/MAX1414 are lowpower, general-purpose, multichannel DAS featuring a
multiplexed fully differential 16-bit ∑∆ analog-to-digital
converter (ADC), 10-bit force/sense digital-to-analog
converters (DAC), a real-time clock (RTC) with an
alarm, a bandgap voltage reference, a signal detect
comparator, two power-supply voltage monitors, wakeup control circuitry, and a high-frequency phase-locked
loop (PLL) clock output all controlled by a 3-wire serial
interface. (See Table 1 for the MAX1407/MAX1408/
MAX1409/MAX1414 feature sets and Figures 1, 2, 3 for
the Functional Diagrams). These DAS directly interface
to various sensor outputs and once configured provide
the stimulus, conditioning, and data conversion, as well
as microprocessor support. Figure 4 is a TypicalApplication Circuit for the MAX1407/MAX1414.
The 16-bit ∑∆ ADC is capable of programmable continuous conversion rates of 30Hz or 60Hz and gains of
1/3, 1, and 2V/V to suit applications with different power
and dynamic range constraints. The force/sense DACs
provide 10-bit linearity for precise sensor applications.
252519DGNDDigital Ground. Reference point for digital circuitry.
262620DV
2727—IN3Analog Input. Analog input to both the positive and negative mux.
28——OUT2Force/Sense DAC2 Output
—28—IN5Analog Input. Analog input to the positive mux only.
MAX1408MAX1409PINFUNCTION
Active-Low Interrupt Output. INT goes low when the PLL output is ready,
when the signal-detect comparator is tripped, or when the alarm is triggered.
Serial Data Output. DOUT outputs serial data from the internal shift register
on SCLK’s falling edge. When CS is high, DOUT is three-stated.
Serial Data Input. Data on DIN is written to the input shift register and is
clocked in at SCLK’s rising edge when CS is low.
Serial Clock Input. Apply an external serial clock to transfer data to and from
the device. This serial clock can be continuous, with data transmitted in a
train of pulses, or intermittent while CS is low.
Active-Low Chip-Select Input. CS is used to select the active device in
systems with more than one device on the serial bus. Data will not be
clocked into DIN unless CS is low. When CS is high, DOUT is three-stated.
DD
Digital Supply Voltage
ADC
PART
MAX140742Yes0YesYesYes8
MAX141442Yes50YesYesYes8
MAX140880Yes0YesYesYes8
MAX140911No0YesNoNo4
AUXILIARY
ANALOG
INPUTS
FORCE/
SENSE
DAC
THREE-
STATE
DIGITAL
OUTPUT
COMPARATOR
THRESHOLD
(mV)
EXTERNAL
RTC
ADC DATA
READY
(DRDY)
POWERSUPPLY
SHUTDOWN
CONTROL
DIFFERENTIAL
INPUT MUX
ADC
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