Maxim MAX1402EAI, MAX1402CAI Datasheet
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General Description
The MAX1402 low-power, multichannel, serial-output
analog-to-digital converter (ADC) features matched
200µA current sources for sensor excitation. This ADC
uses a sigma-delta modulator with a digital decimation
filter to achieve 16-bit accuracy. The digital filter’s userselectable decimation factor allows the conversion resolution to be reduced in exchange for a higher output
data rate. True 16-bit performance is achieved at an
output data rate of up to 480sps. In addition, the modulator sampling frequency may be optimized for either
lowest power dissipation or highest throughput rate.
The MAX1402 operates from a +5V supply.
This device offers three fully differential input channels
that may be independently programmed with a gain
between +1V/V and +128V/V. Furthermore, it can compensate an input-referred DC offset up to 117% of the
selected full-scale range. These three differential channels may also be configured to operate as five pseudodifferential input channels. Two additional, fully
differential system-calibration channels are provided for
gain and offset error correction.
The MAX1402 may be configured to sequentially scan all
signal inputs and provide the results via the serial interface with minimum communications overhead. When
used with a 2.4576MHz or 1.024MHz master clock, the
digital decimation filter can be programmed to produce
zeros in its frequency response at the line frequency and
associated harmonics, ensuring excellent line rejection
without the need for further post-filtering.
The MAX1402 is available in a 28-pin SSOP package.
Applications
Portable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers
Features
♦ 18-Bit Resolution, Sigma-Delta ADC
♦ 16-Bit Accuracy with No Missing Codes to 480sps
♦ Low Quiescent Current
250µA (operating mode)
2µA (power-down mode)
♦ Matched On-Board Current Sources (200µA) for
Sensor Excitation
♦ 3 Fully Differential or 5 Pseudo-Differential Signal
Input Channels
♦ 2 Additional, Fully Differential Calibration
Channels/Auxiliary Input Channels
♦ Programmable Gain and Offset
♦ Fully Differential Reference Inputs
♦ Converts Continuously or On Command
♦ Automatic Channel Scanning and Continuous
Data Output Mode
♦ Operates with +5V Analog Supply and +3V or +5V
Digital Supply
♦ 3-Wire Serial Interface—SPI™/QSPI™ Compatible
♦ 28-Pin SSOP Package
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
________________________________________________________________
Maxim Integrated Products
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCLK
DIN
DOUT
INT
V
DD
DGND
AIN5
CALOFF+
CALOFFREFIN+
REFINCALGAIN+
CALGAINAIN6
AIN4
AIN3
AIN2
AIN1
V+
AGND
OUT1
OUT2
DS0
DS1
RESET
CS
CLKOUT
CLKIN
SSOP
TOP VIEW
MAX1402
PART
MAX1402CAI
MAX1402EAI -40°C to +85°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
28 SSOP
28 SSOP
Pin Configuration
Ordering Information
EVALUATION KIT
AVAILABLE
SPI and QSPI are trademarks of Motorola, Inc.
19-1423; Rev 0; 3/99
%FSR
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to AGND, DGND.................................................-0.3V to +6V
V
DD
to AGND, DGND...............................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
Analog Inputs to AGND................................-0.3V to (V+ + 0.3V)
Analog Outputs to AGND.............................-0.3V to (V+ + 0.3V)
Reference Inputs to AGND...........................-0.3V to (V+ + 0.3V)
CLKIN and CLKOUT to DGND...................-0.3V to (V
DD
+ 0.3V)
All Other Digital Inputs to DGND..............................-0.3V to +6V
All Digital Outputs to DGND.......................-0.3V to (V
DD
+ 0.3V)
Maximum Current Input into Any Pin ..................................50mA
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.52mW/°C above +70°C) ........524mW
Operating Temperature Ranges
MAX1402CAI .....................................................0°C to +70°C
MAX1402EAI...................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
µV/°C
For gains of 1, 2, 4
No missing codes guaranteed by design;
for filter settings with FS1 = 0
For gains of 1, 2, 4, 8, 16, 32, 64
For gain of 128
For gains of 1, 2, 4, 8, 16, 32, 64
For gain of 128
For gains of 1, 2, 4, 8, 16, 32, 64
For gain of 128
For gains of 1, 2, 4
For gains of 1, 2, 4, 8, 16, 32, 64
For gains of 8, 16, 32, 64, 128
For gains of 1, 2, 4
Depends on filter setting and selected gain
Bipolar mode, filter settings with FS1 = 0
Relative to nominal of 1% FSR
For gains of 8, 16, 32, 64, 128
CONDITIONS
0.8
%FSR
-2.5 2.5
Bipolar Negative Full-Scale Error
ppm/°C
5
Gain-Error Drift (Note 5)
1
%FSR
-3 3
Gain Error (Note 4)
-2 2
%FSR
-3.5 3.5
-2.5 2.5
Positive Full-Scale Error
(Note 2)
0.3
Bipolar Zero Drift
Bits16Noise-Free Resolution
0.8
%FSR-2.0 2.0Bipolar Zero Error
µV/°C
0.3
Unipolar Offset Drift
0.5
Table 16Output Noise
%FSR-0.0015 0.0015INLIntegral Nonlinearity
0.98Nominal Gain (Note 1)
%FSR-1 2Unipolar Offset Error
UNITSMIN TYP MAXSYMBOLPARAMETER
For gains of 8, 16, 32, 64, 128
µV/°C
0.3
Bipolar Negative Full-Scale Drift
For gains of 8, 16, 32, 64, 128
For gains of 1, 2, 4
µV/°C
0.3
0.8
Full-Scale Drift (Note 3)
For gain of 128 -3.5 3.5
STATIC PERFORMANCE
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C.)
BUFF = 0
BUFF = 1
Bipolar mode
REFIN and AIN for
BUFF = 0
BUFF = 1
Unipolar mode
REFIN and AIN for BUFF = 0
REFIN and AIN for BUFF = 0
For filter notch 60Hz, ±0.02 · f
NOTCH
,
MF1 = 0, MF0 = 0, f
CLKIN
= 2.4576MHz
For filter notch 50Hz, ±0.02 · f
NOTCH
,
MF1 = 0, MF0 = 0, f
CLKIN
= 2.4576MHz
At DC
For filter notch 60Hz, ±0.02 · f
NOTCH
,
MF1 = 0, MF0 = 0, f
CLKIN
= 2.4576MHz (Note 8)
DAC code = 0000
Unipolar mode
Bipolar mode
Input Referred
For filter notch 50Hz, ±0.02 · f
NOTCH
,
MF1 = 0, MF0 = 0, f
CLKIN
= 2.4576MHz (Note 8)
CONDITIONS
pF
34
AIN Input Capacitance
(Notes 11)
nA10AIN Input Current (Note 10)
nA10
pA40
DC Input Leakage Current
(Note 10)
V
V
AGND
V+
+ 200mV - 1.5
Absolute and Common-Mode
AIN Voltage Range
V
V
AGND
V+
- 30mV + 30mV
Absolute Input Voltage Range
dBV
AGND
V+
Common-Mode Voltage Range
(Note 9)
dB100NMR
Normal Mode 60Hz Rejection
(Note 8)
dB100NMR
Normal Mode 50Hz Rejection
(Note 8)
150
150
-58.35 58.35
%FSR
-116.7 116.7
Offset DAC Range (Note 6)
dB
90
CMRCommon-Mode Rejection
µV
RMS
0
Additional Noise from Offset
DAC (Note 7)
%FSR
16.7
Offset DAC Resolution
8.35
%FSR-2.5 2.5Offset DAC Full-Scale Error
%FSR0Offset DAC Zero-Scale Error
UNITSMIN TYP MAXSYMBOLPARAMETER
TA= +25°C
TA= T
MIN
to T
MAX
38
45
60
BUFF = 1, all gains 30
Unipolar input range (U/B bit = 1)
V
0 to V
REF
/ gain
AIN Differential Voltage Range
(Note 12)
Bipolar input range (U/B bit = 0)
±V
REF
/ gain
Gain = 1
Gain = 2
Gain = 4
Gain = 8, 16, 32, 64, 128
OFFSET DAC
ANALOG INPUTS/REFERENCE INPUTS (Specifications for AIN and REFIN, unless otherwise noted.)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
4 _______________________________________________________________________________________
CONDITIONS
Hz(Table 15)f
S
AIN and REFIN Input Sampling
Frequency
UNITSMIN TYP MAXSYMBOLPARAMETER
0.8
0.8
All inputs except
CLKIN
0.4
µA-10 +10I
IN
Input Current
200
CLKIN only
All inputs except
CLKIN
mV
200
V
HYS
Input Hysteresis
VV
OL
Output Low Voltage (Note 14)
pF9
DOUT
and INT
C
O
Floating-State Output
Capacitance
µA-10 10I
L
Floating-State Leakage Current
0.4
V
0.4
V
IL
Input Low Voltage
±5% for specified performance; functional
with lower V
REF
V2.50
REFIN+ - REFIN- Voltage
(Note 13)
VDD= 5V
VDD= 3.3V
VDD= 5V
VDD= 3.3V
VDD= 5V
VDD= 3.3V
VDD= 5V
VDD= 3.3V
2
3.5
All inputs except
CLKIN
2
CLKIN only
V
2.4
V
IH
Input High Voltage
VDD= 5V
VDD= 3.3V
µA0.1I
BO
Current
%±10Initial Tolerance
%/°C±0.05Drift
VDD= 5V, I
SINK
= 800µA
VDD= 3.3V, I
SINK
= 100µA
VDD= 5V, I
SINK
= 10µA
VDD= 3.3V, I
SINK
= 10µA
CLKOUT 0.4
VDD= 5V, I
SOURCE
= 200µA
VDD= 3.3V, I
SOURCE
= 100µA
VV
OH
Output High Voltage (Note 14)
DOUT
and INT
4
VDD- 0.3
µA200I
EXC
Current
%15Initial Tolerance
ppm/°C100Drift
OUT1 to OUT2 %±1Match
ppm/°C5Drift Match
VV
AGND
V+ -1.0Compliance Voltage Range
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C.)
VDD= 5V, I
SOURCE
= 10µA
VDD= 3.3V, I
SOURCE
= 10µA
CLKOUT
4
VDD- 0.3
TRANSDUCER BURN-OUT (Note 15)
LOGIC OUTPUTS
LOGIC INPUTS
TRANSDUCER EXCITATION CURRENTS
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________ 5
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
370 420
Buffers off
Buffers off
Buffers on
Normal mode,
MF1 = 0,
MF0 = 0
610 700
250 300
Buffers on 610
Buffers on
2X mode,
MF1 = 0,
MF0 = 1
1.2 1.5
CONDITIONS
PD bit = 1, external clock stopped
0.42 0.55
245
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
1.2
Buffers off
Buffers off
Buffers on
4X mode,
MF1 = 1,
MF0 = 0
µA
4.8 6
110
1.8 2.2
Buffers on 4.8
Buffers on
8X mode,
MF1 = 1,
MF0 = 1
mA
4.8 6
I
V+
V+ Current
1.8 2.2
1.8
0.42
V+ Standby Current (Note 18)
0.08
70 200
2X mode,
MF1 = 0, MF0 = 1
0.17 0.35
0.13
Normal mode,
MF1 = 0, MF0 = 0
PD bit = 1, external clock stopped 110
150 300
µAVDDStandby Current (Note 18)
µA
115 300
2X mode,
MF1 = 0, MF0 = 1
1.024MHz
2.4576MHz
0.28 0.5
Normal mode,
MF1 = 0, MF0 = 0
1.024MHz
175 210
2.4576MHz
0.15
0.11
8X mode,
MF1 = 1, MF0 = 1
0.32 0.45
mA
4X mode,
MF1 = 1, MF0 = 0
0.22 0.40
235 450
µA
1.024MHz
1.024MHz
2.4576MHz
I
DD
3.3V Digital Supply Current
1.024MHz
2.4576MHz
2.4576MHz
1.024MHz
2.4576MHz
mA
I
DD
5V Digital Supply Current
UNITSMIN TYP MAXSYMBOLPARAMETER
µA
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C.)
For specified performance V4.75 5.25V+V+ Voltage
V2.7 5.25V
DD
VDDVoltage
dB(Note 17)PSR
Power-Supply Rejection V+
(Note 16)
ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and auxil-
iary currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
DIGITAL POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and auxiliary
currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
POWER REQUIREMENTS
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
6 _______________________________________________________________________________________
Note 1: Nominal gain is 0.98. This ensures a full-scale input voltage may be applied to the part under all conditions without caus-
ing saturation of the digital output data.
Note 2: Positive Full-Scale Error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges. This error does not include the nominal gain of 0.98.
Note 3: Full-Scale Drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar
input ranges.
Note 4: Gain Error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges
and as (full-scale error - bipolar zero error) for bipolar ranges. This error does not include the nominal gain of 0.98.
Note 5: Gain-Error Drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if zero-scale
error is removed.
Note 6: Use of the offset DAC does not imply that any input may be taken below AGND.
Note 7: Additional noise added by the offset DAC is dependent on the filter cutoff, gain, and DAC setting. No noise is added for a
DAC code of 0000.
Note 8: Guaranteed by design or characterization; not production tested.
Note 9: The absolute input voltage must be within the input-voltage range specification.
Note 10: All AIN and REFIN pins have identical input structures. Leakage is production tested only for the AIN3, AIN4, AIN5,
CALGAIN and CALOFF inputs.
Note 11: The dynamic load presented by the MAX1402 analog inputs for each gain setting is discussed in detail in the
Switching
Network
Section.Values are provided for the maximum allowable external series resistance.
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
2.43 3.6
Buffers off
Buffers off
Buffers on
Normal mode,
MF1 = 0,
MF0 = 0
4.23 5.75
2.43 3.75
Buffers on 3.7
Buffers on
2X mode,
MF1 = 0,
MF0 = 1
7.4 10
CONDITIONS
3.5 5.25
1.88
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
6.85
Buffers off
Buffers off
Buffers on
4X mode,
MF1 = 1,
MF0 = 0
25.8 33
10.8 14
Buffers on 25.2
Buffers on
8X mode,
MF1 = 1,
MF0 = 1
mW
26.7 34
PDPower Dissipation
11.7 15
10.2
2.95
(Note 18) 10 100 µWStandby Power Dissipation
1.45 2.55
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= T
MIN
to T
MAX
, unless other-
wise noted. Typical values are at T
A
= +25°C.)
4X mode,
MF1 = 1, MF0 = 0
mA
0.17
I
DD
5V Digital Supply Current
1.024MHz
2.4576MHz 0.36 0.6
8X mode,
MF1 = 1, MF0 = 1
0.241.024MHz
2.4576MHz 0.53 0.8
5V POWER DISSIPATION (V+ = VDD= +5V, digital inputs = 0 or VDD, external CLKIN, burn-out and auxiliary currents disabled,
X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________ 7
TIMING CHARACTERISTICS
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, AGND = DGND, f
CLKIN
= 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA= T
MIN
to T
MAX
,
unless otherwise noted.) (Notes 19, 20, 21)
0 100VDD= 3.3V
VDD= 5V
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
t
10
10 100
ns
VDD= 5V
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
t
6
080
ns
INT High Time
t
INT
560 / N
· t
CLKIN
ns
X2CLK = 1, N = 2
(2 · MF1 + MF0)
Crystal oscillator or clock externally supplied for specified performance (Notes 22, 23)
SCLK Setup to Falling Edge CS
t
4
30 ns
SCLK Low Pulse Width t
8
100 ns
10 70
SCLK Rising Edge to INT High
(Note 27)
t
11
100VDD= 5V
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 21)
t
9
0 ns
SCLK High Pulse Width t
7
100 ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t
5
30 ns
280 / N
· t
CLKIN
INT to CS Setup Time (Note 8)
t
3
X2CLK = 0, N = 2
(2 · MF1 + MF0)
0 ns
RESET Pulse Width Low
t
2
100 ns
Master Clock Input Low Time f
CLKIN LO
0.4 ·
t
CLKIN
nst
CLKIN
= 1 / f
CLKIN
, X2CLK = 0
Master Clock Input High Time f
CLKIN HI
0.4 ·
t
CLKIN
nst
CLKIN
= 1 / f
CLKIN
, X2CLK = 0
Master Clock Frequency f
CLKIN
0.8 5.0
MHz
PARAMETER SYMBOL MIN TYP MAX UNITS
0.4 2.5
CONDITIONS
200
ns
X2CLK = 0
X2CLK = 1
VDD= 3.3V
VDD= 3.3V
Note 12: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-
tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.
Note 13: V
REF
= V
REFIN+
- V
REFIN-
.
Note 14: These specifications apply to CLKOUT only when driving a single CMOS load.
Note 15: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate cor-
rectly.
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
30 nst
12
SCLK Setup to Falling Edge CS
SERIAL-INTERFACE READ OPERATION
SERIAL-INTERFACE WRITE OPERATION
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
8 _______________________________________________________________________________________
Note 19: All input signals are specified with tr= tf= 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 20: See Figure 4.
Note 21: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
SCLK idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently
tied low, the part should only be operated with SCLK idling high between accesses.
Note 22: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1402 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 23: The MAX1402 is production tested with f
CLKIN
at 2.5MHz (1MHz for some IDDtests).
Note 24: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or VOHlimits.
Note 25: For read operations, SCLK active edge is falling edge of SCLK.
Note 26: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 27: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
Note 28: Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
SCLK High Pulse Width t
16
100 ns
SCLK Low Pulse Width t
17
100 ns
Data Valid to SCLK Rising Edge
Hold Time
t
15
0 ns
PARAMETER SYMBOL MIN TYP MAX UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t
13
30 ns
Data Valid to SCLK Rising Edge
Setup Time
t
14
30 ns
CONDITIONS
TIMING CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, AGND = DGND, f
CLKIN
= 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA= T
MIN
to T
MAX
,
unless otherwise noted.) (Notes 19, 20, 21)
CS Rising Edge to SCLK Rising
Edge Hold Time
t
18
0 ns
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21 & 28)
t
20
0 ns
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21 & 28)
t
19
40 ns
800µA
at V
DD
= +5V
100µA
at VDD = +3.3V
TO
OUTPUT
PIN
50pF
200µA
at V
DD
= +5V
100µA
at VDD = +3.3V
Figure 1. Load Circuit for Bus-Relinquish Time and VOLand
V
OH
Levels
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________
9
0
50
100
150
200
250
021 345
OUT1 AND OUT2 COMPLIANCE
MAX1402 toc01
COMPLIANCE VOLTAGE (V)
OUTPUT CURRENT (µA)
-15
0
-5
-10
5
10
15
-2.5 -0.5-1.0-2.0 -1.5 0 0.5 1.0 1.5 2.0 2.5
INTEGRAL NONLINEARITY AT 480sps,
GAIN = 1 (262, 144 pts)
MAX1402 toc12
DIFFERENTIAL INPUT VOLTAGE (V)
INL (ppm)
-15
0
-5
-10
5
10
15
0 0.5 1.0 1.5 2.0 2.5
MAX1402 toc13
CODE (x105)
DNL (ppm)
DIFFERENTIAL NONLINEARITY AT 480sps,
GAIN = 1 (262, 144 pts)
0
100
50
200
150
300
250
350
-50 0 25-25 50 75 100
VDD SUPPLY CURRENT vs. TEMPERATURE
(20sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc02
TEMPERATURE (°C)
V
DD
SUPPLY CURRENT (µA)
VDD = +5.25V
V
DD
= +3.6V
(NOTE 29)
0
100
50
200
150
300
250
350
400
-50 0 25-25 50 75 100
V+ SUPPLY CURRENT vs. TEMPERATURE
(20sps OUTPUT DATA RATE)
MAX1402 toc07
TEMPERATURE (°C)
V+ SUPPLY CURRENT (µA)
BUFFERED
UNBUFFERED
0
100
50
200
150
300
250
350
-50 0 25-25 50 75 100
VDD SUPPLY CURRENT vs. TEMPERATURE
(60sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc03
TEMPERATURE (°C)
V
DD
SUPPLY CURRENT (µA)
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
0
100
50
200
150
300
250
350
-50 0 25-25 50 75 100
VDD SUPPLY CURRENT vs. TEMPERATURE
(120sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc04
TEMPERATURE (°C)
V
DD
SUPPLY CURRENT (µA)
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
0
200
100
400
300
600
500
-50 0 25-25 50 75 100
V+ SUPPLY CURRENT vs. TEMPERATURE
(60sps OUTPUT DATA RATE)
MAX1402 toc08
TEMPERATURE (°C)
V+ SUPPLY CURRENT (µA)
BUFFERED
UNBUFFERED
0
400
200
800
600
1200
1000
-50 0 25-25 50 75 100
V+ SUPPLY CURRENT vs. TEMPERATURE
(120sps OUTPUT DATA RATE)
MAX1402 toc09
TEMPERATURE (°C)
V+ SUPPLY CURRENT (µA)
BUFFERED
UNBUFFERED
Typical Operating Characteristics
(V+ = +5V, VDD= +5V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= +25°C, unless otherwise noted.)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
10 ______________________________________________________________________________________
0
100
50
250
200
150
400
350
300
450
-50 0-25 25 50 75 100
VDD SUPPLY CURRENT vs. TEMPERATURE
(240sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc05
TEMPERATURE (°C)
V
DD
SUPPLY CURRENT (µA)
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
0
200
100
400
300
600
500
-50 0 25-25 50 75 100
VDD SUPPLY CURRENT vs. TEMPERATURE
(480sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc06
TEMPERATURE (°C)
V
DD
SUPPLY CURRENT (µA)
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
0
2000
1000
4000
3000
5000
-50 0 25-25 50 75 100
V+ SUPPLY CURRENT vs. TEMPERATURE
(240sps OUTPUT DATA RATE)
MAX1402 toc10
TEMPERATURE (°C)
V+ SUPPLY CURRENT (µA)
BUFFERED
UNBUFFERED
0
2000
1000
4000
3000
5000
-50 0 25-25 50 75 100
V+ SUPPLY CURRENT vs. TEMPERATURE
(480sps OUTPUT DATA RATE)
MAX1402 toc11
TEMPERATURE (°C)
V+ SUPPLY CURRENT (µA)
BUFFERED
UNBUFFERED
Typical Operating Characteristics (continued)
(V+ = +5V, VDD= +5V, V
REFIN+
= +2.50V, REFIN- = AGND, f
CLKIN
= 2.4576MHz, TA= +25°C, unless otherwise noted.)
Note 29: Minimize capacitive loading at CLKOUT for lowest V
DD
supply current.
Typical Operating Characteristics
show V
DD
supply current with CLKOUT loaded by 120pF.
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________ 11
Pin Description
15 AIN5
Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6
(see
Communications Register
section).
NAME FUNCTION
1 CLKIN
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT unconnected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1.
PIN
2 CLKOUT
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.
3
CS
Chip-Select Input. Active-low logic input used to enable the digital interface. With CS hard-wired low, the
MAX1402 operates in its 3-wire interface mode with SCLK, DIN and DOUT used to interface to the device.
CS is used either to select the device in systems with more than one device on the serial bus, or as a
frame-synchronization signal for the MAX1402 when a continuous SCLK is used.
4
RESET
Active-Low Reset Input. Drive low to reset the control logic, interface logic, digital filter and analog modulator to power-on status. RESET must be high and CLKIN must be toggling in order to exit reset.
5 DS1
Digital Input for Auxiliary Data Input Bit 1. The status of this bit is reflected in the output data by bit D4.
Used to communicate the status of DS1 via the serial interface.
6 DS0
Digital Input for Auxiliary Data Input Bit 0. The status of this bit is reflected in the output data by bit D3.
Used to communicate the status of DS0 via the serial interface.
7 OUT2 Transducer Excitation Current Source 2
8 OUT1 Transducer Excitation Current Source 1
9 AGND Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.
10 V+ Analog Positive Supply Voltage (+4.75V to +5.25V).
11 AIN1
Analog Input Channel 1. May be used as a pseudo-differential input with AIN6 as common, or as the positive input of the AIN1/AIN2 differential analog input pair (see
Communications Register
section).
12 AIN2
Analog Input Channel 2. May be used as a pseudo-differential input with AIN6 as common, or as the negative input of the AIN1/AIN2 differential analog input pair (see
Communications Register
section).
13 AIN3
Analog Input Channel 3. May be used as a pseudo-differential input with AIN6 as common, or as the positive input of the AIN3/AIN4 differential analog input pair (see
Communications Register
section).
14 AIN4
Analog Input Channel 4. May be used as a pseudo-differential input with AIN6 as common, or as the negative input of the AIN3/AIN4 differential analog input pair (see
Communications Register
section).
16 AIN6
Analog Input 6. May be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see
Communications Register
section).
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
12 ______________________________________________________________________________________
Pin Description (continued)
NAME FUNCTIONPIN
17 CALGAIN-
Negative Gain Calibration Input. Used for system-gain calibration. It forms the negative input of a fully
differential input pair with CALGAIN+. Normally these inputs are connected to reference voltages in the
system. When system gain calibration is not required and the auto-sequence mode is used, the
CALGAIN+/CALGAIN- input pair provides an additional fully differential input channel.
18 CALGAIN+
Positive Gain Calibration Input. Used for system gain calibration. It forms the positive input of a fully differential input pair with CALGAIN-. Normally these inputs are connected to reference voltages in the system.
When system gain calibration is not required and the auto-sequence mode is used, the CALGAIN+/
CALGAIN- input pair provides an additional fully differential input channel.
19 REFIN-
Negative Differential Reference Input. Bias REFIN- between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.
20 REFIN+
Positive Differential Reference Input. Bias REFIN+ between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.
21 CALOFF-
Negative Offset Calibration Input. Used for system offset calibration. It forms the negative input of a fully
differential input pair with CALOFF+. Normally these inputs are connected to zero-reference voltages in
the system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.
22 CALOFF+
Positive Offset Calibration Input. Used for system offset calibration. It forms the positive input of a fully
differential input pair with CALOFF-. Normally these inputs are connected to zero-reference voltages in the
system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.
23 DGND Digital Ground. Reference point for digital circuitry.
24 V
DD
Digital Supply Voltage (+2.7V to +5.25V)
25
INT
Interrupt Output. A logic low indicates that a new output word is available from the data register. INT
returns high upon completion of a full output word read operation. INT also returns high for short periods
(determined by the filter and clock control bits) if no data read has taken place. A logic high indicates
internal activity, and a read operation should not be attempted under this condition. INT can also provide
a strobe to indicate valid data at DOUT (MDOUT = 1).
26 DOUT
Serial Data Output. DOUT outputs data from the internal shift register containing information from the
Communications Register, Global Setup Registers, Transfer Function Registers, or Data Register. DOUT
can also provide the digital bit stream directly from the Σ-∆ modulator (MDOUT = 1).
27 DIN
Serial Data Input. Data on DIN is written to the input shift register and later transferred to the
Communications Register, Global Setup Registers, Special Function Register, or Transfer Function
Registers, depending on the register selection bits in the Communications Register.
28 SCLK
Serial Clock Input. Apply an external serial clock to transfer data to and from the MAX1402. This serial
clock can be continuous, with data transmitted in a train of pulses, or intermittent. If CS is used to frame
the data transfer, then SCLK may idle high or low between conversions and CS determines the desired
active clock edge (see
Selecting Clock Polarity
). If CS is tied permanently low, SCLK must idle high
between data transfers.
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