The MAX1363/MAX1364 low-power, 12-bit, 4-channel
analog-to-digital converters (ADCs) feature a digitally
programmable window comparator with an interrupt output for automatic system-monitoring applications. Once
configured, monitor mode automatically asserts an interrupt when any analog input exceeds the programmed
upper or lower thresholds, without interaction to the
host. The MAX1363/MAX1364 respond to the SMBus™
alert, allowing quick identification of the alarming device
on a shared interrupt. A programmable delay between
monitoring intervals lowers power consumption for
reduced monitoring rates.
In addition, the MAX1363/MAX1364 integrate an internal voltage reference, a clock, and a 1.7MHz, highspeed, I2C™-compatible, 2-wire serial interface. The
optimized interface allows a maximum conversion rate
of 94.4ksps in normal mode while reading back the
conversion results. Each of the four analog inputs is
configurable for single-ended or fully differential operation and unipolar or bipolar operation. Two scan modes
utilize on-chip random access memory (RAM) to allow
eight conversions of a selected channel or scanning of
a group of channels to reduce interface overhead.
These devices operate from a single 2.7V to 3.6V
(MAX1363) or 4.5V to 5.5V (MAX1364) supply and
require only 436µA at the maximum sampling rate of
133ksps in monitor mode and 670µA at the maximum
sampling rate of 94.4ksps. AutoShutdown™ powers
down the devices between conversions, reducing supply current to less than 1µA when idle.
The full-scale analog-input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX1363 features
a 2.048V internal reference, and the MAX1364 features
a 4.096V internal reference.
The MAX1363/MAX1364 are available in a 10-pin
µMAX®package and are specified over the extended
(-40°C to +85°C) temperature range. For 10-bit applications, refer to the pin-compatible MAX1361/MAX1362
data sheet.
Applications
System Monitoring/Supervision
Servers/Workstations
High-Reliability Power Supplies
Medical Instrumentation
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
SMBus is a trademark of Intel Corporation.
I
2
C is a trademark of Philips Corporation. Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Typical Operating Circuit and Pin Configuration appear at
end of data sheet.
Ordering Information/Selector Guide continued at end of data sheet.
*Future product—contact factory for availability.
查询MAX1363供应商
PARTTEMP RANGEPIN-PACKAGEI2C SLAVE ADDRESSSUPPLY VOLTAGE (V)
MAX1363EUB-40°C to +85°C10 µMAX0110100/01101012.7 to 3.6
MAX1363LEUB*-40°C to +85°C10 µMAX0110010/01100112.7 to 3.6
MAX1363MEUB*-40°C to +85°C10 µMAX0110110/01101112.7 to 3.6
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
(VDD= 2.7V to 3.6V (MAX1363), VDD= 4.5V to 5.5V (MAX1364), V
REF
= 2.048V (MAX1363), V
REF
= 4.096V (MAX1364), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN3, A0, REF to GND......................-0.3V to (V
DD
+ 0.3V)
SDA, SCL, INT to GND.............................................-0.3V to +6V
Maximum Current Into Any Pin.........................................±50mA
Gain Error(Note 3)±4LSB
Gain Temperature CoefficientRelative to FSR0.3ppm/°C
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
DYNAMIC PERFORMANCE (f
Signal-to-Noise Plus DistortionSINAD70dB
Total Harmonic DistortionTHDUp to the 5th harmonic-78dB
Spurious-Free Dynamic RangeSFDR78dB
Full-Power BandwidthSINAD > 57dB3.0MHz
Full-Linear Bandwidth-3dB point5.0MHz
(VDD= 2.7V to 3.6V (MAX1363), VDD= 4.5V to 5.5V (MAX1364), V
REF
= 2.048V (MAX1363), V
REF
= 4.096V (MAX1364), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Devices configured for unipolar single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have
been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: The throughput rate of the I
2
C bus is limited to 94.4ksps. The MAX1363/MAX1364 can perform conversions up to 133ksps
in monitor mode when not reading back results on the I
2
C bus.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN3) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a
0.01µF capacitor.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10: Maximum conversion throughput in internal clock mode when the data is not clocked out.
Note 11: For the MAX1363, PSRR is measured as
and for the MAX1364, PSRR is measured as
Note 12: C
B
= total capacitance of one bus line in pF.
Note 13: f
SCLH
must meet the minimum clock low time plus the rise/fall times.
Note 14: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge.
(
)
VVVV
(. )(. )
3627
FSFS
[]
−
VV
(.. )
3627
−
N
21
−
×
V
REF
VVVV
(. )(. )
5545
FSFS
[]
−
VV
..
5545
−
×
N
21
−
V
REF
DNL (LSB)
-0.1
-0.2
-0.3
-0.4
-0.5
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
0.5
0.4
0.3
0.2
0.1
0
1000 1500500
04000
2000 2500
DIGITAL OUTPUT CODE
3000 3500
MAX1363/64 toc01
1.0
0.8
0.6
0.4
0.2
INL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
0
1000 1500500
04000
2000 2500
DIGITAL OUTPUT CODE
3000 3500
MAX1363/64 toc02
FFT PLOT
-60
f
= 94.4ksps
SAMPLE
= 10kHz
f
IN
-80
-100
-120
AMPLITUDE (dBc)
-140
-160
-180
01020304050
FREQUENCY (kHz)
MAX1363/64 toc03
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Analog Input or Reference Input or Output. See Table 3.
2
C Address Select Input. Connect to VDD or GND. See Table 1.
6INTActive-Low, Open-Drain Interrupt Output
7SCLI2C Clock Input
8SDAI2C Data Input/Output
9GNDGround
10V
DD
Positive Supply Voltage. Bypass V
to GND with a 0.1µF capacitor.
DD
V
DD
SDA
SCL
A0
INT
AIN0
AIN1
AIN2
AIN3/
REF
4:1
MUX
CLK
12-BIT
ADC
INT
REF
GND
I2C
INTERFACE
CONTROL
TRIP
THRESHOLDS
MAX1363/MAX1364
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