The MAX13335E/MAX13336E are high-fidelity stereo
audio input amplifiers designed for automotive applications requiring audio-level detection and/or jack sensing
capability.
The devices feature a dual-channel, low-noise, programmable gain amplifier that accepts fully differential and
quasi-differential input signals with diagnostics capability
controlled through an I2C interface. The devices’ audio
receiver can also pair with the MAX13325/MAX13326
audio transmitter to form a complete differential audio link
in automotive systems.
Each channel of the device features high common-mode
rejection ratio (CMRR) (80dB), enabling the recovery of
audio signals in the presence of large common-mode
noise in automotive environments. An integrated programmable gain amplifier is adjustable from -14dB to
+16dB (MAX13335E) and -22dB to +8dB (MAX13336E)
with zero-crossing detection to provide an optimum
output-signal level and limit zip noise. The external flexible diagnostic inputs can be configured to perform jack
sense functions or to detect short-to-battery, short-toground, open load, and shorts between channels.
The audio inputs are protected against ISO 10605 Q15kV
Air Gap and Q8kV Contact Discharge ESD pulses. Both
devices have a -40NC to +105NC operating temperature
range, and are available in a 16-pin QSOP package.
Features
S +3.3V or +5V Operation
S +28V to -16V Tolerant Inputs
S Wide Common-Mode Input Range (-5V to +11.5V)
S Fully Differential Inputs Up to 7V
S Quasi-Differential Inputs Up to 3.5V
S Audio Presence Detection
S Jack Sense Detection
S Diagnostic Capability
S Programmable Gain with Zero-Crossing Detection
S I2C Control Interface
S Automotive Grade ESD Protection
ISO 10605 ±15kV Air Gap
±8kV Contact Discharge
RMS
RMS
Applications
Radio Head Units
RSA/RSE
Connectivity Modules
Automotive Telematics
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX13335E.related.
Typical Application Circuits
MAX13335E/MAX13336E
MAX13325
DIAGNOSTICS
MAX13326
PGA
PGA
Typical Application Circuits continued at end of data sheet.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Operating Junction Temperature Range ......... -40NC to +150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Leakage CurrentI
DLKG
ESD PROTECTION
ISO 10605 Air GapV
Contact DischargeV
ESD
ESD
DIGITAL INTERFACE
Input Voltage HighV
Input Voltage LowV
Input Voltage HysteresisV
I/O Leakage CurrentI
Output Low VoltageV
EN to Full Operation Timet
INH
INL
HYS
LKG
OL
SON
I2C TIMING
Output Fall Timet
OF
Pin CapacitanceC
Clock Frequencyf
SCL Low Timet
SCL High Timet
START Condition Hold Timet
START Condition Setup Timet
Data Hold Timet
Data Setup Timet
SCL
LOW
HIGH
HD:STA
SU:STA
HD:DAT
SU:DAT
Input Rise Timet
Input Fall Timet
STOP Condition Setup Timet
Bus Free Timet
Maximum Bus CapacitanceC
SU:STO
BUF
BUS
Note 2: Specifications within minimum and maximum limits are 100% production tested at TA = +25NC and are guaranteed over
the operating temperature range by design and characterization. Actual typical values may vary and are not guaranteed.
Note 3: Guaranteed by bench characterization.
Note 4: A