The MAX13335E/MAX13336E are high-fidelity stereo
audio input amplifiers designed for automotive applications requiring audio-level detection and/or jack sensing
capability.
The devices feature a dual-channel, low-noise, programmable gain amplifier that accepts fully differential and
quasi-differential input signals with diagnostics capability
controlled through an I2C interface. The devices’ audio
receiver can also pair with the MAX13325/MAX13326
audio transmitter to form a complete differential audio link
in automotive systems.
Each channel of the device features high common-mode
rejection ratio (CMRR) (80dB), enabling the recovery of
audio signals in the presence of large common-mode
noise in automotive environments. An integrated programmable gain amplifier is adjustable from -14dB to
+16dB (MAX13335E) and -22dB to +8dB (MAX13336E)
with zero-crossing detection to provide an optimum
output-signal level and limit zip noise. The external flexible diagnostic inputs can be configured to perform jack
sense functions or to detect short-to-battery, short-toground, open load, and shorts between channels.
The audio inputs are protected against ISO 10605 Q15kV
Air Gap and Q8kV Contact Discharge ESD pulses. Both
devices have a -40NC to +105NC operating temperature
range, and are available in a 16-pin QSOP package.
Features
S +3.3V or +5V Operation
S +28V to -16V Tolerant Inputs
S Wide Common-Mode Input Range (-5V to +11.5V)
S Fully Differential Inputs Up to 7V
S Quasi-Differential Inputs Up to 3.5V
S Audio Presence Detection
S Jack Sense Detection
S Diagnostic Capability
S Programmable Gain with Zero-Crossing Detection
S I2C Control Interface
S Automotive Grade ESD Protection
ISO 10605 ±15kV Air Gap
±8kV Contact Discharge
RMS
RMS
Applications
Radio Head Units
RSA/RSE
Connectivity Modules
Automotive Telematics
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX13335E.related.
Typical Application Circuits
MAX13335E/MAX13336E
MAX13325
DIAGNOSTICS
MAX13326
PGA
PGA
Typical Application Circuits continued at end of data sheet.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Operating Junction Temperature Range ......... -40NC to +150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
(VDD = 5V, AV = -6dB, RL = 10kI, f = 20Hz to 20kHz, TA = TJ = -40NC to +105NC, unless otherwise noted. Typical values are at
TA = 25NC under normal conditions, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Leakage CurrentI
DLKG
ESD PROTECTION
ISO 10605 Air GapV
Contact DischargeV
ESD
ESD
DIGITAL INTERFACE
Input Voltage HighV
Input Voltage LowV
Input Voltage HysteresisV
I/O Leakage CurrentI
Output Low VoltageV
EN to Full Operation Timet
INH
INL
HYS
LKG
OL
SON
I2C TIMING
Output Fall Timet
OF
Pin CapacitanceC
Clock Frequencyf
SCL Low Timet
SCL High Timet
START Condition Hold Timet
START Condition Setup Timet
Data Hold Timet
Data Setup Timet
SCL
LOW
HIGH
HD:STA
SU:STA
HD:DAT
SU:DAT
Input Rise Timet
Input Fall Timet
STOP Condition Setup Timet
Bus Free Timet
Maximum Bus CapacitanceC
SU:STO
BUF
BUS
Note 2: Specifications within minimum and maximum limits are 100% production tested at TA = +25NC and are guaranteed over
the operating temperature range by design and characterization. Actual typical values may vary and are not guaranteed.
Note 3: Guaranteed by bench characterization.
Note 4: A
The MAX13335E/MAX13336E are designed to operate
with the MAX13325/MAX13326 dual automotive audio
line drivers to form a complete differential audio link
in automotive systems. In addition, the MAX13335E/
MAX13336E can operate as an auxiliary input audio
amplifier with jack sense function.
Signal Path
The devices can be configured to operate with quasi-differential (up to 3.5V
input signals. Both input channels feature high 80dB CMRR
(typ). An integrated programmable gain amplifier with zerocrossing detection controlled through the I2C interface provides adjustable gain from -14dB to +16dB (MAX13335E)
or -22dB to +8dB (MAX13336E) in +2dB increments. Zerocrossing detection can be enabled to limit the zip noise
during a gain transition by delaying the gain change until a
zero-crossing event occurs on the input signal.
The devices can monitor the inputs for the presence of
audio, clip detection, and change-of-state in the jack sense.
An active-low, open-drain interrupt request output can be
configured through the I2C interface to report the presence
of audio, clip detection, and change-of-state in the jack
sense. The internal status register also latches the status
change of those parameters until an I2C read is performed.
D_
R
D_
Figure 1. Diagnostic I/O Port
) and fully differential (up to 7V
RMS
Interrupt Output
40µA TO
705µA
V
IDH
V
IDL
DH_
DL_
I2C INTERFACE
RMS
)
Thermal Shutdown
Thermal shutdown protects the device when the junction
temperature exceeds +150NC (typ). The device resumes
operation when the junction temperature drops below the
thermal shutdown hysteresis of 15NC (typ). The internal
status register latches the status change of the TSD bit
until an I2C read is performed.
Diagnostics
The devices feature four similar diagnostic I/O ports.
When configured correctly, they are capable of performing jack sense detection, short-to-ground, short-tobattery, open-load, and shorts between channels. Each
diagnostic I/O port contains a programmable current
source, a voltage sense, and a diode to ground.
The principle behind the diagnosis is simply forcing a
current into the load attached to the I/O port and sensing
the voltage to check if it is greater or smaller than the
two predefined low/high thresholds. These can be easily
accessed by a microcontroller through the I2C interface.
The procedure usually starts with stepping up the current
source from the minimum to maximum range.
1) If the sensed voltage is consistently below the low
threshold, a short-to-ground event is determined.
2) However, if the sensed voltage is consistently above
the high threshold, there is a possibility of either a
short-to-battery or an open-load event. In order to differentiate between them, the I/O port should be tested
again with a voltage-sense-only configuration (i.e.,
with the current source switched off). If the sensed
voltage remains above the high threshold, a short-tobattery event has occurred. Otherwise, an open-load
event is detected.
3) In some current source range, if the sensed voltage
is between the high and low thresholds, this could
indicate that the load is present.
A valid readout of the status might require some amount
of delays (to be inserted by the microcontroller) due to
the settling time needed to charge/discharge any external capacitive load on the I/O port.
The diode is useful in the case of sensing an unconnected load or short between channels. Here, one end
of the load can be forced to ground by the diode and
the usual procedure described above can be applied to
detect various events. It is, however, advisable to test the
I/O port for a short-to-battery condition prior to turning on
the diode as it could risk damaging the device.
See the Applications Information section for various
examples on how the diagnostic can be set up to detect
different events.
Applications Information
Serial Interface
Writing to the device using I2C requires that first the master send a START condition (S) followed by the device’s
I2C address. After the address, the master sends the
address of the register that is to be programmed. The
master then ends communication by issuing a STOP condition (P) to relinquish control of the bus, or a repeated
START condition (Sr) to communicate to another I2C
slave (Figure 2).
Bit Transfer
Each SCL rising edge transfers one data bit. The data
on SDA must remain stable during the high portion of the
SCL clock pulse (Figure 3). Changes in SDA while SCL
SDA
t
t
F
t
LOW
SU:DAT
t
R
t
F
is high are read as control signals (see the START and
STOP Conditions section). When the serial interface is
inactive, SDA and SCL idle high.
START and STOP Conditions
A master device initiates communication by issuing a
START condition (S) which is a high-to-low transition on
SDA with SCL high. A START condition from the master
signals the beginning of a transmission to the device.
The master terminates transmission by a STOP condition (P) (see the Acknowledge Bitsection). A STOP
condition is a low-to-high transition on SDA while SCL is
high (Figure 4). The STOP condition frees the bus. If a
repeated START condition (Sr) is generated instead of a
STOP condition, the bus remains active. When a STOP
condition or incorrect slave ID is detected, the device
internally disconnects SCL from the serial interface until
the next START or repeated START condition, minimizing digital noise and feedthrough.
t
t
HD:STA
t
SP
R
t
BUF
SCL
t
HD:STA
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:STO
Figure 2. I2C Timing
START
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE OF
DATA ALLOWED
CONDITION
SDA
SCL
Figure 3. Bit TransferFigure 4. START/STOP Conditions
The acknowledge bit (ACK) is a clocked 9th bit that the
device uses to handshake the receipt of each byte of
data when in write mode. The device pulls down SDA
during the entire master-generated 9th clock pulse if
the previous byte is successfully received (Figure 5).
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master could retry communication. The master must pull down SDA during the 9th clock cycle to
acknowledge receipt of data when the device is in read
mode. An acknowledge must be sent by the master
after each read byte to allow data transfer to continue.
S
SDA
SCL
18
A not-acknowledge is sent when the master reads the
final byte of data from the device, followed by a STOP
condition.
Slave Address
The device is programmable to one of the four I2C slave
addresses (Table 2). The power-on default I2C slave address
of the device for read/write is 0xD0/0xD1 (1101000R/W). The
I2C slave address of the device can be selected by writing
to Control Register 1 (0x03) while INT is pulled low externally
during the I2C write duration (Figure 6).
Single Byte-Write Operation
For a single byte-write operation, send the slave address
as the first byte followed by the register address and then
a single data byte (Figure 7).
For a burst-write operation, send the slave address as
the first byte followed by the register address and then
the data bytes (Figure 8).
Single Byte-Read Operation
For a single byte-read operation, send the slave address
with read bit set as the first byte followed by the register
address. Then send a repeated START condition followed by the slave address. After the slave sends the
SS7S6S5S4S3S2S1ACK
SLAVE ADDRESS
B7B6B5B4B3B2B1B0 ACK B7B6B5B4B3B2B1B0 ACK
DATA 1
Figure 8. A Burst-Write Operation
R/W
= 0
ACK B7B6B5B4B3B2B1B0 ACKP
data byte, send a not-acknowledge followed by a STOP
condition (Figure 9).
Burst-Read Operation
For a burst-read operation, send the slave address with
a write as the first byte followed by the register address.
Then send a repeated START condition followed by the
slave address. The slave sends data bytes until a notacknowledge condition is sent (Figure 10).
The bits in Status Register 0 are updated to reflect the states of the upper (DH_) and lower (DL_) comparator’s threshold
when voltage sensing is enabled for the corresponding diagnostic I/O. Combinations of DH_ and DL_ can be used to
decode the fault on the I/O port.
00Short-to-ground (or disabled)
01No fault
10Invalid (not used)
11Short-to-battery if current source is disabled (i.e., D_[3:0] = 1110)
11Open-load if current source is enabled (i.e., D_[3:0] = 0001 to 1101)
Bits 7 to 2: No Function (0 should be written during write access.)
Bits 1 and 0: I2C�
The I2C1 and I2C0 bits determine the I2C slave address of the device. The I2C slave address is changed by writing to
CTRL1 while INT is pulled low (e.g., by an external microcontroller) for the duration of the I2C write cycle.
The Diagnostic registers, DIAG0 and DIAG1, program the state of the four diagnostic I/O ports D_. The diagnostic ports
can be programmed to operate in one of the four states:
1) Setting D_[3:0] = 0000 disables the corresponding diagnostic I/O.
2) Setting D_[3:0] = 0001 to 1101 enables the internal current source (40FA to 705FA) and voltage sensing. The voltage sensing utilizes a window comparator with an upper threshold of 1.94V and a lower threshold of 0.92V (see the
Diagnostic Configurations section).
3) Setting D_[3:0] = 1110 enables voltage sensing only.
4) Setting D_[3:0] = 1111 enables the internal diode to ground.
Diagnostic output disabled.
Enables the 40FA current source and voltage sense.
Enables the 97FA current source and voltage sense.
Enables the 154FA current source and voltage sense.
Enables the 210FA current source and voltage sense.
Enables the 265FA current source and voltage sense.
Enables the 320FA current source and voltage sense.
Enables the 375FA current source and voltage sense.
Enables the 430FA current source and voltage sense.
Enables the 485FA current source and voltage sense.
Enables the 540FA current source and voltage sense.
Enables the 595FA current source and voltage sense.
Enables the 650FA current source and voltage sense.
Enables the 705FA current source and voltage sense.
Enable voltage sense. The current source is disabled.
Enables the diode. The current source and voltage sense are disabled.
The Gain register sets the gain of the internal programmable gain amplifier (AV) for the left (GL[3:0]) and right (GR[3:0])
channels. The gain of the programmable gain amplifier (AV) is determined by the following transfer function:
GL3GL2GL1GL0GR3GR2GR1GR0
00000000
Gain(AV) = -14dB + (G_[3:0] x 2)dB (for MAX13335E)
Gain(AV) = -22dB + (G_[3:0] x 2)dB (for MAX13336E)
Diagnostic Configurations
The device’s diagnostics can be configured for local jack
sense, remote jack sense, and differential drive connections (see the Typical Application Circuits). Diagnostic
registers DIAG0 and DIAG1 configure the diagnostic I/O
ports D_ as a current-source output with voltage sensing
enabled, a voltage sensing input, or a diode to GND.
When voltage sensing is enabled, the current states of
the internal window comparator are updated to status
register STAT0. A valid readout of the STAT0 register
might require some amount of delays (to be inserted by
the microcontroller) between configuring the diagnostic
and reading the status register due to the settling time
needed to charge/discharge the external capacitive load
on the D_ pins.
Local Jack Sense
The device is configured for jack sense function when the
jack is localized to the same module. In this application
example, the diagnostic I/O D1 is configured as a 97FA
current-source output and D0 is configured for voltage
sensing. When a plug is not inserted, the internal spring
contact of the jack shorts D1 to D0. The 97FA current
source from D1 pulls D0 to VDD resulting in DH0 = 1.
When a plug is inserted, the internal spring contact of
the jack is forced open and disconnects D1 from D0. This
results in D0 going low and hence DH0 = 0.
Remote Jack Sense Detection
When the jack is remotely located, the device can be
used for additional fault detection of the wiring harness
used for the connection. See the Typical Application
Circuits.
For fully differential applications, the device can be configured to detect faults in the wiring harness as shown in
the Typical Application Circuits.
Table 4. Local Jack Sense Diagnostic Configuration
When the device is used in an auxiliary input amplifier, it can detect if audio is present at the inputs so the
downstream DSP does not have to continuously convert
the analog signal to digital in order to monitor the audio
stream. This can save two ADC inputs as the auxiliary
input can be muxed with another audio stream that is
mutually exclusive. To do this, perform the following steps:
V
IDH
DH0
DL0
V
IDL
1) Set the gain in the GAIN register based on the
required input audio level where the APD threshold is
exceeded. The threshold is set to 200mV
RMS
/G_[3:0].
2) Set API bit in the CTRL0 register to enable the APD
interrupt.
When the input audio level exceeds 200mV
RMS
/G_[3:0]
the INT pin is asserted. The microcontroller can read
back the STAT0 register to check for APD = 1.
When the device is used as an auxiliary amplifier, there
is the option to put the device into a low-power standby
mode while waiting for a plug to be inserted into the jack.
To do this, perform the following steps:
1) Connect D0 to the R (or L) of the jack.
2) Connect R
resistor to ground.
SENSE
(or L
) of the jack with a 50I
SENSE
V
IDH
V
IDL
V
IDH
V
IDL
3) Set the SHDN bit to 1 in the CTRL0 register to power
down the amplifier.
4) Set D0[3:0] = 0001 to source 40FA out of the D0 pin.
5) Enable the JSI bit in the CTRL0 register.
When a plug is inserted, the DH0 comparator trips and subsequently asserts the interrupt INT pin. The microcontroller
can read back the STAT0 register to check for DH0 = 1
and follow up by setting SHDN to 0.
In the standby state, the typical current consumption is
reduced to 290FA.
For maximum protection against IEC 61000-4-2 and ISO
10605 ESD pulses, a 1kI or larger resistor is recommended on every diagnostic D_ pin before the input
AC-coupling capacitor. Additionally, a suitable ESD
diode must be connected from the DC-blocking ceramic
capacitor to ground. The ESD diode can be connected
1nF
1nF
1nF
1nF
1kΩ
2.2µF
1kΩ
2.2µF
1kΩ
2.2µF
on either side of the DC-blocking capacitor; however,
depending on application requirements, the IC side
may allow for a lower clamping voltage, which results
in a smaller ESD device. If the input source is always
DC biased to V
/2, then a unidirectional ESD device
BAT
can be used when clamping on the input side of the
DC-blocking capacitor. See Figure 13.
MAX13335E/MAX13336E
D3
20Ω
20Ω
20Ω
20Ω
INL-
INL+
INR+
INR-
D2
D1
D0
DIAGNOSTICS
PGA
PGA
I2C
AND
CONTROL
1kΩ
2.2µF
Figure 13. ESD Protection Technique Against IEC 61000-4-2 and ISO 10605 Pulses
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 28