MAXIM MAX13325, MAX13326 User Manual

19-5136; Rev 3; 6/10

EVALUATION KIT

AVAILABLE

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

General Description

The MAX13325/MAX13326 dual audio line drivers provide
a reliable differential interface between automotive audio
components. The devices feature differential inputs and
outputs, integrated output diagnostics, and are controlled
using an I2C interface or operate in stand-alone mode.
The outputs can deliver up to 4V

The MAX13325 buffers analog audio signals for trans­mission over long cable distances with a fixed gain of
12dB, whereas the MAX13326 provides a 0dB fixed
gain. The diagnostics on the outputs report conditions
on a per channel basis, including short to GND, short
to battery, overcurrent, overtemperature, and excessive
offset. The output amplifiers can drive capacitive loads
up to 4nF to ground and 3nF differentially.

The outputs are protected according to IEC 61000-4-2
Q8kV Contact Discharge, and Q15kV Air Gap. The

MAX13325/MAX13326 are specified from -40NC to

+105NC and are available in a 28-pin TSSOP package
with an exposed pad.

Applications

Automotive Radio and Rear Seat Entertainment

Professional Remote Audio Amplifiers

into 100I loads.

RMS

Features

S Comprehensive Programmability and Diagnostics

Using I2C Interface

S Autoretry Function in Stand-Alone Mode
S Drive Capacitive Loads ≤ 3nF Differentially, ≤ 4nF

to Ground

S 112dB Signal-to-Noise Ratio
S Low 0.002% THD at 4V
S High PSRR (70dB at 1kHz)
S High CMRR (80dB at 1kHz)
S Low Output Noise (3µV
S Excellent Channel-to-Channel Matching
S Load-Dump Transient Protection
S Protected Output Against Various Short-Circuit

Conditions

S ESD Protection for ±8kV Contact Discharge,

±15kV Air Gap

S Long-Distance Drive Capability Typically Up to

15m or Greater

S Noise-Rejecting Differential Inputs and Outputs
S Low-Power Shutdown Mode < 10µA
S Hardware or Software MUTE Function
S 28-Pin TSSOP Package with Exposed Pad

into 2.7kI Loads

RMS

), MAX13326

RMS

MAX13325/MAX13326

Typical Operating Circuit

V

C6

100nF

MICROPROCESSOR

FROM AUDIO

SOURCE

FROM AUDIO

SOURCE

C1

DIAGNOSTIC

MAX13325
MAX13326

OUTPUT

470nF

CHARGE

PUMP

BIAS

CHOLDCMCP

PROTECTION

+5V

V

L

ADD1

ADD0

SDA

2

C INTERFACE

I

SCL

AND

DIGITAL CONTROL

TO

FLAG

SHDN

MUTE

C7

2.2µF
INLP

INLM

C8

2.2µF

C9

2.2µF
INRP

INRM

C10

2.2µF

*OPTIONAL : NEEDED FOR AUTOMOTIVE LOAD DUMP PROTECTION ONLY
**USE D2 WHEN CHARGE PUMP IS OFF AND EXTERNAL SUPPLY IS PROVIDED TO C HOLD

LEFT

RIGHT

SUP

D2**

V

DD

PGND

BIAS

CSS

GND

OUTLP

OUTLM

OUTRP

OUTRM

* OPTIONAL

C2

µF

1

ESD

+12V

C4
10µF

C5
220nF

Q1

1nF

1nF

R1

1kI

D1

1nF

1nF

1nF

1nF

Ordering Information

PART

MAX13325GUI/V+ 28 TSSOP-EP*

C3
1µF

MAX13326GUI/V+ 28 TSSOP-EP*

/V Denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.

PIN­PACKAGE

TEMP RANGE

-40NC to
+105NC

-40NC to
+105NC

GAIN

(dB)

12

0

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

ABSOLUTE MAXIMUM RATINGS

VDD to PGND ........................................................-0.3V to +28V

CHOLD .................................................................-0.3V to +28V

VL to GND ...............................................................-0.3V to +6V

GND, PGND ........................................................-0.3V to +0.3V

OUT_ to PGND ........................................................ -0.3V to 28V

IN_, BIAS to AGND ..................................-0.3V to (VDD + 0.3V)

SCL, SDA, ADD0, ADD1, MUTE, SHDN,

FLAG to GND ..........................................................-0.3V to +6V

OUT_ Short Circuit to PGND or VDD .........................Continuous

Short Circuits Between Any OUT_ ............................ Continuous

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

MAX13325/MAX13326

(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,
unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AMPLIFIER DC CHARACTERISTICS

Transient Supply Voltage
(Load Dump)

Operating Supply Voltage Range

VDD OVLO Threshold V
VDD UVLO Threshold V
VL UVLO Threshold V

Supply Current I

Logic Supply Current I

Shutdown Supply Current I

Turn-On Time (from Shutdown)
Turn-On Time (from Mute)
Differential Input Resistance R

Single-Ended Input Impedance R

Signal-Path Gain (Note 3) A

Channel-to-Channel Gain
Tracking

V

DDMAX

V

DDOV

DDUV

SHDN

DD

V

LUV

DD

INDIF

Using external nMOS-RTR020N05, 300ms
duration

L

Rising edge 18.5 19.2 V
Falling edge 3.3 3.5 V
Falling edge 2.2 2.4 V
TA = +25NC, no load
TA = -40NC to +105NC, no load
VL = 5V 1.7 mA

L

I

DD

I

L

MUTE = VL
SHDN = VL, C

Measure across input 18 24 30

Each input to ground (MAX13325) 15 20 25

IN

Each input to ground (MAX13326) 12 16 20

MAX13325 11.8 12 12.2

V

MAX13326 -0.2 0 +0.2

Continuous Power Dissipation (TA = +70NC) (multilayer board)

28-Pin TSSOP (derate 27mW/NC above +70NC) ..... 2162.2mW

Junction-to-Ambient Thermal Resistance (BJA)

(Note 1) ........................................................................ 37NC/W

Operating Temperature Range ........................ -40NC to +105NC

Storage Temperature Range ............................ -65NC to +150NC

Junction Temperature .....................................................+150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

50 V

4.5 18

2.7 5.5

39 mA

50 mA

TA = +25NC
TA = -40NC to +105NC

= 220nF

CSS

0.5 10

0.5

< 0.1 2

220 ms

6 ms

Q0.4

V

FA

FA

kI

kI

dB

dB

2 ______________________________________________________________________________________

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,
unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Mode Output Balance
OUT_+ to OUT_- (Note 4)

Output Offset Voltage
(OUT_+ to OUT_-)

BIAS Voltage V
BIAS Impedance Z

Output-Voltage Swing Differential

Power-Supply Rejection Ratio PSRR

Common-Mode Rejection Ratio CMRR VIN = 1V

AMPLIFIER AC CHARACTERISTICS

Total Harmonic Distortion Plus
Noise (Note 5)

Total Harmonic Distortion Plus
Noise at VDD = 5V (Note 5)

Capacitive-Load Stability 3 nF

Capacitive-Load Drive Capability

Signal-to-Noise Ratio (Note 5) SNR

Unity-Gain Bandwidth 3 MHz
Output Slew Rate 2.5

Output-Voltage Noise

Crosstalk VIN = 1V
Mute Time To achieve soft mute, C
Mute Attenuation VIN = 1V
Click-and-Pop Level (Note 6) K
Click-and-Pop Level (Note 6) K

V

OOS

BIAS

BIAS

THD+N

THD+N

CP

CP

MUTE = GND, TA = +25NC
MUTE = VL, TA = +25NC

Relative to V
I

BIAS

VDD = 14.4V, VIN = Q14.4V, RL = 1kI Q12.5
VDD = 5.0V, VIN = Q5V, RL = 1kI Q4.2
VDD = 4.5V to 18V -80 -96

VDD = 14.5V, +500mV

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

No sustained
oscillation

MAX13325, gain = 12dB, V
A-weighted

MAX13326, gain = 0dB, V
A-weighted

A-weighted, MAX13325 10

A-weighted, MAX13326 3

Into and out of mute -70 dBV
Into and out of shutdown, 1kI

= Q10FA

RMS

= 4V

RMS

= 4V

RMS

= 4V

RMS

= 7V

RMS

= 1V

RMS

= 1V

RMS

= 2V

RMS

RMS

RMS

DD

69 92 115

ripple at 1kHz -95

P-P

ripple at 10kHz -80

P-P

, 100Hz to 10kHz -48 -80 dB

, RL = 2.7kI
, RL = 1kI
, RL = 100I, VDD = 8V
, RL = 1kI
, RL = 2.7kI
, RL = 1kI
, RL = 1kI

C

to GND 4

LOAD

C

differential 3

LOAD

= 4V

OUT

= 4V

OUT

, 1kHz -110 dB

= 220nF 4 ms

CSS

, 1kHz -75 dB

RMS

RMS

,

,

-40 dB

Q0.5 Q10
Q0.2 Q3

50 52.5 %

0.002

0.004

0.03

0.2

0.01

0.02

0.8

112

122

-45 dBV

mV

kI

V

dBVDD = 14.5V, +500mV

%

%

nF

dB

V/Fs

FV

MAX13325/MAX13326

_______________________________________________________________________________________ 3

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,
unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHARGE PUMP

Charge-Pump Overdrive Voltage,
V

V

Charge-Pump Frequency f

DIAGNOSTICS

Output Current Limit Short to GND or battery 580 mA
Current-Limit Warning Threshold 230 mA

MAX13325/MAX13326

Open-Load Detection 10
Output Offset Detection Valid when muted
Thermal Warning Threshold 135
Thermal Shutdown Threshold 165
Thermal Shutdown Hysteresis 15

ESD PROTECTION

Air Gap IEC 61000-4-2 OUT_ pins
Contact Discharge IEC 61000-4-2 OUT_ pins
HBM All pins

CHOLD

CHOLD

– V

(Hard Mode)

DD

- V

(Soft Mode) V

DD

V

CPH

CPS

CP

VDD = 4.5V, I
VDD = 18V, I

VDD unconnected, I
VL = 3.3V

VL = 5V 3.9

CPOFF = 0

SOURCE

SOURCE

= 6.6mA 3.2 4.0

= 6.6mA 4.5 5.5

SOURCE

= 40FA,

CPF[1:0] = 00 333
CPF[1:0] = 01 190
CPF[1:0] = 10 426
CPF[1:0] = 11 260

2.1

Q250

Q15

Q8
Q2

V

V

kHz

kI

mV

NC
NC
NC

kV
kV
kV

4 ______________________________________________________________________________________

Dual Automotive, Audio Line Drivers

_

−

 

_

OUT_ OUT_

OUT_ OUT

( | V ) ( V )

20 log .

( V ) ( V ) 2

−

+ −

+

 

−

 

×

 

+ ×

 
 

with I2C Control and Diagnostic

DIGITAL CHARACTERISTICS

(VDD = 14.4V, VL = 3.3V, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INTERFACE

Input-Voltage High V

INH

Input-Voltage Low V
Input-Voltage Hysteresis 50 mV
Input Leakage Current Q100 FA
Output Low Voltage FLAG, SDA, I
Output Leakage Current FLAG, SDA = 5.5V 2 FA
Stand-Alone FLAG Pulse Width ADD0, ADD1 = GND 100 ms
Stand-Alone Fault Retry Time ADD0, ADD1 = GND 500 ms

I2C TIMING

Serial-Clock Frequency f
Bus Free Time t
Hold Time t
SCL Low Time t
SCL High Time t
Data Hold Time t
Data Setup Time t

SCL

BUF

HD:STA

LOW

HIGH

HD:DAT

SU:DAT

Bus Capacitance C
Receiving Rise Time t
Receiving Fall Time t
Transmitting Fall Time t
STOP Condition Setup Time t

SU:STO

Pulse Width of Suppressed Spike t

Note 2: All devices are 100% tested at TA = +25NC. Limits over temperature are guaranteed by design.

VL = 2.7V to 5.5V 0.75 x V
VL = 2.7V to 5.5V 0.25 x V

INL

= 3mA 0.4 V

SINK

L

0 400 kHz
Between START and STOP conditions 1.3 Fs
Repeated START condition 0.6 Fs

1.3 Fs

0.6 Fs
0 900 ns

100 ns

Per bus line 400 pF

B

SCL, SDA 20 + 0.1C

R

SCL, SDA 20 + 0.1C

F

SDA, VL = 3.6V 20 + 0.05C

F

B

B

B

0.6 Fs

SP

0 50 ns

L

300 ns
300 ns
250 ns

MAX13325/MAX13326

V
V

Note 3: Signal path gain is defined as:

Note 3: Signal Path Gain is defined as

Note 4: Measured in differential output mode, differential input voltage 4V

Common-mode output balance is defined as:

Common-Mode Output Balance is defined as

Note 5: 22Hz to 22kHz measurement bandwidth.
Note 6: KCP level is calculated as 20log[(peak voltage during mode transition, no input signal)/1V

dBV.

20 log .

 
 

(V ) (V )

 

×

−

OUT_ OUT_

+ −

−

(V ) (V )

IN_ IN

+

(for 0dB gain), 1V

P-P

(for 12dB gain) 1kHz.

P-P

]. Units are expressed in

RMS

_______________________________________________________________________________________ 5

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

Typical Operating Characteristics

(V

= 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)

DD

SHUTDOWN CURRENT

COMMON-MODE REJECTION RATIO

vs. TEMPERATURE

0.40

0.35

0.30

0.25

0.20

0.15

SHUTDOWN CURRENT (µA)

0.10

0.05

0

-40

MAX13325/MAX13326

TEMPERATURE (°C)

NO LOAD
INPUTS SHORTED
V

= 0V

SHDN

9580-25 -10 5 35 5020 65

TOTAL HARMONIC DISTORTION PLUS

MAX13325 toc01

0

-10

-20

-30

-40

-50

CMRR (dB)

-60

-70

-80

-90

-100
10 100k

POWER-SUPPLY REJECTION RATIO

NOISE vs. OUTPUT VOLTAGE

MAX13325 toc04

PSRR (dB)

0

500mV

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120
10 100k

0.020

0.018

0.016

0.014

0.012

0.010

THD+N (%)

0.008

0.006

0.004

0.002

0

0 10

OUTPUT VOLTAGE (V

RMS

fIN = 1kHz

986 72 3 4 51

)

vs. FREQUENCY

FREQUENCY (Hz)

vs. FREQUENCY

RIPPLE

P-P

FREQUENCY (Hz)

1V

INPUT

RMS

20kHz AES17 FILTER

10k1k100

10k1k100

MAX13325 toc02

MAX13325 toc05

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

0.010

0.009

0.008

0.007

0.006

0.005

THDN (%)

0.004

0.003

0.002

0.001

0

LEFT CHANNEL

RIGHT CHANNEL

10 100k

FREQUENCY (Hz)

CROSSTALK vs. FREQUENCY

0

-10

1V

INPUT

RMS

20kHz AES17 FILTER

-20

-30

-40

-50

-60

-70

-80

CROSSTALK (dB)

-90

-100

-110

-120

-130

-140
10 100k

RIGHT TO LEFT

LEFT TO RIGHT

FREQUENCY (Hz)

1V

OUTPUT

RMS

MAX13325 toc03

10k1k100

MAX13325 toc06

10k1k100

MUTE ATTENUATION vs. FREQUENCY

-60
2V

INPUT

RMS

A-WEIGHTED

-64

-68

-72

MUTE ATTENUATION (dB)

-76

-80

10 100k

LEFT CHANNEL

RIGHT CHANNEL

FREQUENCY (Hz)

OUTPUT-NOISE VOLTAGE vs. FREQUENCY

0

-10

-20

MAX13325 toc07

-30

-40

-50

-60

-70

-80
90

-100

-110

OUTPUT-NOISE VOLTAGE (dBV)

-120

-130

-140

10k1k100

-150
0 20

FREQUENCY (kHz)

MAX13325 toc08

181612 144 6 8 102

0

-15

-30

-45

-60

-75

FFT (dBV)

-90

-105

-120

-135

-150
10 100k

FFT vs. FREQUENCY

V

= 1V

OUT

RMS

1kHz

FREQUENCY (Hz)

6 ______________________________________________________________________________________

MAX13325 toc09

10k1k100

Dual Automotive, Audio Line Drivers

GAIN ERROR (dB)

with I2C Control and Diagnostic

Typical Operating Characteristics (continued)

(V

= 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)

DD

MAX13325/MAX13326

0.020

0.015

0.010

0.005

LEFT CHANNEL

0

-0.005

-0.010

-0.015
RIGHT CHANNEL

-0.020

-40
TEMPERATURE (°C)

OUTPUT-NOISE VOLTAGE vs. FREQUENCY

0

MAX13326 (0dB)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

OUTPUT NOISE VOLTAGE (dBV)

-120

-130

-140

-150
0 20

FREQUENCY (kHz)

GAIN ERROR vs. TEMPERATURE

OUTPUT VOLTAGE vs. CHARGE-PUMP

OVERDRIVE VOLTAGE

MAX13325 toc12

GAIN ERROR (dB)

0.050

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

-0.005

-0.010

-0.015

-0.020

-0.025

-0.030

-0.035

-0.040

-0.045

-0.050

10.5

10.0

MAX13325 toc10

9.5

9.0

8.5

- VDD) (V)

THDN = 1%

= 1kHz

f

IN

V

= 14.4

DD

= 1kI

R

L

CPOFF = 1

4.0 4.53.52.5 3.00.5 1.0 1.5 2.0

OUTPUT VOLTAGE (V)

8.0

7.5

9580-25 -10 5 35 5020 65

7.0
0 5.0

(V

CHOLD

GAIN vs. TEMPERATURE

0.20
MAX13326 (0dB)

0.15

VOUT = 1V

MAX13325 toc13

0.10

0.05

0

GAIN (dB)

-0.05

-0.10

-0.15

-0.20

181612 144 6 8 102

-40

RMS

TEMPERATURE (°C)

LEFT CHANNEL

RIGHT CHANNEL

9580-25 -10 5 35 5020 65

MAX13325 toc14

-0.005

-0.010

GAIN ERROR (dB)

-0.015

-0.020

-0.025

-0.030

-0.035

-0.040

-0.045

-0.050

0.050

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

GAIN ERROR vs. FREQUENCY

1V

OUTPUT

RMS

0

10 100k

FREQUENCY (Hz)

10k1k100

GAIN ERROR vs. FREQUENCY

MAX13326 (0dB)

OUTPUT

1V

RMS

0

10 100k

FREQUENCY (Hz)

10k1k100

MAX13325 toc12

MAX13325 toc15

_______________________________________________________________________________________ 7

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

Pin Configuration

TOP VIEW

+

BIAS

V

L

I.C.

I.C.

INLP

INLM

V

DD

INRM

INRP

I.C.

I.C.

SHDN

MAX13325/MAX13326

MUTE

ADD0

1

2

3

4

5

MAX13325

6

MAX13326

7

8

9

11

12

13

EP

28

CSS

FLAG

27

CM

26

CP

25

OUTLP

24

OUTLM

23

22

CHOLD

21

PGND

20

OUTRP

1910OUTRM

18

GND

17

ADD1

16

SDA

1514SCL

TSSOP

CONNECT TO PGND.

Pin Description

PIN NAME FUNCTION

1 BIAS Analog Bias Voltage. Bypass BIAS to GND with a 10FF capacitor.

2 V

L

3, 4, 10, 11 I.C. Internally Connected. Leave unconnected.

5 INLP

6 INLM

7 V

DD

8 INRM

9 INRP

12 SHDN Shutdown Input. Drive SHDN low to power down the device.
13 MUTE Mute Input. Drive MUTE low to mute the outputs. The outputs are low impedance in mute.

Logic Supply Voltage. Connect VL to a 2.7V to 5V logic supply. Bypass VL to GND with a 0.1FF
capacitor.

Left Audio Positive Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.

Left Audio Negative Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.

Power-Supply Input. Connect VDD to the supply voltage. Bypass VDD to GND through a 1FF
capacitor.

Right Audio Negative Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.

Right Audio Positive Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.

8 ______________________________________________________________________________________

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

Pin Description (continued)

PIN NAME FUNCTION

14 ADD0

15 SCL Serial Clock
16 SDA Serial-Data IO

17 ADD1

18 GND Analog Ground. Ground connection for the input bias and gain circuits.
19 OUTRM Right Audio Negative Output. Each output is current limited.
20 OUTRP Right Audio Positive Output . Each output is current limited.
21 PGND Power Ground. Ground connection for the output stage drivers.

22 CHOLD

23 OUTLM Left Audio Negative Output. Each output is current limited.
24 OUTLP Left Audio Positive Outputs. Each output is current limited.
25 CP Charge-Pump Flying Capacitor, Positive Connection
26 CM Charge-Pump Flying Capacitor, Negative Connection

27 FLAG

28 CSS

— EP Exposed Pad. Connect to PGND.

I2C Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses.
Connect ADD0 and ADD1 to GND for stand-alone mode.

I2C Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses.
Connect ADD0 and ADD1 to GND for stand-alone mode.

Charge-Pump Output (When Charge Pump is On; CPOFF = 0). When the charge pump is off,
provide an external supply through a diode to the CHOLD input. Bypass CHOLD with 1µF to PGND.

Open-Drain Fault Flag Output. FLAG indicates a fault on any one channel. In stand-alone mode,
FLAG is stretched to a typical pulse width of 100ms.

Soft-Start Capacitor Connection. CSS is charged/discharged by < 100FA current to get soft mute/
play transition. Bypass to GND through a 220nF capacitor.

MAX13325/MAX13326

Detailed Description

The MAX13325/MAX13326 audio line drivers are designed
to transmit audio data across noisy environments. The dif­ferential interface is highly resistant to noise injection from
external sources common to automotive applications.

The MAX13325/MAX13326 operate in stand-alone or
I2C-compatible mode with diagnostic outputs capable
of detecting short to GND or battery, overcurrent, over­temperature, or excessive offset. A short across another
audio output signal line is also protected.

Table 1. Register Address Map

ADDRESS REGISTER TYPE NAME READ/WRITE DEFAULT

0x00 Configuration CONFIG Read/Write 0x00
0x01 Command Byte CMD Read/Write 0x00
0x02 General Fault GFAULT Read 0x00
0x03 Left-Channel Fault LFAULT Cleared on Read 0x00
0x04 Right-Channel Fault RFAULT Cleared on Read 0x00

0x05 Flag FLAG Read

0x06 General Mask GMASK Read/Write 0x00
0x07 Left-Channel Mask LMASK Read/Write 0x00
0x08 Right-Channel Mask RMASK Read/Write 0x00

_______________________________________________________________________________________ 9

0x04 (12dB)

0x05 (0dB)

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

Configuration Register

Table 2. Configuration Register Format

FUNCTION

Configuration

Register

DIAG: Set DIAG to 1 to enable diagnostic mode. Write '0' to disable diagnostic mode.
ENABLE: Set ENABLE bit to 1 to enable the device. Write ‘0’ disables the device. Low on the SHDN pin overrides the

ENABLE bit.

MUTE: Set the MUTE bit to 1 to mute both the output channels. Output is low impedance when in mute. Low on the
MUTE pin input overrides the MUTE bit.

CPOFF: Set the CPOFF bit to 1 to turn off the charge pump. CHOLD pin must be externally supplied (see the V
parameter in the Electrical Characteristics table). Charge pump is enabled when CPOFF = 0.

OLDL: Write 1 to the OLDL bit to initiate the open-load detection for the left channel. To run OLDL again, write ‘0’ and
‘1’ again.

OLDR: Write 1 to the OLDR bit to initiate the open-load detection for the right channel. To run OLDR again, write ‘0’

MAX13325/MAX13326

and ‘1’ again.

ADDRESS

CODE (HEX)

0x00 DIAG ENABLE MUTE CPOFF OLDL OLDR CPF1 CPF0 0x00

D7 D6 D5 D4 D3 D2 D1 D0

Table 2a. Charge-Pump Frequency Bits

CPF1 CPF0 FREQUENCY (kHz)

0 0 333
0 1 190
1 0 426
1 1 260

REGISTER DATA

POR STATE

(HEX)

CPH

CPF[1:0]: Sets the frequency of the charge pump.

Command Byte Register

Table 3. Command Byte Register Format

FUNCTION

Command Byte

Register

RETRYR: The right-channel power amplifier switches off after a fault condition. Write ‘1’ to turn it back on after the fault
condition.

RETRYL: The left-channel power amplifier switches off after a fault condition. Write ‘1’ to turn on the left-channel power
amplifier after the fault condition.

10 _____________________________________________________________________________________

ADDRESS

CODE (HEX)

0x01 RETRYR RETRYL x x x x x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

REGISTER DATA

POR STATE

(HEX)

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

Table 4. General Fault Register Format

FUNCTION

General Fault

Register

TWARN: The TWARN bit is set to ‘1’ when the temperature warning threshold is reached.

TSHDN: The TSHDN is set to ‘1’ when the temperature shutdown threshold is reached.

DUMP: The DUMP bit is set to ‘1’ when the VDD voltage exceeds the overvoltage threshold.

Set the appropriate mask bit in the GMASK register to detect the general faults. See Table 8.

ADDRESS

CODE (HEX)

0x02 x TWARN TSHDN DUMP x x x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

Table 5. Left-Channel Fault Register Format

ADDRESS

FUNCTION

Left-Channel

Fault Register

CODE

(HEX)

0x03 SVDDL SGNDL LIMITL x OFFSETL OPENL x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

REGISTER DATA

REGISTER DATA

General Faults

MAX13325/MAX13326

POR STATE

(HEX)

Left-Channel Faults

POR STATE

(HEX)

SVDDL: The SVDDL bit is set to ‘1’ when a short to VDD is detected on the left channel.

SGNDL: The SGNDL bit is set to ‘1’ when a short to GND is detected on the left channel.

LIMITL: The LIMITL bit is set to ‘1’ when the current-limit threshold is tripped for left output.

OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.

OPENL: The OPENL bit is set to ‘1’ when an open load is detected on the left channel.

Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9.
When any bit of the LFAULT register is high, the FLAG output is low.

Right-Channel Faults

Table 6. Right-Channel Fault Register Format

ADDRESS

FUNCTION

Right-Channel

Fault Register

SVDDR: The SVDDR bit is set to ‘1’ when a short to VDD is detected on the right channel.

SGNDR: The SGNDR bit is set to ‘1’ when a short to GND is detected on the right channel.

LIMITR: The LIMITR bit is set to ‘1’ when the current-limit threshold is tripped for right output.

OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.

OPENR: The OPENR bit is set to ‘1’ when an open load is detected on the right channel.

Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10.
When any bit of the RFAULT register is high, the FLAG output is pulled low.

CODE
(HEX)

0x04 SVDDR SGNDR LIMITR x OFFSETR OPENR x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

REGISTER DATA

POR STATE

(HEX)

______________________________________________________________________________________ 11

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

FLAG Register

Table 7. Flag Register Format

ADDRESS

FUNCTION

FLAG

Register

FLAG: FLAG bit is set to ‘1’ when the FLAG output is logic-low. The FLAG bit allows to quickly access the status of the
device without using the FLAG output and without having to read all the fault registers.

LHIGHZ: The LHIGHZ bit is set to ‘1’ when the left-channel output is high impedance; for example due to a short circuit.
RHIGHZ: The RHIGHZ bit is set to ‘1’ when the right-channel output is high impedance; for example due to a short

circuit.
OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.
OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.
ID[2:0]: The ID[2:0] bits indicate the device type (12dB = 100 and 0dB = 101).

MAX13325/MAX13326

Table 8. General Mask Register Format

FUNCTION

General Mask

Register

CODE
(HEX)

0x05 FLAG LHIGHZ RHIGHZ OFFSETL OFFSETR ID2 ID1 ID0 0x04/0x05

ADDRESS

CODE
(HEX)

0x06 0 MTWARN MTSHDN MDUMP x x x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

REGISTER DATA

REGISTER DATA

POR STATE

(HEX)

General Mask Register

POR STATE

(HEX)

MTWARN: Set MTWARN to ‘1’ to enable the TWARN fault detection. See Table 4.
MTSHDN: Set MTSHDN to ‘1’ to enable the TSHDN fault detection. See Table 4.
MDUMP: Set MDUMP to ‘1’ to enable the DUMP fault detection. See Table 4.

Left-Channel Mask Register

Table 9. Left-Channel Mask Register

ADDRESS

FUNCTION

Left-Channel

Mask Register

MSVDDL: Set MSVDDL to 1 to enable the short to VDD detection on the left channel.
MSGNDL: Set MSGNDL to 1 to enable the short to GND detection on the left channel.
MLIMITL: Set MLIMITL to 1 to enable overcurrent detection on the left channel.
MOFFSETL: Set MOFFSETL to 1 to enable excessive-offset detection on the left-channel output.
MOPENL: Set MOPENL to 1 to enable open-load detection on the left channel.

12 _____________________________________________________________________________________

CODE
(HEX)

0x07 MSVDDL MSGNDL MLIMITL 0 MOFFSETL MOPENL x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

REGISTER DATA

POR

STATE

(HEX)

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

Right-Channel Mask Register

Table 10. Right-Channel Mask Register

ADDRESS

FUNCTION

Right-Channel
Mask Register

CODE
(HEX)

0x08 MSVDDR MSGNDR MLIMITR 0 MOFFSETR MOPENR x x 0x00

D7 D6 D5 D4 D3 D2 D1 D0

MSVDDR: Set MSVDDR to 1 to enable the short to VDD detection on the right channel.
MSGNDR: Set MSGNDR to 1 to enable the short to GND detection on the right channel.
MLIMITR: Set MLIMITR to 1 to enable overcurrent detection on the right channel.
MOFFSETR: Set MOFFSETR to 1 to enable excessive-offset detection on the right channel.
MOPENR: Set MOPENR to 1 to enable open-load detection on the right channel.

REGISTER DATA

MAX13325/MAX13326

POR

STATE

(HEX)

I2C and Stand-Alone Diagnostics

When the DIAG bit and the appropriate mask bits are set
to 1, the MAX13325/MAX13326 enter diagnostic mode.
In this mode, the MAX13325/MAX13326 detect short
to GND, short to battery, overcurrent condition, over­temperature condition, excessive offset, and report the
diagnosis using the I2C serial interface, FLAG bit, and
the FLAG output.

For stand-alone mode, there exists a 500ms stand-alone
fault retry function (for autoretry) until the fault goes
away. The FLAG output is pulsed to indicate a fault.

Output Short to V

When in diagnostic mode, the MAX13325/MAX13326
detect if any of the differential outputs is shorted to VDD
or battery. Upon detection of the short to VDD or battery,
the faulted channel is switched off and its output goes
into a high-impedance state. The fault is reported using
the I2C interface and the FLAG output. See Table 11.

Table 11. Output Short to V

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

FLAG is asserted low.

FLAG bit set. See Table 7.

Left-Channel Output
Short to V

Right-Channel
Output Short to V

DD

DD

SVDDL bit is set in the LFAULT

register. See Table 5.

Left channel switches off and output

goes to high-impedance state.

FLAG is asserted low.

FLAG bit set. See Table 7.

SVDDR bit is set in the RFAULT

register. See Table 6.

Right channel switches off and

output goes to high-impedance

/Battery Diagnostic

DD

state.

In LMASK register, set

MSVDDL bit to 1.

See Table 9.

Cannot be masked.

In RMASK register, set

MSVDDR bit to 1. See

Table 10.

Cannot be masked.

Cleared on reading the LFAULT

register. See Table 5.

Note: 500ms autoretry in stand-

alone mode.

Output is enabled by setting the

RETRYL bit to 1 in the Common

Byte register. See Table 3.

Cleared on reading the RFAULT

register. See Table 6.

Note: 500ms autoretry in stand-

alone mode.

Output is enabled by setting the

RETRYR bit to 1 in the Command

Byte register. See Table 3.

DD

______________________________________________________________________________________ 13

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

Output Short to GND

When in diagnostic mode, the MAX13325/MAX13326
detect if any of the differential outputs is shorted to
ground. Upon detection of the short to ground, the
faulted channel is switched off and its output goes into a

When in diagnostic mode, if the MAX13325/MAX13326
exceed the overtemperature warning or temperature shut­down thresholds the device reports the condition using
the I2C interface and the FLAG output. See Table 13.

high-impedance state. The fault is reported using the I2C
interface and the FLAG output. See Table 12.

Table 12. Output Short to GND Diagnostic

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

FLAG is asserted low.

FLAG bit set. See Table 7.

Left-Channel Output

Short to GND

MAX13325/MAX13326

Right-Channel Output

Short to GND

SGNDL bit is set in the LFAULT

register. See Table 5.

Left channel switches off and output

goes to high-impedance state.

FLAG is asserted low.

FLAG bit set. See Table 7.

SGNDR bit is set in the RFAULT

register. See Table 6.

Right channel switches off and

output goes to high-impedance

state.

In LMASK register, set

MSGNDL bit to 1. See

Table 9.

Cannot be masked.

In RMASK register, set
MSGNDR bit to 1. See

Table 10.

Cannot be masked.

Cleared on reading the LFAULT

register. See Table 5.

Note: 500ms autoretry in stand-

Output is enabled by setting the

RETRYL bit to 1 in the Command

Byte register. See Table 3.

Cleared on reading the RFAULT

register. See Table 6.

Note: 500ms autoretry in stand-

Output is enabled by setting the

RETRYR bit to 1 in the Command

Byte register. See Table 3.

Overtemperature

alone mode.

alone mode.

Table 13. Overtemperature Diagnostic

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

FLAG is asserted low.

Overtemperature

Warning

Overtemperature

Shutdown

14 _____________________________________________________________________________________

FLAG bit set. See Table 7.

TWARN bit is set in the GFAULT

register. See Table 4.

FLAG is asserted low.

FLAG bit set. See Table 7.

TSHDN bit is set in the GFAULT

Register. See Table 4.

Left and right channels switch

off and output goes to high-

impedance state.

In GMASK register, set

MTWARN bit to 1. See

Table 8.

In GMASK register, set

MTSHDN bit to 1. See

Table 8.

Cannot be masked.

Die temperature falls below warning

threshold.

Cleared on reading the GFAULT

register.

Die temperature falls below

shutdown threshold.

Cleared on reading the GFAULT

register.

Note: 500ms autoretry in stand-

alone mode.

Left channel is enabled by setting

the RETRYL bit to 1 in the Command

Byte register.

Right channel is enabled by

setting the RETRYR bit to 1 in the

Command Byte register.

See Table 3.

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

Excessive Offset

When in diagnostic mode with mute enabled, if there
is excessive offset on any output, the MAX13325/
MAX13326 reports the condition through the I2C inter­face and the FLAG output. See Table 14.

Overcurrent

When in diagnostic mode, if any of the output pairs is
excessively loaded, the MAX13325/MAX13326 issue a
warning and report the condition through the I2C inter­face and the FLAG output. The faulted channel is not
switched off. See Table 15.

Table 14. Excessive Offset Diagnostic

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Excessive Output

Offset on Left

Channel

Excessive Output

Offset on Right

Channel

FLAG is asserted low.

FLAG bit set. See Table 7.

OFFSETL bit is set in the LFAULT

register. See Table 5.

FLAG is asserted low.

FLAG bit set.

OFFSETR bit is set in the RFAULT

register. See Table 6.

When in diagnostic mode and the open-load detec­tion is initiated, the selected channel is switched off for
1ms during which the diagnosis is taking place. Upon
detecting an open load on any channel, the MAX13325/
MAX13326 report the condition using the I2C interface
and the FLAG output. See Table 16.

When in diagnostic mode, if the MAX13325/MAX13326
exceed the VDD overvoltage threshold (for example
during a load-dump condition), the device reports the
condition using the I2C interface and the FLAG output.
See Table 17.

In the LMASK register, set

MOFFSETL bit to 1. See

Table 9.

In the RMASK register, set

MOFFSETR bit to 1. See

Table 10.

Cleared on reading the LFAULT

register.

Cleared on reading the RFAULT

register.

Open Load

MAX13325/MAX13326

Overvoltage

Table 15. Overcurrent Diagnostic

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Overcurrent on Left

Channel

Overcurrent on Right

Channel

FLAG is asserted low.

FLAG bit set. See Table 7.

LIMITL bit is set in the LFAULT

register. See Table 5.

FLAG is asserted low.

FLAG bit set. See Table 7.

LIMITR bit is set in the RFAULT

register. See Table 6.

In the LMASK register,

set MLIMITL bit to 1. See

Table 9.

In the RMASK register,

set MLIMITR bit to 1. See

Table 10.

Load current falls below the

current-limit threshold.

Cleared on reading the LFAULT

register.

Load current falls below the

current-limit threshold.

Cleared on reading the RFAULT

register.

Table 16. Open-Load Diagnostic

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

Left-Channel Open

Load

Right-Channel Open

Load

______________________________________________________________________________________ 15

FLAG is asserted low.

FLAG bit set. See Table 7.

OPENL bit is set in the LFAULT

register. See Table 5.

FLAG is asserted low.

FLAG bit set. See Table 7.

OPENR bit is set in the RFAULT

register. See Table 6.

In the LMASK register,

set MOPENL bit to 1. See

Table 9.

In the RMASK register,

set MOPENR bit to 1. See

Table 10.

Cleared on reading

the LFAULT register.

Cleared on reading

the RFAULT register.

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

Table 17. Overvoltage Diagnostic

FAULT CONDITION STATUS REPORT UNMASK RECOVERY

FLAG is asserted low.

VDD voltage falls below overvoltage

threshold. Cleared on reading the

GFAULT register. Note: 500ms
autoretry in stand-alone mode.

Left channel is enabled by setting

the RETRYL bit to 1. Right channel

is enabled by setting the RETRYR

bit to 1. See Table 3.

Overvoltage

Shutdown

FLAG bit set. See Table 7.

DUMP bit is set in the GFAULT

register. See Table 4.

Left and right channels switch

off and output goes to a

high-impedance state.

In GMASK register, set

MDUMP bit to 1.

See Table 8.

Cannot be masked.

Applications Information

Serial Interface

Writing to the MAX13325/MAX13326 using I2C requires

MAX13325/MAX13326

that first the master sends a START (S) condition fol­lowed by the device’s I2C address. After the address,
the master sends the register address of the register
that is to be programmed. The master then ends com­munication by issuing a STOP (P) condition to relinquish

SDA

t

t

F

SCL

S

Figure 1. I2C Timing

t

LOW

t

HD:STA

t

LOW

t

HD:DAT

SU:DAT

t

HIGH

t

F

t

SU:STA

control of the bus, or a Repeated START (Sr) condition to
communicate to another I2C slave (see Figure 1).

Bit Transfer

Each SCL rising edge transfers one data bit. The data
on SDA must remain stable during the high portion of the
SCL clock pulse (see Figure 2). Changes in SDA while
SCL is high are read as control signals (see the START
and STOP Conditions section). When the serial interface
is inactive, SDA and SCL idle high.

t

HD:STA

r

t

SP

t

SU:STO

t

R

t

BUF

P

SS

SDA

SCL

DATA LINE

STABLE;

DATA VALID

CHANGE OF

DATA ALLOWED

Figure 2. Bit Transfer

16 _____________________________________________________________________________________

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

START and STOP Conditions

A master device initiates communication by issuing
a START condition, which is a high-to-low transition
on SDA with SCL high. A START condition from the
master signals the beginning of a transmission to the
MAX13325/MAX13326. The master terminates transmis­sion by a STOP condition (see the Acknowledge Bit
section). A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 3). The STOP condi­tion frees the bus. If a Repeated START condition is
generated instead of a STOP condition, the bus remains
active. When a STOP condition or incorrect slave ID is
detected, the device internally disconnects SCL from the

serial interface until the next START or Repeated START

MAX13325/MAX13326

condition, minimizing digital noise and feedthrough.

Acknowledge Bit

The acknowledge (ACK) bit is a clocked 9th bit that
the MAX13325/MAX13326 use to handshake receipt of
each byte of data when in write mode. The MAX13325/
MAX13326 pull down SDA during the entire master­generated 9th clock pulse if the previous byte is suc­cessfully received (see Figure 4). Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event

START

CONDITION

SDA

SCL

Figure 3. START/STOP Conditions

S

SDA

SCL

Figure 4. Acknowledge and Not-Acknowledge Bits

NOT ACKNOWLEDGE

ACKNOWLEDGE

1 8

STOP

CONDITION

9

Table 18. Slave Address

SLAVE

ADD1 ADD0 A6 A5 A4 A3 A2 A1 A0

GND GND — — — — — — — — — —

GND V

V
V
V
V

SCL V

SDA V

GND 1 1 0 0 0 1 0 1/0 0xC5 0xC4 I2C

L

L

SCL 1 1 0 0 1 0 0 1/0 0xC9 0xC8 I2C

L

SDA 1 1 0 0 1 0 1 1/0 0xCB 0xCA I2C

L

L

V

L

L

L

1 1 0 0 0 0 1 1/0 0xC3 0xC2 I2C

1 1 0 0 0 1 1 1/0 0xC7 0xC6 I2C

1 1 0 0 1 1 0 1/0 0xCD 0xCC I2C
1 1 0 0 1 1 1 1/0 0xCF 0xCE I2C

R/W

ADDRESS

READ
(HEX)

SLAVE

ADDRESS

WRITE

(HEX)

MODE

Stand-

alone

______________________________________________________________________________________ 17

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

of an unsuccessful data transfer, the bus master may
retry communication. The master must pull down SDA
during the 9th clock cycle to acknowledge receipt of
data when the MAX13325/MAX13326 are in read mode.
An acknowledge must be sent by the master after each
read byte to allow data transfer to continue. A not­acknowledge is sent when the master reads the final
byte of data from the MAX13325/MAX13326, followed by
a STOP condition.

Slave Address

The MAX13325/MAX13326 are programmable to one of
seven I2C slave addresses. These slave addresses are
unique device IDs. Connect ADD_ to GND, VL, SCL, or
SDA to set the I2C slave address. The address is defined
as the seven most significant bits (MSBs) followed by
the read/write bit. Set the read/write bit to 1 to configure
the MAX13325/MAX13326 to read mode. Set the read/
write bit to 0 to configure the device to write mode. The
address is the first byte of information sent after the

MAX13325/MAX13326

START condition.

Register Address Map

Single-Byte Write Operation

For a single-byte write operation, send the slave address
as the first byte followed by the register address and
then a single data byte (see Figure 5).

Burst Write Operation

For a burst write operation, send the slave address as
the first byte followed by the register address and then
the data bytes (see Figure 6).

Single-Byte Read Operation

For a single-byte read operation, send the slave address
with the read bit set, as the first byte followed by the reg­ister address. Then send a Repeated START condition
followed by the slave address. After the slave sends the
data byte, send a not-acknowledge followed by a STOP
condition (see Figure 7).

Burst Read Operation

For a burst read operation, send the slave address with
a write as the first byte followed by the register address.
Then send a Repeated START condition followed by the
slave address. The slave sends data bytes until a not­acknowledge condition is sent (see Figure 8).

S S7 S6 S5 S4 S3 S2 S1 ACK

SLAVE ADDRESS

B7 B6 B5 B4 B3 B2 B1 B0 ACK P

DATA 1

Figure 5. A Single-Byte Write Operation

S S7 S6 S5 S4 S3 S2 S1 ACK

SLAVE ADDRESS

B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

DATA 1

Figure 6. A Burst Write Operation

R/W

= 0

R/W

= 0

C7 C6 C5 C4 C3 C2 C1 C0 ACK

REGISTER ADDRESS

R7 R6 R5 R4 R3 R2 R1 R0 ACK

REGISTER ADDRESS

DATA 2

ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK P

DATA N

18 _____________________________________________________________________________________

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

S S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

SLAVE ADDRESS REGISTER ADDRESS

R/W

= 0

MAX13325/MAX13326

Sr S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 NACK P

SLAVE ADDRESS DATA

Figure 7. A Single-Byte Read Operation

S S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

SLAVE ADDRESS REGISTER ADDRESS

Sr S7 S6 S5 S4 S3 S2 S1 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK

SLAVE ADDRESS DATA 1

Figure 8. A Burst Read Operation

R/W

= 1

R/W

= 0

R/W

= 1

ACK B7 B6 B5 B4 B3 B2 B1 B0 NACK P

Charge Pump

The MAX13325/MAX13326 charge pump can be dis­abled depending on application requirements. When
charge pump is enabled [CPOFF = 0], please follow the
charge-pump capacitor selections. When the charge
pump is disabled [CPOFF = 1], the flying capacitor
(C1) is not needed. There are internal diodes between
V

OUT_ to CHOLD, so it is important that CHOLD

DD/

not be forced below VDD or any of the outputs. A series
diode needs to be placed between the external supply
(V

) and CHOLD. See D2 in the Typical Operating

SUP

Circuit.

Charge-Pump Capacitor Selection

Use ceramic capacitors with a low ESR for optimum per­formance. For optimal performance over the extended
temperature range, select capacitors with an X7R
dielectric. Table 19 lists suggested manufacturers.

DATA N

Flying Capacitor (C1)

The value of the flying capacitor (see the Typical
Operating Circuit) affects the charge pump’s load regu-

lation and output resistance. A C1 value that is too small
degrades the device’s ability to provide sufficient current
drive, which leads to a loss of output voltage. Increasing
the value of C1 improves load regulation and reduces
the charge-pump output resistance. For optimum perfor­mance, use a 470nF capacitor for C1. When the charge
pump is disabled [CPOFF = 1], the flying capacitor (C1)
is not needed.

Hold Capacitor (C2)

The hold capacitor value (see the Typical Operating
Circuit) and ESR directly affect the ripple at the internal

negative rail. Increasing the value of C2 reduces output
ripple. Likewise, decreasing the ESR of C2 reduces both
ripple and output resistance. Lower capacitance values
can be used in systems with low maximum output power
levels. For optimum performance, use a 1FF capacitor
for C2.

Table 19. Suggested Capacitor Vendors

SUPPLIER PHONE FAX WEBSITE

Murata 770-436-1300 770-436-3030 www.murata.com
Taiyo Yuden 800-348-2496 847-925-0899 www.t-yuden.com
TDK 847-803-6100 847-390-4405 www.component.tdk.com

______________________________________________________________________________________ 19

Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic

Power-Supply Bypass Capacitor (C3)

The power-supply bypass capacitor (see the Typical
Operating Circuit) lowers the output impedance of the

power supply, and reduces the impact of the MAX13325/
MAX13326 charge-pump switching transients. Bypass
VDD with C3, the same value as C2, and place it physi­cally close to the VDD and PGND pins.

Load-Dump Protection

With minimal external components, the MAX13325/
MAX13326 can be protected against automotive load­dump conditions. See the Typical Operating Circuit.

nMOSFET (Q1)

Q1 should be selected to withstand the full-voltage expo­sure (BV
should be chosen to be less than V
startup. Using an external nMOS, RTR020N05, 300ms
duration component provides 50V load-dump protection.

> 45V). The gate-source turn-on voltage

DSS

to ensure initial

CPS

MAX13325/MAX13326

Chip Information

PROCESS: BCD

Zener Diode (D1)

During short-to-battery condition, OUT_ lifts up CHOLD
using an internal diode. In order not to violate the maxi­mum gate-source voltage of Q1, a zener diode of appro­priate clamping voltage should be added between the
gate and source terminals.

Series Resistor (R1)

Normally, a series resistor for current limitation is needed
during short-to-battery condition. R1 should be chosen
according to (18V - V
excessive current is being drawn from CHOLD.

DD(min)

- V

)/1mA so that no

ZENER

Layout and Grounding

Proper layout and grounding are essential for optimum
performance. Connect the EP and GND together at a
single point on the PCB. Ensure ground return resistance
is minimized for optimum crosstalk performance.

Package Information

For the latest package outline information and land pat­terns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suf­fix character, but the drawing pertains to the package
regardless of RoHS status.

PACKAGE

TYPE

28 TSSOP-EP U28E+5

PACKAGE

CODE

OUTLINE

NO.

21-0108 90-0147

LAND PATTERN

NO.

20 _____________________________________________________________________________________

Dual Automotive, Audio Line Drivers

with I2C Control and Diagnostic

Revision History

MAX13325/MAX13326

REVISION

NUMBER

0 1/10 Initial release —
1 3/10 Updated the Typical Operating Circuit 1

2 4/10

3 6/10

REVISION

DATE

DESCRIPTION

Added new register bits to Tables 1, 2, and 7. Revised FLAG Register sec­tion and added Table 2a and Charge Pump section.

Introduced the MAX13326. Updated the Electrical Characteristics table
and added new Typical Operating Characteristics graphs.

PAGES

CHANGED

1, 4, 7, 8–12, 19, 20

1, 4, 5, 7

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.

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©

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