The MAX13301 combines four high-efficiency Class D
amplifiers with integrated diagnostic hardware for reliable automotive audio systems, and delivers up to 80W
at 10% THD+N per channel into 4I when operating from
a 24V supply.
The internal diagnostics evaluate each channel’s output
impedance to check for shorts across the outputs, to the
battery, or to ground. The I2C interface allows the system to query critical device parameters such as device
temperature and output clipping. The device is programmable to four different I2C addresses.
The audio amplifiers feature single-ended analog inputs
with a common negative input. The MAX13301 has a
fixed gain of 26dB.
The Class D amplifier has 10 programmable switching
frequencies between 300kHz and 750kHz.
The BTL outputs are protected against short circuits and
thermal overload. The outputs can be configured as a
2-, 3-, or 4-channel amplifier. The device provides 50V
load-dump protection, and is offered in the thermally
enhanced, 48-pin TSSOP-EPR package operating over
the -40NC to +125NC temperature range.
Applications
Car Stereo
Rear-Seat Entertainment Units
Discrete Amplifier Modules
Active Loudspeaker Systems
Radio Head Units
Mobile Surround Systems
Features
SHigh Output Power (10% THD+N)
2 x 160W into 2I at 24V
4 x 80W into 4I at 24V
S 2 Channels Can Be Paralleled
S Feedback After the Filter
S Four-Address I2C Control Interface
S Low-Power Shutdown Mode
S Up to 90.5% Efficiency
S-40°C to +125°C Ambient Operating Temperature
S48-Pin TSSOP-EPR (Top Side Exposed Pad) Package
SAEC-Q100 Qualified
MAX13301
Ordering Information
PARTPIN-PACKAGE
Typical Operating Circuit appears at end of data sheet.
MAX13301AUM/V+48 TSSOP-EPR*6 to 25.5
Note: The device operates over the -40°C to +125°C operating
temperature range.
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EPR = Top side exposed pad.
, CM to PGND ................................................. -0.3V to +6V
DD5
CP to PGND ........................(V
CHOLD to PVDD .....................................................-0.3V to +6V
OUT_ to PGND, FB_ to PGND ..............-0.3V to (V
VDD to GND ............................................................-0.3V to +6V
REF to GND ............................................................. -0.3V to +6V
MAX13301
SCL, SDA, SYNC to GND ........................................-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Note 2: The 48-pin TSSOP-EPR package has a top side exposed pad for enhanced thermal management. Connect this exposed
pad to an external heatsink to ensure the device is adequately cooled. The maximum power dissipation in the device is a
function of this external heatsink and other system parameters. See the Thermal Information section for more information.
MUTE_CL1, CL0, FLT_OT, EN to GND ...................-0.3V to +6V
IN_ to GND ..............................................................-0.3V to +6V
GND to PGND ......................................................-0.3V to +0.3V
= 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting),
PGND
P
= 10W, RL = 4I, BW = 22Hz to
OUT
20kHz AES17 filter, f = 1kHz
P
= 1W to 10W, RL = 4I, BW = 22Hz
OUT
to 20kHz AES17 filter, f = 1kHz
A-weighted, V
22Hz to 22kHz, V
A-weighted, CTRL5.SS[2:0] = 110,
SSEN = 1, V
= 4W, f = 1kHz to 10kHz60dB
OUT_
RL = 4I, P
VDD supplied from a switching power
supply
6 to 15 clock-divider range 300750kHz
CTRL2.STBY = 1, CTRL3.SDET = 16V
CTRL3.LDM = 1, power amplifier mode70100
CTRL3.LDM = 0, line-driver mode200300
15kHz < f < 25kHz,
TA = +25NC,
CTRL3.TW = 1
f < 20Hz,
CTRL3.TW = 0
No audio in play mode 0.561.041.6V
RL = 4I
OUT
= 24V 100
PVDD
= 24V140
PVDD
= 24V
PVDD
= 20W/channel, V
CTRL3.HCL = 0160291500
CTRL3.HCL = 1200364625
CTRL3.HCL = 00.651.151.85
CTRL3.HCL = 10.91.652.15
CTRL1.CLVL[1:0]
= 11
CTRL1.CLVL[1:0]
= 01
CTRL1.CLVL[1:0]
= 10
CTRL1.CLVL[1:0]
= 00
DD5
,
0.040.14
0.1
100
88%
1
3
5
10
%
FV
RMS
I
I
mA
A
%THDN
4
4-Channel, Automotive Class D Audio Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= 14.4V, VDD = V
PVDD
TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Short-to-Ground/PVDD
Level 1 Output Current LimitI
Level 2 Output Current LimitI
THERMAL PROTECTION
Thermal Warning Range 1Guaranteed monotonic110
Thermal Warning Range 2Guaranteed monotonic120
Thermal Warning Range 3Guaranteed monotonic130
Thermal Warning Range 4Guaranteed monotonic140
Thermal Shutdown LevelGuaranteed monotonic150165
Thermal Warning Hysteresis5
Thermal Shutdown Hysteresis15
CHARGE PUMP
Switching FrequencyfCP = f
Soft-Start Time100
Charge-Pump Output
Impedance
Output VoltageV
INTERNAL OSCILLATOR
SYNC I/O Frequency Range2x switching frequency0.61.5MHz
FrequencySpread-spectrum disabled17.11818.9MHz
DIGITAL INTERFACE (SCL, SDA, ADDR, CL0, MUTE_CL1, EN, SYNC, FLT_OT)
SYNC HighCTRL1.CM[1:0] = 01, I
SYNC LowCTRL1.CM[1:0] = 01, I
Input Voltage HighV
Input Voltage LowV
Input Voltage Hysteresis300mV
Input Leakage Current
Output Low Voltage
Pulldown Current
DD5
= 5V, V
GND
LIM1
LIM2
INH
INL
= V
= 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting),
PGND
OUT__ shorted
to ground/PVDD,
CTRL1.CL_TH = 1
OUT__ shorted
to ground/PVDD,
CTRL1.CL_TH = 0
CTRL3.HCL = 05.57A
CTRL3.HCL = 178.75A
SW
Guaranteed by FET R
measurement
SDA, SCL, CL0, MUTE_CL1, FLT_OT
SDA, CL0, MUTE_CL1, I
FLT_OT
MUTE_CL1
EN1018
CTRL3.HCL = 01.03
CTRL3.HCL = 11.28
CTRL3.HCL = 03.09
CTRL3.HCL = 13.86
300750kHz
DS(ON)
SOURCE
SINK
= 3mA4.5V
= 3mA0.4V
2.0V
= 3mA,
SINK
1.8
+ 5V
PVDD
513
NC
NC
NC
NC
NC
NC
NC
Fs
I
0.8V
Q10FA
0.4V
FA
MAX13301
A
5
4-Channel, Automotive Class D Audio Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= 14.4V, VDD = V
PVDD
TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I2C TIMING
Output Fall Timet
Pin Capacitance10pF
Clock Frequencyf
MAX13301
SCL Low Timet
SCL High Timet
START Condition Hold Timet
START Condition Setup Timet
Data Hold Timet
Data Setup Timet
Input Rise Timet
Input Fall Timet
STOP Condition Setup Timet
Bus Free Timet
Maximum Bus CapacitanceC
Note 3: All units are 100% production tested at TA = +25NC. All temperature limits are guaranteed by design.
DD5
= 5V, V
= V
GND
OF
SCL
LOW
HIGH
HD:STA
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
BUF
BUS
= 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting),
PGND
C
= 10pF to 400pF250ns
BUS
400kHz
1.3
0.6
Repeated START condition0.6
Repeated START condition0.6
0900ns
100ns
SCL, SDA300ns
SCL, SDA300ns
0.6
Between START and STOP conditions1.3
Per bus line400pF
Fs
Fs
Fs
Fs
Fs
Fs
6
4-Channel, Automotive Class D Audio Amplifier
Typical Operating Characteristics
(V
= 24V, VDD = V
PVDD
TA = +25NC, unless otherwise noted.)
THD+N vs. OUTPUT POWER
10
f = 1kHz
BW = 22Hz TO
20kHz AES17
R
= 4I
L
1
THD+N (%)
0.1
0.01
080
OUTPUT POWER (W)
DD5
= 5V, V
604020
GND
= V
MAX13301 toc01
= 0V, fSW = 500kHz, MAP.COMP[2:0] = 011, see Table 32 for LC filter value,
PGND
EFFICIENCY vs. OUTPUT POWER
PER CHANNEL
RL = 4I
RL = 2I
OUTPUT POWER PER CHANNEL (W)
2-CHANNEL
PARALLEL MODE
R
= 1I
L
fIN = 1kHz
10% THD+N
BW = 22Hz TO 20kHz AES17
10
1
THD+N (%)
0.1
0.01
THD+N vs. OUTPUT POWER
f = 1kHz
BW = 22Hz TO
20kHz AES17
PARALLEL MODE
RL = 2I
RL = 4I
OUTPUT POWER (W)
140120100806040200160
MAX13301 toc02
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
908010 20 3050 6040700100
MAX13301
MAX13301 toc03
EFFICIENCY vs. OUTPUT POWER
PER CHANNEL
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
090
OUTPUT POWER PER CHANNEL (W)
fIN = 1kHz
RL = 4I
10% THD+N
BW = 22Hz TO 20kHz AES1
OUTPUT POWER vs. SUPPLY VOLTAGE
100
RL = 4I
90
fIN = 1kHz
80
70
60
50
40
30
20
OUTPUT POWER PER CHANNEL(W)
10
0
10% THD+N
1% THD+N
10152025530
V
(V)
PVDD
POWER DISSIPATION vs. OUTPUT POWER
PER CHANNEL
40
35
MAX13301 toc04
30
25
20
15
POWER DISSIPATION (W)
10
5
807050 6020 30 4010
0
OUTPUT POWER PER CHANNEL (W)
RL = 2I
f
= 1kHz
IN
10% THD+N
BW = 22Hz TO 20kHz AES17
MAX13301 toc05
45405 10 1525 302035050
CROSSTALK
-40
P
= 4W
OUT
R
= 4I
L
-50
MAX13301 toc07
-60
-70
OUT0 TO OUT2
CROSSTALK (dB)
-80
-90
-100
0.01100
OUT0 TO OUT3
OUT0 TO OUT1
FREQUENCY (kHz)
1010.1
MAX13301 toc08
POWER DISSIPATION vs. OUTPUT POWER
PER CHANNEL
50
45
40
35
30
25
20
15
POWER DISSIPATION (W)
10
5
0
090
OUTPUT POWER PER CHANNEL (W)
fIN = 1kHz
RL = 4I
10% THD+N
BW = 22Hz TO 20kHz AES17
OUTPUT FREQUENCY SPECTRUM
0
MUTE MODE
R
= 4I
L
-20
-40
-60
AMPLITUDE (dBV)
-80
-100
-120
020
FREQUENCY (kHz)
MAX13301 toc06
807050 6020 30 4010
MAX13301 toc09
15105
7
4-Channel, Automotive Class D Audio Amplifier
Typical Operating Characteristics (continued)
(V
= 24V, VDD = V
PVDD
TA = +25NC, unless otherwise noted.)
DD5
= 5V, V
GND
= V
= 0V, fSW = 500kHz, MAP.COMP[2:0] = 011, see Table 32 for LC filter value,
PGND
3
2
MAX13301
1
0
RESPONSE (dB)
-1
-2
-3
SPREAD-SPECTRUM MODULATION WIDEBAND
0
-10
-20
-30
-40
-50
AMPLITUDE (dBV)
-60
-70
-80
-90
FREQUENCY RESPONSE
= 1W AND 10W
P
OUT
R
= 4I
L
P
= 30W
OUT
R
= 2I
L
C2 = 1µF
0.01100
FREQUENCY (kHz)
1010.1
OUTPUT SPECTRUM
CTRL5 = 0x09
MEASURED AT
OUT__ WITH -20dB
ATTENUATION
0.1100
FREQUENCY (MHz)
101
MAX13301 toc10
MAX13301 toc12
FIXED-FREQUENCY MODULATION WIDEBAND
OUTPUT SPECTRUM
0
-10
-20
-30
-40
-50
AMPLITUDE (dBV)
-60
-70
-80
-90
0.1100
MEASURED AT OUT__
WITH -20dB ATTENUATION
101
FREQUENCY (MHz)
SPREAD-SPECTRUM MODULATION WIDEBAND
OUTPUT SPECTRUM
0
-10
-20
-30
-40
-50
AMPLITUDE (dBV)
-60
-70
-80
-90
0.1100
WITH -20dB ATTENUATION
FREQUENCY (MHz)
CTRL5 = 0xB9
MEASURED AT OUT__
101
MAX13301 toc11
MAX13301 toc13
8
4-Channel, Automotive Class D Audio Amplifier
Pin Configuration
TOP VIEW
PVDD
FB2+
FB2-
FB3-
CL0
OUT3+
PGND
PGND
PGND
OUT2+
OUT2-
MUTE_CL1
IN-
GND
V
IN0+
IN1+
REF
PVDD
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DD
19
20
21
22IN2+
23IN3+
24
MAX13301
EPR
48
PVDD
47
CP
46
CHOLD
45
CMFB3+
V
44
DD5
PGND
43
OUT1+
42
OUT1-OUT3-
41
PGND
40
PGNDPGND
39
PGND
38
PGND
37
OUT0+
36
OUT0-
35
FLT_OT
34
FB0+
33
FB0-
32
FB1+
31
FB1-
30
SDA
29
SCL
28
EN
27
SYNC
26
PVDD
25
MAX13301
TSSOP
Pin Description
PINNAMEFUNCTION
Audio Output Power-Supply Input. Bypass each PVDD to its PGND pair locally with 0.1FF and 4.7FF
ceramic capacitors. Each PVDD/PGND pair consists of one PVDD and two PGNDs. The PVDD/
1, 24, 25, 48PVDD
2FB2+
3FB2-
PGND pairs are 1 and 9-10, 48 and 39-40, 24 and 11-12, and 25 and 37-38. Bypassing PVDD
locally minimizes the area of di/dt loops. An additional 1000FF, low-ESR electrolytic capacitor
should be placed from 1 and 48 to PGND and 24 and 25 to PGND.
Output 2 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor.
Output 2 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1%
resistor.
9
4-Channel, Automotive Class D Audio Amplifier
Pin Description (continued)
PINNAMEFUNCTION
4FB3+
5FB3-
6
MAX13301
7OUT3+Channel 3 Power Amplifier Positive Output
8OUT3-Channel 3 Power Amplifier Negative Output
9–12,
37–40, 43
13OUT2+Channel 2 Power Amplifier Positive Output
14OUT2-Channel 2 Power Amplifier Negative Output
15
16IN-
17GNDAnalog Ground
18V
19IN0+
20IN1+
21REF
22IN2+
23IN3+
26SYNC
27EN
28SCLI2C Serial-Clock Input
29SDAI2C Serial-Data Input and Output
30FB1-
31FB1+
32FB0-
33FB0+
CL0
PGNDAudio Output Power Ground
MUTE_CL1
DD
Output 3 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor.
Output 3 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1%
resistor.
Active-Low Open-Drain Clip 0 Output. CL0 is configurable to provide clipping indication for outputs
0 and 1 or for all four outputs.
Mute Input or Active-Low Open-Drain Clip 1 Output. MUTE_CL1 is configurable as a mute input or
as an open-drain clip indicator output. When configured as an input, drive MUTE_CL1 low to mute
all four outputs. As an output, MUTE_CL1 provides clipping indication for outputs 2 and 3. This
pin also selects the low bit of the I2C address and is latched upon the rising edge of the EN pin.
MUTE_CL1 has an internal 5FA pulldown.
Common Audio Negative Input. IN- has 5kI of input resistance. Bypass to analog ground with 2µF
or 4 x C
5V Analog Power-Supply Input. Bypass with a 2.2FF or larger ceramic capacitor to GND. V
provides power to the analog and digital circuitry.
Channel 0 Audio Input. IN0+ has 20kI of input resistance. Connect a series capacitor of at least
0.47FF to IN0+.
Channel 1 Audio Input. IN1+ has 20kI of input resistance. Connect a series capacitor of at least
0.47FF to IN1+.
2.2V Reference Output. Bypass REF to GND with a 1FF ceramic capacitor.
Channel 2 Audio Input. IN2+ has 20kI of input resistance. Connect a series capacitor of at least
0.47FF to IN2+.
Channel 3 Audio Input. IN3+ has 20kI of input resistance. Connect a series capacitor of at least
0.47FF to IN3+.
Sync I/O. In master mode, SYNC outputs a clock signal that is synchronized to that of the
modulator. In slave mode, SYNC is a clock input and serves as the clock source for the modulator.
Enable Input. Connect EN to VDD for normal operation. Connect EN to GND to place the device in a
low-power mode. There is an internal 10µA pulldown on EN.
Output 1 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1%
resistor.
Output 1 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor.
Output 0 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1%
resistor.
Output 0 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor.
IN_+
.
DD
10
4-Channel, Automotive Class D Audio Amplifier
Pin Description (continued)
PINNAMEFUNCTION
34
FLT_OT
35OUT0-Channel 0 Power Amplifier Negative Output
36OUT0+Channel 0 Power Amplifier Positive Output
41OUT1-Channel 1 Power Amplifier Negative Output
42OUT1+Channel 1 Power Amplifier Positive Output
Active-Low Open-Drain Fault and Overtemperature Output. FLT_OT provides indication of faults,
overtemperature, and thermal shutdown status.
5V Power-Supply Input. Bypass with a 0.1FF capacitor to PGND. V
provides power to the gate
DD5
drivers and charge pump.
Charge-Pump Output. Connect a 1FF capacitor from CHOLD to PVDD.
Top Side Exposed Pad. Connect this exposed pad to an external heatsink to ensure the device is
adequately cooled. The maximum power dissipation in the device is a function of this external
heatsink and other system parameters. See the Thermal Information section for more information.
The top side exposed pad is electrically isolated from the die.
MAX13301
Functional Diagram
V
DD5
PGND
IN_+
IN-
V
GND
REF
SCL
SDA
CLO
MUTE_CL1
FLT_OT
SYNC
OSC
DD
EN
ANALOG
AUDIO
INTERFACE
I2C CONTROL
INTERFACE
REGISTERS
AND
SYSTEM
CONTROL
ANALOG
MODULATOR
AND
DIAGNOSTICS
V
DD5
GATE
DRIVER 0
LPF
LPF
V
DD5
GATE
DRIVER 3
MAX13301
CLASS D
OUTPUT
STAGE 0
AND DIAGS
FEEDBACK
DIFF. AMP
FEEDBACK
DIFF. AMP
CLASS D
OUTPUT
STAGE 3
AND DIAGS
CHARGE
PUMP
PVDD
OUT0+
OUT0-
PGND
FB0+
FB0-
FB3+
FB3-
PVDD
OUT3+
OUT3-
PGND
CP
CM
CHOLD
11
4-Channel, Automotive Class D Audio Amplifier
2
C COMP
I
MAX13301
AUDIO IN
PWM LOGIC
TRIANGLE WAVE
REF
REF
PWM
COMPARATOR
REF
I2C COMP
ERROR
AMPLIFIER
REF
3-BIT ADC
FEED-
FORWARD
OSC
PVDD
REF
PREAMPLIFIER
Figure 1. Detailed Block Diagram of the MAX13301 Audio Path
Detailed Description
The MAX13301 4-channel, Class D audio power amplifiers is specifically designed for automotive applications.
Integrated feedback from the LC filter’s output improves
the THD+N by reducing the distortion, providing Class
AB performance while achieving efficiency up to 90.5%.
The devices also support spread-spectrum modulation
for AM radio compatibility.
Description of Operation
The device emulates current-mode controllers with digital
feed-forward (Figure 1). The internal oscillator creates an
18MHz square wave. The I2C controls a clock divider that
divides down this high-frequency clock to a usable frequency. The resulting square wave is integrated to create
12
a triangle wave. A 3-bit ADC converts the PVDD voltage
into a code that adjusts the resistors used in the trianglewave integrator. The triangle-wave amplitude becomes
progressively larger as PVDD increases. The triangle
wave is fed into the PWM comparator.
The two differential amplifiers provide both analog and
digital feedback. The feedback is summed with the output of the preamplifier at the error amplifier. The output
of the error amplifier is an AC replica of the inductor current (emulated current mode) and the triangle wave is
therefore the slope compensation. The PWM comparator
controls the full-bridge operation, turning on and off each
FET pair (double-edge modulation). To ensure that the
devices switch at the desired frequency, it is important
to ensure that the triangle wave is greater than the error-
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