MAXIM MAX13101E, MAX13102E, MAX13103E, MAX13108E User Manual

General Description

The MAX13101E/MAX13102E/MAX13103E/MAX13108E 16-bit bidirectional CMOS logic-level translators provide the level shifting necessary to allow data transfer in multivoltage systems. These devices are inherently bidirectional due to their design and do not require the use of a direction input. Externally applied voltages, VCCand VL, set the logic levels on either side of the devices. Logic signals present on the V

L

side of the device appear as a higher voltage logic signal on the VCCside of the device, and vice-versa.

The MAX13101E/MAX13102E/MAX13103E feature an enable input (EN) that, when low, reduces the V

CC

and VLsupply currents to less than 2µA. The MAX13108E features a multiplexing input (MULT) that selects one byte between the two, thus allowing multiplexing of the signals. The MAX13101E/MAX13102E/MAX13103E/ MAX13108E have ±15kV ESD protection on the I/O V

CC

side for greater protection in applications that route signals externally. Three different output configurations are available during shutdown, allowing the I/O on the V

CC

side or the VLside to be put in a high-impedance state or pulled to ground through an internal 6kΩ resistor.

The MAX13101E/MAX13102E/MAX13103E/MAX13108E accept VCCvoltages from +1.65V to +5.5V and V

L

voltages from +1.2V to VCC, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAX13101E/MAX13102E/ MAX13103E/MAX13108E are available in 36-bump WLP and 40-pin TQFN packages, and operate over the extended -40°C to +85°C temperature range.

Applications

Features

♦ Wide Supply Voltage Range

VCCRange of 1.65V to 5.5V VLRange of 1.2V to V

CC

♦ ESD Protection on I/O VCCLines

±15kV Human Body Model

♦ Up to 20Mbps Throughput ♦ Low 0.03µA Typical Quiescent Current ♦ WLP and TQFN Packages

MAX13101E/MAX13102E/MAX13103E/MAX13108E

16-Channel Buffered CMOS

Logic-Level Translators

________________________________________________________________

Maxim Integrated Products

1

Pin Configurations

19-3802; Rev 3; 6/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information/Selector Guide continued at end of data sheet.

Ordering Information/Selector Guide

PART PIN-PACKAGE

DATA

I/O VL STATE

I/O VCC STATE

MULTIPLEXER

FEATURE

MAX13101EEWX+*

36 WLP**

3.06mm x 3.06mm

20 High impedance 6kΩ to GND No

MAX13101EETL+

40 TQFN-EP***

20 High impedance 6kΩ to GND No

Note:

All devices are specified over the -40°C to +85°C operating temperature range.

MAX13101E MAX13102E MAX13103E

TQFN

+

TOP VIEW OF BOTTOM LEADS

56

4

3

I/O V

L

14

I/O V

L

16

V

L

V

CC

I/O VCC16

I/O V

L

13

I/O V

L

3

I/O V

L

1

V

L

I/O VL4

V

CC

I/O VCC1

11

12

I/O V

L

7

14

15

16

17

I/O V

L

8

I/O V

L

9

I/O V

CC

7

I/O V

CC

8

I/O V

CC

9

I/O V

CC

10

I/O VL15

I/O V

L

2

13

7

I/O V

L

10

I/O V

CC

11

8

*EXPOSED PAD CONNECTED TO GROUND

I/O V

L

11

I/O V

L

12

EN

I/O V

CC

12

GND

9 10

I/O V

L

6

2

I/O V

CC

6

I/O V

L

5

1

I/O V

CC

5

GND

26 25

27

28 24 23 22 212930

I/O VCC15

I/O V

CC

14

I/O V

CC

13

I/O V

CC

2

I/O V

CC

3

I/O V

CC

4

18

19

20

40

39

37

36

35

34

38

33

32

31

GND

*EP

CMOS Logic-Level Translation

Portable Equipment

Cell Phones

PDAs

Digital Still Cameras

Smart Phones

+

Denotes a lead-free/RoHS-compliant package.

*

Future product—contact factory for availability.

**

WLP bumps are in a 6 x 6 array.

***

EP = Exposed pad.

Pin Configurations continued at end of data sheet.

Typical Operating Circuit appears at end of data sheet.

5mm x 5mm x 0.8mm

RATE (Mbps)

DURING SHUTDOWN

MAX13101E/MAX13102E/MAX13103E/MAX13108E

16-Channel Buffered CMOS Logic-Level Translators

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= +1.65V to +5.5V, VL= +1.2V to VCC, EN = VL(MAX13101E/MAX13102E/MAX13103E), MULT = VLor GND (MAX13108E), T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VCC= +1.65V, VL= +1.2V, TA= +25°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(All voltages referenced to GND.) V

CC

...........................................................................-0.3V to +6V

V

L...........................................................................................

-0.3V to +6V

I/O V

CC_

......................................................-0.3V to (VCC+ 0.3V)

I/O V

L_.....................................................................

-0.3V to (VL+ 0.3V)

EN, MULT .................................................................-0.3V to +6V

Short-Circuit Duration I/O V

L_

, I/O V

CC_

to GND .......Continuous

Continuous Power Dissipation (T

A

= +70°C)

36-Bump WLP (derate 17.0mW/°C above +70°C).....1361mW

40-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range ............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER SUPPLIES

VL Supply Range V

L

1.2

V

VCC Supply Range V

CC

V

Supply Current from V

CC

I

QVCC

I/O VCC_ = GND, I/O VL _ = GND or I/O V

CC

_ = VCC, I/O VL _ = VL,

EN = V

L

, MULT = GND or V

L

10 µA

Supply Current from V

L

I

QVL

I/O VCC_ = GND, I/O VL _ = GND or I/O V

CC

_ = VCC, I/O VL _ = VL,

EN = V

L

, MULT = GND or V

L

20 µA

VCC Shutdown Supply Current

TA = +25°C, EN = GND, I/O VCC_ = GND, I/O V

L

_ = GND,

MAX13101E/MAX13102E/MAX13103E

1µA

VL Shutdown Supply Current I

SHDN-VL

TA = +25°C, EN = GND, I/O VCC_ = GND, I/O V

L

_ = GND,

MAX13101E/MAX13102E/MAX13103E

2µA

TA = +25°C, EN = GND, MAX13102E/MAX13103E

1

I/O VCC_ Tri-State Output Leakage Current

or M U LT = VL ( I/O V

C C

9 - I/O V

C C

16)

M AX13108E

1

µA

TA = +25°C, EN = GND, MAX13101E/ MAX13103E

1

I/O VL _ Tri-State Output Leakage Current

T

A

= +25°C, MULT = GND (I/O VL1 - I/O

V

L

8) or MULT = VL (I/OVL9 - I/O VL16)

MAX13108E

1

µA

I/O VL _ Pulldown Resistance During Shutdown

EN = GND, MAX13102E 4 10 kΩ

V

CC

1.65 5.50

I

SHDN-VCC

TA = + 25°C , M U LT = GN D (I/O V

0.03

1 - I/O V

C C

8)

0.03

0.02

MAX13101E/MAX13102E/MAX13103E/MAX13108E

16-Channel Buffered CMOS

Logic-Level Translators

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC= +1.65V to +5.5V, VL= +1.2V to VCC, EN = VL(MAX13101E/MAX13102E/MAX13103E), MULT = VLor GND (MAX13108E), T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VCC= +1.65V, VL= +1.2V, TA= +25°C.) (Notes 1, 2)

PARAMETER

CONDITIONS

I/O VCC_ Pulldown Resistance During Shutdown

EN = GND, MAX13101E 4 10 kΩ

EN or MULT Input Leakage Current

T

A

= +25°C 1 µA

LOGIC-LEVEL THRESHOLDS

I/O VL _ Input-Voltage High Threshold

V

IHL

2/3 x

V

L

V

I/O VL _ Input-Voltage Low Threshold

V

ILL

1/3 x

V

L

V

I/O VCC_ Input-Voltage High Threshold

V

IHC

2/3 x

V

I/O VCC_ Input-Voltage Low Threshold

V

ILC

1/3 x

V

EN, MULT Input-Voltage High Threshold

V

EN, MULT Input-Voltage Low Threshold

0.4 V

I/O VL _ Output-Voltage High V

OHL

V

I/O VL _ Output-Voltage Low V

OLL

0.4 V

I/O VCC_ Output-Voltage High V

OHC

V

I/O VCC_ Output-Voltage Low V

OLC

0.4 V

RISE/FALL-TIME ACCELERATOR STAGE

I/O VCC side

Transition-Detect Threshold

I/O V

L

side

V

Accelerator Pulse Duration VL = 1.2V, VCC = 1.65V 20 ns

VL = 1.2V, VCC = 1.65V 60

I/O VL _ Output-Accelerator Sink Impedance

V

L

= 5V, VCC = 5V 5

Ω

VL = 1.2V, VCC = 1.65V 15

I/O VCC_ Output-Accelerator Sink Impedance

V

L

= 5V, VCC = 5V 5

Ω

VL = 1.2V, VCC = 1.65V 30

I/O VL _ Output-Accelerator Source Impedance

V

L

= 5V, VCC = 5V 5

Ω

VL = 1.2V, VCC = 1.65V 20

I/O VCC_ Output-Accelerator Source Impedance

V

L

= 5V, VCC = 5V 7

Ω

ESD PROTECTION

I/O VCC_ Human Body Model

kV

SYMBOL

V

IH-SHDN

V

IL-SHDN

I/O V L _ sour ce cur r ent = 20µA, I/O V

I/O VL _ sink current = 20µA, I/O VCC_ ≤ V

I/O V

_ sour ce cur r ent = 20µA, I/O V L _ ≥ V

C C

I/O VCC_ sink current = 20µA, I/O VL _ ≤ V

_ ≥ V

C C

MIN TYP MAX UNITS

V

CC

- 0.4

IH C VL

ILC

IH L V C C

ILL

- 0.4

V

VL / 2

CC

±15

/ 2

VL - 0.4

V

CC

MAX13101E/MAX13102E/MAX13103E/MAX13108E

16-Channel Buffered CMOS Logic-Level Translators

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS

(VCC= +1.65V to +5.5V, VL= +1.2V to VCC, EN = VL(MAX13101E/MAX13102E/MAX13103E), MULT = VLor GND (MAX13108E), T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at VCC= +1.65V, VL= +1.2V, TA= +25°C.) (Notes 1, 2)

PARAMETER

CONDITIONS

I/O VL _ Rise Time t

RVL

RS = 50Ω, C

I/OVL_

= 15pF, t

RISE

≤ 3ns,

(Figures 2a, 2b)

15 ns

I/O VL _ Fall Time t

FVL

RS = 50Ω, C

I/OVL_

= 15pF, t

FALL

≤ 3ns,

(Figures 2a, 2b)

15 ns

I/O VCC_ Rise Time t

RVCC

RS = 50Ω, C

I/OVCC_

= 50pF, t

RISE

≤ 3ns,

(Figures 1a, 1b)

15 ns

I/O VCC_ Fall Time t

FVCC

RS = 50Ω, C

I/OVCC_

= 50pF, t

FALL

≤ 3ns,

(Figures 1a, 1b)

15 ns

Propagation Delay (Driving I/O V

L

_)

RS = 50Ω, C

I/OVCC_

= 50pF, t

RISE

≤ 3ns,

(Figures 1a, 1b)

20 ns

Propagation Delay (Driving I/O V

CC

_)

RS = 50Ω, C

I/OVL_

= 15pF, t

RISE

≤ 3ns,

(Figures 2a, 2b)

20 ns

Channel-to-Channel Skew t

SKEW

RS = 50Ω, C

I/OVCC_

= 50pF, C

I/OVL_

=

15pF, t

RISE

≤ 3ns

5ns

Part-to-Part Skew

RS = 50Ω, C

I/OVCC_

= 50pF, C

I/OVL_

=

10 ns

Propagation Delay from I/O V

L

_ to I/O VCC_ After EN

C

I/OVCC_

= 50pF (Figure 3) 1 µs

Propagation Delay from I/O V

CC

_ to I/O VL _ After EN

t

EN-VL

C

I/OVL_

= 15pF (Figure 4) 1 µs

Maximum Data Rate

R

SOURCE

= 50Ω, C

I/OVCC_

= 50pF,

C

I/OVL_

= 15pF, t

RISE

≤ 3ns

20

Note 1: All units are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by design

and not production tested.

Note 2: For normal operation, ensure that V

L

< (VCC+ 0.3V). During power-up, VL> (VCC+ 0.3V) does not damage the device.

Note 3: V

CC

from device 1 must equal VCCof device 2. VLfrom device 1 must equal VLof device 2.

Note 4: Guaranteed by design, not production tested.

SYMBOL

t

PVL-VCC

t

PVCC-VL

MIN TYP MAX UNITS

t

PPSKEW

t

EN-VCC

15pF, t

≤ 3ns, ΔTA = +20°C (Notes 3, 4)

RISE

Mbps

MAX13101E/MAX13102E/MAX13103E/MAX13108E

16-Channel Buffered CMOS

Logic-Level Translators

_______________________________________________________________________________________ 5

Test Circuits/Timing Diagrams

MAX13101E MAX13102E MAX13103E MAX13108E

SOURCE

R

S

6kΩ

ALL UNUSED I/O V

CC_

AND I/O VL_ CONNECTED TO GND

I/O V

L_

EN/(MULT)

V

L

V

CC

I/O V

CC_

C

I/OVCC_

( ) ARE FOR THE MAX13108E

t

PHL

t

PLH

50%

90%

10%

I/O V

CC_

I/O V

L_

90%

50%

10%

90%

50%

10%

t

RISE/FALL

≤ 3ns

t

FVCC

t

PVL-VCC

= t

PHL

or t

PLH

t

RVCC

SOURCE

R

S

I/O V

L_

EN/(MULT)

V

L

V

CC

I/O V

CC_

C

I/OVL_

MAX13101E MAX13102E MAX13103E MAX13108E

6kΩ

ALL UNUSED I/O V

CC_

AND I/O V

L_

CONNECTED TO GND

( ) ARE FOR THE MAX13108E

t

PHL

t

PLH

I/O V

L_

I/O V

CC_

90%

50%

10%

90%

50%

10%

50%

90%

10%

t

RISE/FALL

≤ 3ns

t

FVL

t

RVL

t

PVCC-VL

= t

PHL

or t

PLH

Figure 1a. Driving I/O V

L_

Figure 1b. Timing for Driving I/O V

L_

Figure 2a. Driving I/O V

CC_

Figure 2b. Timing for Driving I/O V

CC_

MAX13101E/MAX13102E/MAX13103E/MAX13108E

16-Channel Buffered CMOS Logic-Level Translators

6 _______________________________________________________________________________________

Test Circuits/Timing Diagrams (continued)

SOURCE

I/O V

CC_

100kΩ

I/O V

L_

C

I/OVCC

V

L

EN/(MULT)

I/O V

L_

I/O V

CC_

t

EN-VCC

V

L

V

L

V

CC

0

V

CC 2

MAX13101E MAX13102E MAX13103E MAX13108E

EN/(MULT)

( ) ARE FOR THE MAX13108E

6kΩ

Figure 3. Propagation Delay from I/O VL_to I/O V

CC_

After EN

I/O V

CC_

I/O V

L_

C

I/OVL

100kΩ

V

CC

EN/(MULT)

I/O V

L_

I/O V

CC_

t

EN-VL

V

L

V

L

V

CC

0

V

L

2

SOURCE

MAX13101E MAX13102E MAX13103E MAX13108E

EN/(MULT)

( ) ARE FOR THE MAX13108E

6kΩ

Figure 4. Propagation Delay from I/O V

CC_

to I/O VL_After EN