Maxim MAX1294BEEI, MAX1294BCEI, MAX1294AEEI, MAX1294ACEI, MAX1296BEEG Datasheet

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General Description

The MAX1294/MAX1296 low-power, 12-bit analog-to­digital converters (ADCs) feature a successive-approxi­mation ADC, automatic power-down, fast wake-up
(2µs), on-chip clock, +2.5V internal reference, and
high-speed 12-bit parallel interface. They operate with
a single +5V analog supply.

Power consumption is only 10mW at the maximum sam­pling rate of 420ksps. Two software-selectable power­down modes enable the MAX1294/MAX1296 to be shut
down between conversions; accessing the parallel
interface returns them to normal operation. Powering
down between conversions can reduce supply below
10µA at lower sampling rates.

Both devices offer software-configurable analog inputs for
unipolar/bipolar and single-ended/pseudo-differential
operation. In single-ended mode, the MAX1294 has six
input channels and the MAX1296 has two (three input
channels and one input channel, respectively, when in
pseudo-differential mode).

Excellent dynamic performance and low power combined
with ease of use and small package size make these con­verters ideal for battery-powered and data-acquisition
applications or for other circuits with demanding power­consumption and space requirements. The MAX1294 is
offered in a 28-pin QSOP package, while the MAX1296
is available in a 24-pin QSOP. For pin-compatible +3V,
12-bit versions, see the MAX1295/MAX1297.

Applications

Industrial Control Systems Data Logging
Energy Management Patient Monitoring
Data-Acquisition Systems Touchscreens

Features

♦ 12-Bit Resolution, ±0.5LSB Linearity
♦ Single +5V Operation
♦ Internal +2.5V Reference
♦ Software-Configurable Analog Input Multiplexer

6-Channel Single-Ended/
3-Channel Pseudo-Differential (MAX1294)

2-Channel Single-Ended/
1-Channel Pseudo-Differential (MAX1296)

♦ Software-Configurable Unipolar/Bipolar

Analog Inputs

♦ Low Current

2.0mA (420ksps)

1.0mA (100ksps)
400µA (10ksps)
2µA (shutdown)

♦ Internal 6MHz Full-Power Bandwidth Track/Hold
♦ Parallel 12-Bit Interface
♦ Small Footprint

28-Pin QSOP (MAX1294)
24-Pin QSOP (MAX1296)

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________

Maxim Integrated Products

1

19-1533; Rev 0; 9/99

PART

MAX1294ACEI

MAX1294BCEI 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

28 QSOP
28 QSOP

Ordering Information

Pin Configurations

INL

(LSB)

±0.5
±1

Typical Operating Circuits appear at end of data sheet.

Pin Configurations continued at end of data sheet.

MAX1294AEEI -40°C to +85°C 28 QSOP ±0.5
MAX1294BEEI -40°C to +85°C 28 QSOP ±1

EVALUATION KIT

AVAILABLE

MAX1296ACEG

MAX1296BCEG
MAX1296AEEG -40°C to +85°C

0°C to +70°C

0°C to +70°C 24 QSOP

24 QSOP
24 QSOP ±0.5

MAX1296BEEG -40°C to +85°C 24 QSOP ±1

±0.5
±1

TOP VIEW

1

D9

2

D8

3

D7

4

D6

5

D5

D4

D3

D2

D1

D0

INT

MAX1296

6

7

8

9

10

11

12

QSOP

24

23

22

21

20

19

18

17

16

15

14

13

D10

D11

V

DD

REF

REFADJ

GND

COM

CH0

CH1

CS

CLK

WRRD

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±10%, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 7.6MHz (50% duty cycle),

T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

CH0–CH5, COM to GND............................-0.3V to (VDD+ 0.3V)

REF, REFADJ to GND.................................-0.3V to (VDD+ 0.3V)

Digital Inputs to GND ...............................................-0.3V to +6V

Digital Outputs (D0–D11, INT) to GND.......-0.3V to (V

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW

28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW

Operating Temperature Ranges

MAX1294_C_ _/MAX1296_C_ _.........................0°C to +70°C

MAX1294_E_ _/MAX1296_E_ _ ......................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

External acquisition or external clock mode

Internal acquisition/internal clock mode

MAX129_A

External acquisition/internal clock mode

External clock mode

-3dB rolloff

SINAD > 68dB

fIN= 175kHz (Note 4)

f

IN1

= 49kHz, f

IN2

= 52kHz

MAX129_B
No missing codes over temperature

CONDITIONS

ns25Aperture Delay

ns400t

ACQ

T/H Acquisition Time

3.2 3.6 4

2.5 3.0 3.5

µs

2.1

t

CONV

Conversion Time (Note 5)

MHz

6

Full-Power Bandwidth

kHz

350

Full-Linear Bandwidth

dB

-78

Channel-to-Channel Crosstalk

dB

76

IMDIntermodulation Distortion

dB

-80

SFDRSpurious-Free Dynamic Range

Total Harmonic Distortion
(including 5th-order harmonic)

dB

-80

THD

±0.5

INLRelative Accuracy (Note 2)

Bits

12

RESResolution

dB

67 70

SINADSignal-to-Noise Plus Distortion

LSB

±0.2

Channel-to-Channel Offset
Matching

ppm/°C

±2.0

Gain Temperature Coefficient

LSB

±1

LSB

±1

DNLDifferential Nonlinearity

LSB

±4

Offset Error

LSB

±4

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

Internal acquisition/internal clock mode

External acquisition or external clock mode

<200

ps

<50

Aperture Jitter

MHz0.1 7.6f

CLK

External Clock Frequency

%30 70Duty Cycle

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (f

IN(sine wave)

= 50kHz, VIN= 2.5Vp-p, 420ksps, external f

CLK

= 7.6MHz, bipolar input mode)

CONVERSION RATE

I

DD

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±10%, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 7.6MHz (50% duty cycle),

T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

Shutdown mode

V

REF

= 2.5V, f

SAMPLE

= 420ksps

0 to 0.5mA output load

To power down the internal reference

For small adjustments

On/off-leakage current, VIN= 0 or V

DD

Unipolar, V

COM

= 0

Bipolar, V

COM

= V

REF

/2

2

µA

200 300

I

REF

V

1.0

V

DD

+

50mV

V

REF

REF Input Voltage Range

µF

4.7 10

Capacitive Bypass at REF

µF

0.01 1

Capacitive Bypass at REFADJ

mV/mA

0.2 0.5

Load Regulation (Note 7)

V

VDD- 1

REFADJ High Threshold

mV

±100

REFADJ Input Range

ppm/°C

±20

TC

REF

REF Temperature Coefficient

mA

15

REF Short-Circuit Current

V

2.49 2.5 2.51

REF Output Voltage

pF

12

C

IN

Input Capacitance

µA

±0.01 ±1

Multiplexer Leakage Current

V

0 V

REF

V

IN

Analog Input Voltage Range
Single-Ended and Differential
(Note 6)

-V

REF

/2 +V

REF

/2

CS = V

DD

I

SOURCE

= 1mA

I

SINK

= 1.6mA

VIN= 0 or V

DD

µA

±0.1 ±1

I

LEAKAGE

Three-State Leakage Current

V

VDD- 0.5

V

OH

Output Voltage High

V

0.4

V

OL

Output Voltage Low

pF

15

C

IN

Input Capacitance

µA

±0.1 ±1

I

IN

Input Leakage Current

mV

200

V

HYS

Input Hysteresis

V

0.8

V

IL

Input Voltage Low

V

4.0

V

IH

Input Voltage High

CS = V

DD

V

4.5 5.5

V

DD

Analog Supply Voltage

pF

15

C

OUT

Three-State Output Capacitance

2.6 2.9

REF Input Current

µA

External reference

2.2 2.5

External reference

0.5 0.8

mA

Internal reference

1.0 1.2

Power-Supply Rejection PSR VDD= 5V ±10%, full-scale input

±0.3 ±0.7

mV

Positive Supply Current I

DD

Shutdown mode

210

µA

ANALOG INPUTS

INTERNAL REFERENCE

EXTERNAL REFERENCE AT REF

DIGITAL INPUTS AND OUTPUTS

POWER REQUIREMENTS

Internal reference

Operating mode,
f

SAMPLE

= 420ksps

Standby mode

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

4 _______________________________________________________________________________________

t

TR

10 40

nsC

LOAD

= 20pF, Figure 1

RD Rise to Output Disable

WR to CLK Fall Setup Time

t

CWS

60

ns

nsCLK Pulse Width High

nsCLK Period

t

CH

40

RD Fall to Output Data Valid

t

DO

10 50

ns

RD Fall to INT High Delay

t

INT1

50

ns

CS Fall to Output Data Valid

t

DO2

100

ns

C

LOAD

= 20pF, Figure 1

C

LOAD

= 20pF, Figure 1

C

LOAD

= 20pF, Figure 1

t

CP

132

CLK Pulse Width Low t

CL

40

ns

Data Valid to WR Rise Time

t

DS

40

ns

WR Rise to Data Valid Hold Time

t

DH

0

ns

CLK Fall to WR Hold Time

t

CWH

40

ns

CS to CLK or WR Setup Time

t

CSWS

40

ns

CLK or WR to CS Hold Time

t

CSWH

0

ns

CS Pulse Width

t

CS

100

ns

WR Pulse Width (Note 8)

t

WR

60

ns

t

TC

10 60

nsC

LOAD

= 20pF, Figure 1

PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS

CS Rise to Output Disable

Note 1: Tested at VDD= +5V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V

DD

.

Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.

TIMING CHARACTERISTICS

(VDD= +5V ±10%, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 7.6MHz (50% duty cycle),

T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Figure 1. Load Circuits for Enable/Disable Times

V

DD

3k

DOUT

3k

GND GND

a) High-Z to VOH and VOL to V

C

LOAD

20pF

OH

DOUT

b) High-Z to VOL and VOH to V

C

LOAD

20pF

OL

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(VDD= +5V, V

REF

= +2.500V, f

CLK

= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)

0.1

1k

100k

101100

10k

1M

SUPPLY CURRENT vs. SAMPLE FREQUENCY

MAX1294/6-02A

f

SAMPLE

(Hz)

I

DD

(µA)

0

10

100

1000

10,000

WITH EXTERNAL REFERENCE

WITH INTERNAL REFERENCE

INTEGRAL NONLINEARITY vs.

DIGITAL OUTPUT CODE

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5
0 20001000 3000 4000 5000

DIGITAL OUTPUT CODE

SUPPLY CURRENT vs. SUPPLY VOLTAGE

2.2
R

= ∞

L

CODE = 101010100000

2.1

(mA)

2.0

DD

I

1.9

DIFFERENTIAL NONLINEARITY vs.

DIGITAL OUTPUT CODE

0 20001000 3000 4000 5000

DIGITAL OUTPUT CODE

SUPPLY CURRENT vs. TEMPERATURE

R

= ∞

L

CODE = 101010100000

MAX1294/6-01

MAX1294/6 toc03

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5

2.3

2.2

2.1

(mA)

2.0

DD

I

1.9

1.8

MAX1294/6-02

MAX1294/6 toc04

STANDBY CURRENT vs. SUPPLY VOLTAGE

990

980

970

(µA)

DD

960

STANDBY I

950

940

MAX1294/6 toc05

1.8

4.50 5.004.75 5.25 5.50

STANDBY CURRENT vs. TEMPERATURE

990

980

970

(µA)

DD

960

STANDBY I

950

940

930

-40 10-15 35 60 85
TEMPERATURE (°C)

MAX1290/2 toc07

930

4.50 5.004.75 5.25 5.50
VDD (V)

POWER-DOWN CURRENT

vs. TEMPERATURE

2.2

2.1

(µA)

DD

2.0

POWER-DOWN I

1.9

1.8

-40 10-15 35 60 85
TEMPERATURE (°C)

VDD (V)

MAX1294/6 toc06

1.7

-40 10-15 35 60 85
TEMPERATURE (°C)

POWER-DOWN CURRENT

vs. SUPPLY VOLTAGE

3.0

2.5

(µA)

DD

2.0

POWER-DOWN I

1.5

1.0

4.50 5.004.75 5.25 5.50

VDD (V)

MAX1294/6 toc08

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= +5V, V

REF

= +2.500V, f

CLK

= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)

2.48

2.49

2.50

2.52

2.51

2.53

REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1294/6-10

TEMPERATURE (°C)

V

REF

(V)

-40 35-15 10 60 85

-1.0

0

-0.5

0.5

1.0

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX1294/6 toc11

VDD (V)

OFFSET ERROR (LSB)

4.50 5.004.75 5.25 5.50

-2

-1

0

1

2

OFFSET ERROR vs. TEMPERATURE

MAX1294/6 toc12

TEMPERATURE (°C)

OFFSET ERROR (LSB)

-40 35 60-15 10 85

-2

0

-1

1

2

GAIN ERROR vs. SUPPLY VOLTAGE

MAX1294/6 toc13

VDD (V)

GAIN ERROR (LSB)

4.50 5.004.75 5.25 5.50

0

0.5

1.0

1.5

2.0

GAIN ERROR vs. TEMPERATURE

MAX1294/6 toc14

TEMPERATURE (°C)

GAIN ERROR (LSB)

-40 35 60-15 10 85

2.48

2.49

2.51

2.50

2.52

2.53

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX1294/6-09

VDD (V)

V

REF

(V)

4.50 5.004.75 5.25 5.50

-140

-120

-100

-80

-60

-40

-20

0

20

0 200 400 600 800 1000

FFT PLOT

MAX1294/6-15

FREQUENCY (kHz)

AMPLITUDE (dB)

V

DD

= 5V

f

IN

= 50kHz

f

SAMPLE

= 400ksps

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 7

Pin Description

D01010

INT

1111

RD

1212

WR

1313

CLK1414

D466

D377

D288

D199

D555

D644

1

D733

D822

D9

1

Three-State Digital I/O Line (D0)

INT goes low when the conversion is complete and output data is ready.

Active-Low Read Select. If CS is low, a falling edge on RD will enable the read
operation on the data bus.

Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver­sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.

Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either VDDor GND.

Three-State Digital I/O Line (D4)

Three-State Digital I/O Line (D3)

Three-State Digital I/O Line (D2)

Three-State Digital I/O Line (D1)

Three-State Digital I/O Line (D5)

Three-State Digital I/O Line (D6)

Three-State Digital I/O Line (D7)

Three-State Digital Output (D8)

Three-State Digital Output (D9)

GND1923

REFADJ2024

CH2—19

CH11620

CH01721

COM1822

CH3—18

CH4—17

CH5—16

CS

1515

Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with

a 0.01µF capacitor. When using an external reference, connect REFADJ to VDDto
disable the internal bandgap reference.

Analog Input Channel 2

Analog Input Channel 1

Analog Input Channel 0

Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5LSB during conversion.

Analog Input Channel 3

Analog Input Channel 4

Analog Input Channel 5

Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high
impedance.

PIN

MAX1296MAX1294

NAME FUNCTION

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

8 _______________________________________________________________________________________

Pin Description (continued)

PIN

MAX1296

REF

2125

MAX1294

NAME

Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.

FUNCTION

26 22 V

DD

Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.

27 23 D11 Three-State Digital Output (D11)

28 24 D10 Three-State Digital Output (D10)

_______________Detailed Description

Converter Operation

The MAX1294/MAX1296 ADCs use a successive-approx­imation (SAR) conversion technique and an input

track/hold (T/H) stage to convert an analog input signal to
a 12-bit digital output. This output format provides easy
interface to standard microprocessors (µPs). Figure 2
shows the simplified internal architecture of the MAX1294/
MAX1296.

Figure 2. Simplified Functional Diagram

(CH5)
(CH4)
(CH3)
(CH2)

CH1
CH0

COM

CLK

ANALOG

INPUT

MULTIPLEXER

CLOCK

REF REFADJ

AV =

2.05

T/H

CHARGE REDISTRIBUTION

12-BIT DAC

12

SUCCESSIVE-

APPROXIMATION

REGISTER

17k

COMP

1.22V

REFERENCE

CS

WR

RD

INT

( ) ARE FOR MAX1294 ONLY.

CONTROL LOGIC

&

LATCHES

MAX1294
MAX1296

12

THREE-STATE, BIDIRECTIONAL

I/O INTERFACE

D0–D11

12-BIT DATA BUS

V

GND

DD

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 9

BIT

PD1, PD0

0

D7, D6

PD1 and PD0 select the various clock and power-down modes.

Full Power-Down Mode. Clock mode is unaffected.

D5 ACQMOD

ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode

NAME FUNCTIONAL DESCRIPTION

0
10

Standby Power-Down Mode. Clock mode is unaffected.

0
11

Normal Operation Mode. External clock mode selected.

1

Normal Operation Mode. Internal clock mode selected.

D4

SGL/DIF

SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2, 4).

D3

UNI/BIP

UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V

REF

can be converted; in bipolar mode, the

signal can range from -V

REF

/2 to +V

REF

/2.

D2, D1, D0 A2, A1, A0

Address bits A2, A1, A0 select which of the 6/2 (MAX1294/MAX1296) channels is to be converted
(see Tables 2, 3).

Table 1. Control-Byte Functional Description

Single-Ended and

Pseudo-Differential Operation

The sampling architecture of the ADCs’ analog com­parator is illustrated in the equivalent input circuits of
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1294
(Figure 3a) and to CH0–CH1 for the MAX1296 (Figure
3b), while IN- is switched to COM (Table 2). In differen-

tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
the analog inputs. This configuration is pseudo-differen­tial to the effect that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5LSB
(±0.1LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a

0.1µF capacitor from IN- (the selected input) to GND.

Figure 3a. MAX1294 Simplified Input Structure Figure 3b. MAX1296 Simplified Input Structure

12-BIT CAPACITIVE DAC

V

REF

INPUT

C

HOLD

MUX

–

C

SWITCH

12pF

+

TRACK

SWITCH

T/H

R

IN

800Ω

HOLD

CH0

CH1

CH2

CH3

CH4

CH5

COM

SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1 AND CH2/CH3, AND CH4/CH5

COMPARATOR

ZERO

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.

12-BIT CAPACITIVE DAC

V

REF

INPUT

C

HOLD

MUX

–

C

SWITCH

12pF

TRACK

SWITCH

+

R

IN

800Ω

HOLD

T/H

CH0

CH1

COM

SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR

CH0/CH1.

COMPARATOR

ZERO

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

10 ______________________________________________________________________________________

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C

HOLD

. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on C

HOLD

as a sample of the

signal at IN+.
The conversion interval begins with the input multiplex-

er switching C

HOLD

from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to­analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(VIN+ - VIN-)] charge from C

HOLD

to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.

Analog Input Protection

Internal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).

If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current
to 4mA.

Track/Hold

The MAX1294/MAX1296 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next on ris­ing edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that in internal clock
mode this is approximately 1µs after writing the control
byte.

In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega­tive input “-”, and the difference of |(IN+) - (IN-)|is sam­pled. At the beginning of the next conversion, the
positive input connects back to IN+ and C

HOLD

charges to the input signal.
The time required for the T/H stage to acquire an input

signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,

A1 CH0

0 +00

A0

0 1

CH2* CH4*

+0

1 0 +

CH3*

0

CH1

1

CH5*

1 +0

0 0

A2

+1

0 1 +1

Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)

Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)

A1 CH0

0 +00

A0

0 1

CH2* CH4*

+0

1 0 + -

CH3*

0

CH1

1

CH5*

1 +0

0 0

A2

+ -1

0 1 - +1

*

Channels CH2–CH5 apply to MAX1294 only.

*

Channels CH2–CH5 apply to MAX1294 only.

-

-

-

COM

-

-

-

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 11

the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
t

ACQ

, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow­ing equation:

t

ACQ

= 9 (RS+ RIN)C

IN

where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the ADC’s input capacitance. Source impedances
below 3kΩ have no significant impact on the MAX1294/
MAX1296’s AC performance.

Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.

Input Bandwidth

The MAX1294/MAX1296 T/H stage offers a 350kHz full­linear and a 6MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADCs
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre­quency band of interest, anti-alias filtering is recom­mended.

Starting a Conversion

Initiate a conversion by writing a control byte, which
selects the multiplexer channel and configures the
MAX1294/MAX1296 for either unipolar or bipolar opera­tion. A write pulse (WR + CS) can either start an acqui­sition interval or initiate a combined acquisition plus
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle will abort the conversion and start a
new acquisition interval.

Internal Acquisition

Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)

ends (Figure 4). Note that when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.

External Acquisition

Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi­tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).

The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see

Power-Down

Modes

section). Changing other bits in the control byte

will corrupt the conversion.

Reading a Conversion

A standard interrupt signal INT is provided to allow the
MAX1294/MAX1296 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4, 5). It returns high on the first read
cycle or if a new control byte is written.

Selecting Clock Mode

The MAX1294/MAX1296 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1294/MAX1296
enter the default external clock mode.

Internal Clock Mode

Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bits D6
and D7 of the control byte must be set to 1; the internal
clock frequency is then selected, resulting in a conver­sion time of 3.6µs. When using the internal clock mode,
tie the CLK pin either high or low to prevent the pin
from floating.

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

12 ______________________________________________________________________________________

Figure 5. Conversion Timing Using External Acquisition Mode

Figure 4. Conversion Timing Using Internal Acquisition Mode

t

CS

t

CSWS

t

WR

t

ACQ

t

CONV

t

DH

t

DS

t

INT1

t

D0

t

TR

HIGH-ZHIGH-Z

CS

WR

D11–D0

INT

RD

DOUT

ACQMOD ="0"

VALID DATA

CONTROL

BYTE

t

CSWH

t

CS

CS

WR

D11–D0

INT

RD

DOUT

t

CSWS

t

DS

HIGH-Z

t

WR

CONTROL

BYTE

ACQMOD = "1"

t

CSLOH

t

DH

t

ACQ

ACQMOD = "0"

CONTROL

BYTE

t

CONV

t

NT1

t

D0

VALID DATA

t

TR

HIGH-Z

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 13

External Clock Mode

To select external clock mode, bits D6 and D7 of the
control byte must be set to zero. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an exter­nal clock. For proper operation, a 100kHz to 7.6MHz
clock frequency with 30% to 70% duty cycle is recom­mended. Operating the MAX1294/MAX1296 with clock
frequencies lower than 100kHz is not recommended
because the resulting voltage droop across the hold
capacitor in the T/H stage will degrade performance.

Digital Interface

The input and output data are multiplexed on a three­state parallel interface (I/O) that can easily be inter­faced with standard µPs. The signals CS, WR, and RD
control the write and read operations. CS represents
the chip-select signal, which enables a µP to address
the MAX1294/MAX1296 as an I/O port. When high, CS
disables the CLK, WR, and RD inputs and forces the
interface into a high-impedance (high-Z) state.

Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)

Figure 6b. External Clock and WR Timing (External Acquisition Mode)

WR

CLK

CLK

WR

WR GOES HIGH WHEN CLK IS HIGH

WR GOES HIGH WHEN CLK IS LOW

t

CWS

t

CH

t

CL

t

CP

t

CWH

ACQUISITION STARTS

ACQUISITION STARTS

CONVERSION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQUISITION ENDS

ACQMOD = "0"

ACQMOD = "0"

ACQUISITION STARTS

CLK

t

DH

WR

ACQMOD = "1"

ACQUISITION STARTS

t

DH

CLK

WR

ACQMOD = "1"

WR GOES HIGH WHEN CLK IS HIGH

ACQUISITION ENDS

WR GOES HIGH WHEN CLK IS LOW

ACQUISITION ENDS

ACQMOD = "0"

t

CWH

ACQMOD = "0"

t

CONVERSION STARTS

CWS

CONVERSION STARTS

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

14 ______________________________________________________________________________________

Input Format

The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.

Output Data Format

The 12-bit-wide output format for both the MAX1294/
MAX1296 is binary in unipolar mode and two’s comple­ment in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.

__________Applications Information

Power-On Reset

When power is first applied, internal power-on reset cir­cuitry activates the MAX1294/MAX1296 in external clock
mode and sets INT high. After the power supplies stabi­lize, the internal reset time is 10µs; no conversions
should be attempted during this phase. When using the
internal reference, 500µs is required for V

REF

to stabilize.

Internal and External Reference

The MAX1294/MAX1296 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.

An internal buffer is designed to provide +2.5V at REF for
both devices. The internally trimmed +1.22V reference is
buffered with a +2.05V/V gain.

Internal Reference

The full-scale range with the internal reference is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).

Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize reference
noise, connect a 0.01µF capacitor between REFADJ
and GND.

External Reference

With the MAX1294/MAX1296, an external reference can
be placed at either the input (REFADJ) or the output
(REF) of the internal-reference buffer amplifier.

Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.

When applying an external reference to REF, disable the
internal reference buffer by connecting REFADJ to V

DD

.

The DC input resistance at REF is 25kΩ. Therefore, an
external reference at REF must deliver up to 200µA DC
load current during a conversion and have an output
impedance less than 10Ω. If the reference has higher
output impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor.

Power-Down Modes

To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode through bits D6 and D7 of the
control byte (Tables 1, 4). In both software power-down
modes, the parallel interface remains active, but the
ADC does not convert.

Standby Mode

While in standby mode, the supply current is typically
1mA. The part will power up on the next rising edge of
WR and be ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 420ksps.

D6 D4D5

PD0

SGL/DIF

ACQMOD A2 A0A1

D2

D0

(LSB)

UNI/BIP

PD1

D1D3

D7

(MSB)

Table 4. Control-Byte Format

Figure 7. Reference Adjustment with External Potentiometer

VDD = +5V

50k

330k

50k

0.01µF

4.7µF

MAX1294
MAX1296

REFADJ

REF

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 15

Shutdown Mode

Shutdown mode turns off all chip functions that draw
quiescent current, reducing the typical supply current
to 2µA immediately after the current conversion is com­pleted. A rising edge on WR causes the MAX1294/
MAX1296 to exit shutdown mode and return to normal
operation. To achieve full 12-bit accuracy with a 4.7µF
reference bypass capacitor, 500µs is required after
power-up. Waiting 500µs in standby mode instead of in
full-power mode can reduce power consumption by a
factor of three or more. When using an external refer­ence, only 50µs is required after power-up. Enter
standby mode by performing a dummy conversion with
the control byte specifying standby mode.

Note: Bypass capacitors larger than 4.7µF between
REF and GND will result in longer power-up delays.

Transfer Function

Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figures 8 depicts the nominal

unipolar input/output (I/O) transfer function, and Figure 9
shows the bipolar I/O transfer function. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = (V

REF

/4096).

Maximum Sampling Rate/

Achieving 475ksps

When running at the maximum clock frequency of

7.6MHz, the specified throughput of 420ksps is
achieved by completing a conversion every 18 clock
cycles: one write cycle, three acquisition cycles, 13
conversion cycles, and one read cycle. This assumes
that the results of the last conversion are read before
the next control byte is written. It is possible to achieve
higher throughputs, up to 475ksps, by first writing a
control byte to begin the acquisition cycle of the next
conversion, and then reading the results of the previous
conversion from the bus. This technique (Figure 10)
allows a conversion to be completed every 16 clock
cycles. Note that the switching of the data bus during

Table 5. Full Scale and Zero Scale for Unipolar and Bipolar Operation

UNIPOLAR MODE BIPOLAR MODE

V

REF

+ COM V

REF

/2 + COMPositive Full ScaleFull Scale

COM COMZero ScaleZero Scale

— -V

REF

/2 + COM Negative Full Scale—

Figure 8. Unipolar Transfer Functions

Figure 9. Bipolar Transfer Functions

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

*COM V

OUTPUT CODE

FS

1LSB =

- FS

≤

/2

REF

REF

+ COM

=

2

ZS = COM

-REF

-FS = + COM
2

REF
4096

INPUT VOLTAGE (LSB)

OUTPUT CODE

111 . . . 111

111 . . . 110

100 . . . 010

100 . . . 001

100 . . . 000

011 . . . 111

011 . . . 110

011 . . . 101

000 . . . 001

000 . . . 000

0

(COM)

FS = REF + COM

ZS = COM

REF

1LSB =

4096

1

2

2048

INPUT VOLTAGE (LSB)

FULL-SCALE
TRANSITION

FS

FS - 3/2LSB

COM*

+FS - 1LSB

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

16 ______________________________________________________________________________________

acquisition or conversion can cause additional supply­noise, which may make it difficult to achieve true 12-bit
performance.

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards. Wire­wrap configurations are not recommended, since the
layout should ensure proper separation of analog and
digital traces. Do not run analog and digital lines paral­lel to each other, and don’t lay out digital signal paths
underneath the ADC package. Use separate analog
and digital PC board ground sections with only one
“star point” (Figure 11) connecting the two ground sys­tems (analog and digital). For lowest noise operation,
ensure the ground return to the star ground’s power
supply is low impedance and as short as possible.
Route digital signals far away from sensitive analog and
reference inputs.

High-frequency noise in the power supply, VDD, could
impair operation of the ADC’s fast comparator. Bypass
VDDto the star ground with a network of two parallel
capacitors, 0.1µF and 4.7µF, located as close to the
MAX1294/MAX1296’s power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5Ω) if the
power supply is extremely noisy.

Figure 10. Timing Diagram for Fastest Conversion

Figure 11. Power-Supply and Grounding Connections

123 4 5 6 78910111213141516

CLK

WR

RD

D7–D0

STATE

CONTROL

WORD

D11–

D0

ACQUISITION

SAMPLING INSTANT

CONTROL WORD

CONVERSION

SUPPLIES

+5V

V

DD

*OPTIONAL

4.7µF

0.1µF

GND

MAX1294
MAX1296

R* = 5Ω

D11–D0

ACQUISITION

+5V

DIGITAL

CIRCUITRY

GND

DGND+5VCOM

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 17

_________________________Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1294/MAX1296 is measured using the end­point method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam­ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog­to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):

SNR = (6.02 · N + 1.76)dB

In reality, there are other noise sources besides quanti­zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen­tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:

SINAD (dB) = 20 · log (Signal

RMS

/Noise

RMS

)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti­zation noise only. With an input range equal to the full­scale range of the ADC, calculate the effective number
of bits as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:

where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next largest distortion
component.

Chip Information

TRANSISTOR COUNT: 5781
SUBSTRATE CONNECTED TO GND

THD V V V V V=+++



⋅20



log /

223242521

















MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

18 ______________________________________________________________________________________

Typical Operating Circuits

Pin Configurations (continued)

CLK

MAX1294

µP

CONTROL

INPUTS

µP DATA BUS

CS

WR

RD

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

V

REF

REFADJ

INT

CH5

CH4

CH3

CH2

CH1

CH0

COM

GND

DD

0.1µF

TOP VIEW

+5V

+2.5V

4.7µF

OUTPUT STATUS

ANALOG

INPUTS

µP

CONTROL

INPUTS

µP DATA BUS

CLK

CS

WR

RD

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MAX1296

V

REF

REFADJ

INT

CH1

CH0

COM

GND

DD

0.1µF

OUTPUT STATUS

+5V

+2.5V

4.7µF

ANALOG

INPUTS

28

27

26

25

24

23

22

21

20

19

18

17

16

15

D10

D11

V

DD

REF

REFADJ

GND

COM

CH0

CH1

CH2

CH3

CH4

CH5

CS

INT

WR

CLK

1

D9

2

D8

3

D7

4

D6

5

D5

D4

D3

D2

D1

D0

RD

MAX1294

6

7

8

9

10

11

12

13

14

QSOP

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 19

Package Information

QSOP.EPS

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

NOTES