Maxim MAX1293BCEG, MAX1293AEEG, MAX1293ACEG, MAX1291BEEI, MAX1291BCEI Datasheet

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General Description

The MAX1291/MAX1293 low-power, 12-bit analog-to­digital converters (ADCs) feature a successive-approxi­mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
with a single +3V analog supply and feature a V

LOGIC

pin that allows them to interface directly with a +1.8V to
+5.5V digital supply.

Power consumption is only 5.7mW (V

DD

= V

LOGIC

) at
the maximum sampling rate of 250ksps. Two software­selectable power-down modes enable the MAX1291/
MAX1293 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can
cut supply current to under 10µA at reduced sampling
rates.

Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen­tial operation. In single-ended mode, the MAX1291 has
8 input channels and the MAX1293 has 4 input chan­nels (4 and 2 input channels, respectively, when in
pseudo-differential mode).

Excellent dynamic performance and low power com­bined with ease of use and small package size make
these converters ideal for battery-powered and data­acquisition applications or for other circuits with demand­ing power consumption and space requirements.

The MAX1291 is available in a 28-pin QSOP package,
while the MAX1293 is available in a 24-pin QSOP. For
pin-compatible +5V, 12-bit versions, refer to the
MAX1290/MAX1292 data sheet.

Applications

Industrial Control Systems Data Logging
Energy Management Patient Monitoring

Data-Acquisition Systems Touch Screens

Features

♦ 12-Bit Resolution, ±0.5LSB Linearity
♦ +3V Single Operation
♦ User-Adjustable Logic Level (+1.8V to +3.6V)
♦ Internal +2.5V Reference
♦ Software-Configurable, Analog Input Multiplexer

8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1291)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1293)

♦ Software-Configurable, Unipolar/Bipolar Inputs
♦ Low Power: 1.7mA (250ksps)

1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)

♦ Internal 3MHz Full-Power Bandwidth Track/Hold
♦ Byte-Wide Parallel (8+4) Interface
♦ Small Footprint: 28-Pin QSOP (MAX1291)

24-Pin QSOP (MAX1293)

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________

Maxim Integrated Products

1

19-1532; Rev 0; 9/99

PART

MAX1291ACEI

0°C to +70°C

TEMP. RANGE

PIN-PACKAGE

28 QSOP

Ordering Information

Pin Configurations

±0.5

INL

(LSB)

MAX1291BCEI

0°C to +70°C

±128 QSOP

Ordering Information continued at end of data sheet. Typical Operating Circuits appear at end of data sheet.

Pin Configurations continued at end of data sheet.

EVALUATION KIT

AVAILABLE

MAX1291BEEI

MAX1291AEEI

-40°C to +85°C

±1

-40°C to +85°C

±0.528 QSOP

28 QSOP

TOP VIEW

HBEN

D7

D6

D5

D4

D3/D11

D2/D10

D1/D9

D0/D8

INT

RD

WR

1

2

3

4

5

MAX1291

6

7

8

9

10

11

12

13

QSOP

28

27

26

25

24

23

22

21

20

19

18

17

16

1514 CH7CS

V

LOGIC

V

DD

REF

REFADJ

GND

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6CLK

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= V

LOGIC

= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 4.8MHz (50% duty

cycle); T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

V

LOGIC

to GND.........................................................-0.3V to +6V

CH0–CH7, COM to GND............................-0.3V to (V

DD

+ 0.3V)

REF, REFADJ to GND ................................-0.3V to (V

DD

+ 0.3V)

Digital Inputs to GND ...............................................-0.3V to +6V

Digital Outputs (D0–D11, INT) to GND...-0.3V to (V

LOGIC

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

24-Pin QSOP (derate 9.5mW/°C above +70°C) ...........762mW

28-Pin QSOP (derate 8.00mW/°C above +70°C) .........667mW

Operating Temperature Ranges

MAX1291_C_ _/MAX1293_C_ _..............................0°C to +70°C

MAX1291_E_ _/MAX1293_E_ _ ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

External acquisition or external clock mode

Internal acquisition/internal clock mode

MAX129_A

External acquisition/internal clock mode

External clock mode

-3dB rolloff

SINAD > 68dB

fIN= 125kHz, VIN= 2.5Vp-p (Note 4)

f

IN1

= 49kHz, f

IN

2

= 52kHz

MAX129_B
No missing codes over temperature

CONDITIONS

ns50Aperture Delay

ns625t

ACQ

Track/Hold Acquisition Time

µs

3.2 3.6 4.1

2.5 3.0 3.5

3.3

t

CONV

Conversion Time (Note 5)

MHz

3

Full-Power Bandwidth

kHz

250

Full-Linear Bandwidth

dB

-78

Channel-to-Channel Crosstalk

dB

76

IMDIntermodulation Distortion

dB

80

SFDRSpurious-Free Dynamic Range

dB

-78

Total Harmonic Distortion
(including 5th-order harmonic)

THD

±0.5

INLRelative Accuracy (Note 2)

Bits

12

RESResolution

dB

67 70

SINADSignal-to-Noise Plus Distortion

LSB

±0.2

Channel-to-Channel Offset
Matching

ppm/°C

±2.0

Gain Temperature Coefficient

LSB

±1

LSB

±1

DNLDifferential Nonlinearity

LSB

±4

Offset Error

LSB

±4

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

Internal acquisition/internal clock mode

External acquisition or external clock mode

<200

ps

<50

Aperture Jitter

MHz0.1 4.8f

CLK

External Clock Frequency

%30 70Duty Cycle

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (f

IN(sine wave)

= 50kHz, VIN= 2.5Vp-p, 250ksps, external f

CLK

= 4.8MHz, bipolar input mode)

CONVERSION RATE

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= V

LOGIC

= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 4.8MHz (50% duty

cycle); T

A

= T

MIN

to T

MAX

unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

0 to 0.5mA output load

To power down the internal reference

For small adjustments

TA= 0°C to +70°C

On/off-leakage current, VIN= 0 or V

DD

Unipolar, V

COM

= 0

V

1.0

V

DD

+

50mV

V

REF

REF Input Voltage Range

µF

4.7 10

Capacitive Bypass at REF

µF

0.01 1

Capacitive Bypass at REFADJ

mV/mA

0.2 0.5

Load Regulation (Note 7)

V

VDD- 1.0

REFADJ High Threshold

mV

±100

REFADJ Input Range

±20

ppm/°CTC

REF

REF Temperature Coefficient

mA

15

REF Short-Circuit Current

V

2.49 2.5 2.51

REF Output Voltage

pF

12

C

IN

Input Capacitance

µA

±0.01 ±1

Multiplexer Leakage Current

V

Analog Input Voltage Range
Single-Ended and Differential
(Note 6)

0V

REF

V

IN

CS = V

DD

I

SOURCE

= 1mA

I

SINK

= 1.6mA

VIN= 0 or V

DD

V

LOGIC

= 2.7V

µA

±0.1 ±1

I

LEAKAGE

Three-State Leakage Current

V

V

LOGIC

- 0.5

V

OH

Output High Voltage

V

0.4

V

OL

Output Low Voltage

pF

15

C

IN

Input Capacitance

µA

±0.1 ±1

I

IN

Input Leakage Current

mV

200

V

HYS

Input Hysteresis

2.0

CS = V

DD

pF

15

C

OUT

Three-State Output Capacitance

Bipolar, V

COM

= V

REF

/2

-V

REF

/2 +V

REF

/2

V

REF

= 2.5V, f

SAMPLE

= 250ksps

µA

200 300

I

REF

REF Input Current

Shutdown mode

2

V

LOGIC

= 1.8V

V

1.5

V

IH

Input High Voltage

V

LOGIC

= 1.8V

V

0.5

V

IL

Input Low Voltage

V

LOGIC

= 2.7V

0.8

ANALOG INPUTS

INTERNAL REFERENCE

EXTERNAL REFERENCE AT REF

DIGITAL INPUTS AND OUTPUTS

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS

(VDD= V

LOGIC

= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 4.8MHz (50% duty

cycle); T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

Shutdown mode

Standby mode

Operating mode,
f

SAMPLE

= 250ksps

µA

210

0.9 1.2

mA

2.3 2.6

V

2.7 3.6

V

DD

Analog Supply Voltage

150

ELECTRICAL CHARACTERISTICS (continued)

(VDD= V

LOGIC

= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 4.8MHz (50% duty

cycle); T

A

= T

MIN

to T

MAX

unless otherwise noted. Typical values are at TA= +25°C.)

V

LOGIC

Current I

LOGIC

CL= 20pF

10

µA

Power-Supply Rejection PSR VDD= 3V ±10%, full-scale input

±0.4 ±0.7

mV

f

SAMPLE

= 250ksps

Not converting

V

1.8 VDD+

0.3

V

LOGIC

Digital Supply Voltage

WR to CLK Fall Setup Time

t

CWS

40

ns

nsCLK Pulse Width High

nsCLK Period

t

CH

40

t

CP

208

CLK Pulse Width Low t

CL

40

ns

Data Valid to WR Rise Time

t

DS

40

ns

WR Rise to Data Valid Hold Time

t

DH

0

ns

CLK Fall to WR Hold Time

t

CWH

40

ns

CS to CLK or WR
Setup Time

t

CSWS

60

ns

CLK or WR to CS
Hold Time

t

CSWH

0

ns

CS Pulse Width

t

CS

100

ns

WR Pulse Width (Note 8)

t

WR

60

ns

t

TC

20 100

nsC

LOAD

= 20pF, Figure 1

PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS

CS Rise to Output Disable

POWER REQUIREMENTS

Internal reference

Internal reference

External reference

External reference

1.9 2.3

0.5 0.8

I

DD

Positive Supply Current

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 5

Note 1: Tested at VDD= +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V

DD

.

Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.

TIMING CHARACTERISTICS (continued)

(VDD= V

LOGIC

= +2.7V to +3.6V, COM = GND, REFADJ = VDD, V

REF

= +2.5V, 4.7µF capacitor at REF pin, f

CLK

= 4.8MHz (50% duty

cycle); T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

t

TR

20 70

nsC

LOAD

= 20pF, Figure 1

RD Rise to Output Disable
RD Fall to Output Data Valid

t

DO

20 70

ns

RD Fall to INT High Delay

t

INT1

100

ns

CS Fall to Output Data Valid

t

DO2

110

ns

C

LOAD

= 20pF, Figure 1

C

LOAD

= 20pF, Figure 1

C

LOAD

= 20pF, Figure 1

PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS

HBEN to Output Data Valid t

DO1

20 110

nsC

LOAD

= 20pF, Figure 1

Figure 1. Load Circuits for Enable/Disable Times

DOUT

V

LOGIC

3k

C

3k

GND GND

20pF

LOAD

DOUT

C

LOAD

20pF

a) HIGH-Z TO VOH AND VOL TO V

OH

b) HIGH-Z TO VOL AND VOH TO V

OL

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= V

LOGIC

= +3V, V

REF

= +2.500V, f

CLK

= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 20001000 3000 4000 5000

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1291/93 toc01

DIGITAL OUTPUT CODE

INL (LSB)

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 20001000 3000 4000 5000

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1291/93 toc02

DIGITAL OUTPUT CODE

DNL (LSB)

0.1 10k101 100 1k 100k 1M

SUPPLY CURRENT

vs. SAMPLE FREQUENCY

MAX1291/93 toc03

f

SAMPLE

(Hz)

I

DD

(µA)

1

10

100

1000

10,000

WITH INTERNAL
REFERENCE

WITH EXTERNAL
REFERENCE

1.80

1.90

1.85

2.00

1.95

2.05

2.10

2.7 3.0 3.3 3.6

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX1291/93 toc04

VDD (V)

I

DD

(mA)

R

L

= ∞

CODE = 101010100000

1.6

1.8

1.7

2.0

1.9

2.1

2.2

-40 10-15 35 60 85

SUPPLY CURRENT vs. TEMPERATURE

MAX1291/3 toc05

TEMPERATURE (°C)

I

DD

(mA)

R

L

= ∞

CODE = 101010100000

880

890

910

900

920

930

STANDBY CURRENT vs. SUPPLY VOLTAGE

MAX1291/3 toc06

V

DD

(V)

STANDBY I

DD

(µA)

2.7 3.33.0 3.6

880

890

910

900

920

930

STANDBY CURRENT vs. TEMPERATURE

MAX1291/3 toc07

TEMPERATURE (°C)

STANDBY I

DD

(µA)

-40 10-15 35 8560

0.50

1.00

0.75

1.25

1.50

2.7 3.0 3.3 3.6

POWER-DOWN CURRENT

vs. SUPPLY VOLTAGE

MAX1291/3 toc08

VDD (V)

POWER-DOWN I

DD

(µA)

0.8

0.9

1.0

1.1

1.2

POWER-DOWN CURRENT

vs. TEMPERATURE

MAX1291/3 toc09

TEMPERATURE (°C)

POWER-DOWN I

DD

(µA)

-40 35-15 10 60 85