MAXIM MAX1270, MAX1271 Technical data

General Description
The MAX1270/MAX1271 are multirange, 12-bit data­acquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that can span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: ±10V, ±5V, 0 to +10V, 0 to +5V for the MAX1270; ±V
REF
, ±V
REF
/2, 0 to
V
REF
, 0 to V
REF
/2 for the MAX1271. This range switch­ing increases the effective dynamic range to 14 bits and provides the flexibility to interface 4–20mA, ±12V, and ±15V powered sensors directly to a single +5V system. In addition, these converters are fault protected to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other fea­tures include a 5MHz bandwidth track/hold, software­selectable internal/external clock, 110ksps throughput rate, and internal 4.096V or external reference operation.
The MAX1270/MAX1271 serial interface directly connects to SPI™/QSPI™ and MICROWIRE™ devices without external logic.
A hardware shutdown input (SHDN) and two software­programmable power-down modes, standby (STBYPD) or full power-down (FULLPD), are provided for low-cur­rent shutdown between conversions. In standby mode, the reference buffer remains active, eliminating startup delays.
The MAX1270/MAX1271 are available in 24-pin narrow PDIP or space-saving 28-pin SSOP packages.
Applications
Features
12-Bit Resolution, 0.5 LSB Linearity
+5V Single-Supply Operation
SPI/QSPI and MICROWIRE-Compatible
3-Wire Interface
Four Software-Selectable Input Ranges
MAX1270: 0 to +10V, 0 to +5V, ±10V, ±5V MAX1271: 0 to V
REF
, 0 to V
REF
/2, ±V
REF
,
±V
REF
/2
Eight Analog Input Channels
110ksps Sampling Rate
±16.5V Overvoltage-Tolerant Input Multiplexer
Internal 4.096V or External Reference
Two Power-Down Modes
Internal or External Clock
24-Pin Narrow PDIP or 28-Pin SSOP Packages
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
________________________________________________________________ Maxim Integrated Products 1
V
DD
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
DGND
4.7µF
0.1µF
0.01µF
SHDN
MAX1270 MAX1271
+5V
ANALOG
INPUTS
CS
SCLK
DIN
DOUT
SSTRB
I/O SCK MOSI MISO
REF REFADJ
AGND
MC68HCXX
Typical Operating Circuit
PART
TEMP RANGE
PIN-PACKAGE
INL
(LSB)
MAX1270ACNG
±0.5
MAX1270BCNG
±1
MAX1270ACAI
28 SSOP
±0.5
MAX1270BCAI
28 SSOP ±1
Ordering Information
19-4782; Rev 2; 9/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
EVALUATION KIT
AVAILABLE
Industrial Control Systems Data-Acquisition Systems Battery-Powered Instruments
Automatic Testing Robotics Medical Instruments
0°C to +70°C 24 Narrow PDIP 0°C to +70°C 24 Narrow PDIP 0°C to +70°C 0°C to +70°C
MAX1270/MAX1271
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock; f
CLK
= 2.0MHz,
50% duty cycle (MAX127_B); f
CLK
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND ......................................................... ±16.5V
REF, REFADJ to AGND ..............................-0.3V to (V
DD
+ 0.3V)
SSTRB, DOUT to DGND.............................-0.3V to (V
DD
+ 0.3V)
SHDN, CS, DIN, SCLK to DGND..............................-0.3V to +6V
Max Current into Any Pin ....................................................50mA
Continuous Power Dissipation (T
A
= +70°C) 24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..1067mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW
Operating Temperature Ranges
MAX127_C_ _......................................................0°C to +70°C
MAX127_E_ _......................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETER
CONDITIONS
UNITS
ACCURACY (Note 1)
Resolution 12 Bits
MAX127_A
Integral Nonlinearity INL
MAX127_B
LSB
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
MAX127_A ±3
Unipolar
MAX127_B ±5 MAX127_A ±5
Offset Error
Bipolar
MAX127_B ±10
LSB
Unipolar
Channel-to-Channel Offset Error Matching
Bipolar
LSB
MAX127_A ±7
Unipolar
MAX127_B ±10 MAX127_A ±7
Gain Error (Note 2)
Bipolar
MAX127_B ±10
LSB
Unipolar, external reference ±3
Gain Error Temperature Coefficient (Note 2)
Bipolar, external reference ±5
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10V
P-P
(MAX1270), or ±4.096V
P-P
(MAX1271), f
SAMPLE
= 110ksps
(MAX127_B), f
SAMPLE
= 100ksps (MAX127_A))
SINAD 70 dB Total Harmonic Distortion THD Up to the 5th harmonic -87 -78 dB Spurious-Free Dynamic Range SFDR 80 dB
50kHz (Note 3) -86
Channel-to-Channel Crosstalk
DC, V
IN
= ±16.5V -96
dB
Aperture Delay External clock mode 15 ns
External clock mode
ps
Aperture Jitter
Internal clock mode 10 ns
SYMBOL
MIN TYP MAX
±0.5 ±1.0
Signal-to-Noise + Distortion Ratio
±0.1 ±0.3
<50
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock; f
CLK
= 2.0MHz,
50% duty cycle (MAX127_B); f
CLK
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
MAX127_A, f
CLK
= 1.8MHz 3.3
Track/Hold Acquisition Time t
ACQ
MAX127_B, f
CLK
= 2.0MHz 3.0
µs
±10V or ±V
REF
range
5
±5V or ±V
REF
/2
range
2.5
0 to 10V or 0 to V
REF
range
2.5
Small-Signal Bandwidth -3dB rolloff
0 to 5V or 0 to V
REF
/2 range
MHz
RNG = 1 0 10
MAX1270
RNG = 0 0 5 RNG = 1 0
Unipolar (BIP =
0), Table 3 MAX1271
RNG = 0 0 RNG = 1 -10
MAX1270
RNG = 0 -5 +5 RNG = 1
Input Voltage Range (Table 3)
V
IN
Bipolar (BIP =
1), Table 3 MAX1271
RNG = 0
+V
REF
/
2
V
0 to 10V range
-10
MAX1270
0 to 5V range
-10
Unipolar
MAX1271 -10 0.1
±10V range
MAX1270
±V
REF
range
Input Current I
IN
Bipolar
MAX1271
±V
REF
/2
range
µA
Unipolar 21
Dynamic Resistance
Bipolar 16
k
Input Capacitance (Note 4) 40 pF
VIN/I
IN
±5V range -600 +360
1.25
-V
REF
-V
/2
REF
-1200 +720
-1200 +10
-600 +10
V
V
REF
+10
+V
+720
+360
+10
REF
/2
REF
MAX1270/MAX1271
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock; f
CLK
= 2.0MHz,
50% duty cycle (MAX127_B); f
CLK
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
INTERNAL REFERENCE
REF Output Voltage V
REF
TA = +25°C
V
MAX1270_C/MAX1271_C
REF Output Tempco
MAX1270_E/MAX1271_E
ppm/°C
Output Short-Circuit Current 30 mA Load Regulation 0 to 0.5mA output current (Note 5) 10 mV Capacitive Bypass at REF 4.7 µF Capacitive Bypass at REFADJ
µF
REFADJ Output Voltage
V
REFADJ Adjustment Range Figure 1
%
Buffer Voltage Gain
V/V
REFERENCE INPUT (Reference buffer disabled, reference input applied to REF)
Input Voltage Range
V
Normal or STBYPD 400
Input Current V
REF
= 4.18V
FULLPD 1
µA
Normal or STBYPD 10 k
Input Resistance V
REF
= 4.18V
FULLPD
M
REFADJ Threshold for Buffer Disable
VDD -
0.5
V
POWER REQUIREMENT
Supply Voltage V
DD
V
Bipolar range 18
Normal
Unipolar range 6 10
mA
STBYPD power-down mode (Note 6)
850
Supply Current I
DD
FULLPD power-down mode
220
µA
External reference = 4.096V
Power-Supply Rejection Ratio (Note 7)
PSRR
Internal reference
LSB
TIMING
MAX127_A 0.1 1.8
External Clock Frequency Range
f
SCLK
MAX127_B 0.1 2.0
MHz
MAX127_A 3.3
External clock mode (Note 8)
MAX127_B 3.0
Acquisition Phase
Internal clock mode, Figure 9 3 5
µs
SYMBOL
TC V
REF
MIN TYP MAX
4.076 4.096 4.116
0.01
2.465 2.500 2.535
2.40 4.18
4.18
4.75 5.25
±15 ±30
±1.5
1.638
700 120
±0.1 ±0.5 ±0.5
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock; f
CLK
= 2.0MHz,
50% duty cycle (MAX127_B); f
CLK
= 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
MAX127_A 6.6
External clock mode (Note 8)
MAX127_B 6.0
Conversion Time t
CONV
Internal clock mode, Figure 9 6 7.7 11
µs
MAX127_A 100
External clock mode
MAX127_B 110
Throughput Rate
Internal clock mode 43
ksps
Bandgap Reference Startup Time
Power-up (Note 9)
µs
C
REF
= 4.7µF 8
Reference Buffer Settling Time
To 0.1mV, REF bypass capacitor fully discharged
C
REF
= 33µF 60
ms
DIGITAL INPUTS (DIN, SCLK, CS, and SHDN)
Input High Threshold Voltage V
IH
2.4 V
Input Low Threshold Voltage V
IL
0.8 V
Input Hysteresis V
HYS
0.2 V
Input Leakage Current I
IN
VIN = 0 to V
DD
-10
µA
Input Capacitance C
IN
(Note 4) 15 pF
DIGITAL OUTPUTS (DOUT, SSTRB)
I
SINK
= 5mA 0.4
Output Voltage Low V
OL
I
SINK
= 16mA 0.4
V
Output Voltage High V
OH
I
SOURCE
= 0.5mA
V
DD -
0.5
V
Tri-State Leakage Current I
L
CS = V
DD
-10
µA
Tri-State Output Capacitance C
OUT
CS = V
DD
(Note 4) 15 pF
SYMBOL
MIN TYP MAX
200
+10
+10
MAX1270/MAX1271
Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
6 _______________________________________________________________________________________
Note 1: Accuracy specifications tested at VDD= +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: External reference: V
REF
= 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels. V
IN
= ±5V (MAX1270), VIN= ±4V (MAX1271).
Note 4: Guaranteed by design, not production tested. Note 5: Use static external loads during conversion for specified accuracy. Note 6: Tested using internal reference. Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges. Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6). Note 9: Not production tested. Provided for design guidance only.
TIMING CHARACTERISTICS
(VDD= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock; f
CLK
=
2.0MHz (MAX127_B); f
CLK
= 1.8MHz (MAX127_A); TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are TA= +25°C.)
(Figures 2, 5, 7, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIN to SCLK Setup t
DS
ns
DIN to SCLK Hold t
DH
0ns
SCLK Fall to Output Data Valid t
DO
20
ns
CS Fall to Output Enable t
DV
C
LOAD
= 100pF
ns
CS Rise to Output Disable t
TR
C
LOAD
= 100pF
ns
CS to SCLK Rise Setup t
CSS
ns
CS to SCLK Rise Hold t
CSH
0ns
SCLK Pulse-Width High t
CH
ns
SCLK Pulse-Width Low t
CL
ns
SCLK Fall to SSTRB t
SSTRB
C
LOAD
= 100pF
ns
CS to SSTRB Output Enable t
SDV
C
LOAD
= 100pF, external clock mode only
ns
CS to SSTRB Output Disable t
STR
C
LOAD
= 100pF, external clock mode only
ns
SSTRB Rise to SCLK Rise t
SCK
Internal clock mode only (Note 4) 0 ns
100
100
200 200
170 120 100
200 200 200
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