Maxim MAX12557 Specifications

General Description

The MAX12557 is a dual 3.3V, 14-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12557 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 610mW while delivering a typical 72.5dB signal-tonoise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12557 features a 166µW powerdown mode to conserve power during idle periods.

A flexible reference structure allows the MAX12557 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12557 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.

The MAX12557 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE).

The MAX12557 features two parallel, 14-bit-wide, CMOS-compatible outputs. The digital output format is pin-selectable to be either two’s complement or Gray code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12557 is available in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed paddle (EP), and is specified for the extended (-40°C to +85°C) temperature range.

For a 12-bit, pin-compatible version of this ADC, refer to the MAX12527 data sheet.

Applications

IF and Baseband Communication Receivers

Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN

I/Q Receivers

Ultrasound and Medical Imaging

Portable Instrumentation

Digital Set-Top Boxes

Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance

74.1dB/72.5dB SNR at f

= 70MHz/175MHz

83.4dBc/79.5dBc SFDR at f

= 70MHz/175MHz

♦ 3.3V Low-Power Operation

637mW (Differential Clock Mode) 610mW (Single-Ended Clock Mode)

♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Differential Analog Input Voltage ♦ 750MHz Input Bandwidth ♦ Adjustable, Internal or External, Shared Reference ♦ Differential or Single-Ended Clock ♦ Accepts 25% to 75% Clock Duty Cycle ♦ User-Selectable DIV2 and DIV4 Clock Modes ♦ Power-Down Mode ♦ CMOS Outputs in Two’s Complement or Gray

Code

♦ Out-of-Range and Data-Valid Indicators ♦ Small, 68-Pin Thin QFN Package ♦ 12-Bit Compatible Version Available (MAX12527) ♦ Evaluation Kit Available (Order MAX12557 EV Kit)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3544; Rev 0; 2/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-PACKAGE

MAX12557ETK

68 Thin QFN-EP*

(10mm x 10mm x 0.8mm)

*EP = Exposed paddle.

PART

SAMPLING RATE

(Msps)

RESOLUTION

(Bits)

MAX12557 65 14

MAX12527 65 12

Selector Guide

Pin Configuration appears at end of data sheet.

-40°C to +85°C

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, VIN= -0.5dBFS (differential), DIFFCLK/

SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 65MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND ................................................................-0.3V to +3.6V

to GND............-0.3V to the lower of (VDD+ 0.3V) and +3.6V

INAP, INAN to GND ...-0.3V to the lower of (V

+ 0.3V) and +3.6V

INBP, INBN to GND ...-0.3V to the lower of (V

+ 0.3V) and +3.6V

CLKP, CLKN to

GND ........................-0.3V to the lower of (V

+ 0.3V) and +3.6V

REFIN, REFOUT

to GND ..................-0.3V to the lower of (V

+ 0.3V) and +3.6V

REFAP, REFAN,

COMA to GND ......-0.3V to the lower of (V

+ 0.3V) and +3.6V

REFBP, REFBN,

COMB to GND ......-0.3V to the lower of (V

+ 0.3V) and +3.6V

DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,

DIV4 to GND .........-0.3V to the lower of (VDD+ 0.3V) and +3.6V

D0A–D13A, D0B–D13B, DAV,

DORA, DORB to GND..............................-0.3V to (OV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C) 68-Pin Thin QFN 10mm x 10mm x 0.8mm

(derate 70mW/°C above +70°C) ....................................4000mW

Operating Temperature Range................................-40°C to +85°C

Junction Temperature ...........................................................+150°C

Storage Temperature Range .................................-65°C to +150°C

Lead Temperature (soldering 10s).......................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution 14 Bits

Integral Nonlinearity INL fIN = 3MHz

LSB

Differential Nonlinearity DNL

= 3MHz, no missing codes over

temperature (Note 2)

LSB

Offset Error

%FSR

Gain Error

%FSR

ANALOG INPUT (INAP, INAN, INBP, INBN)

Differential Input Voltage Range V

DIFF

Differential or single-ended inputs

Common-Mode Input Voltage

Analog Input Resistance R

Each input, Figure 3 3.4 kΩ

PAR

Fixed capacitance to ground, each input, Figure 3

Analog Input Capacitance

Switched capacitance, each input, Figure 3

4.5

CONVERSION RATE

Maximum Clock Frequency f

CLK

65 MHz

Minimum Clock Frequency 5 MHz

Data Latency Figure 5 8

Clock

Cycles

DYNAMIC CHARACTERISTICS (differential inputs)

Small-Signal Noise Floor SSNF Input at -35dBFS

dBFS

fIN = 3MHz at -0.5dBFS

fIN = 32.5MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Signal-to-Noise Ratio SNR

= 175MHz at -0.5dBFS

±2.1

-1.0 ±0.6 +1.3

SAMPLE

74.5

72.5

70.4 72.5

±0.1 ±0.9

±0.5 ±5.0

±1.024

/ 2

74.5

74.1

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, VIN= -0.5dBFS (differential), DIFFCLK/SECLK = OV

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 65MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 32.5MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Signal-to-Noise Plus Distortion SINAD

= 175MHz at -0.5dBFS

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 32.5MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Spurious-Free Dynamic Range SFDR

= 175MHz at -0.5dBFS

dBc

fIN = 3MHz at -0.5dBFS (Note 3)

fIN = 32.5MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Total Harmonic Distortion THD

= 175MHz at -0.5dBFS

dBc

fIN = 3MHz at -0.5dBFS

fIN = 32.5MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Second Harmonic HD2

= 175MHz at -0.5dBFS

dBc

fIN = 3MHz at -0.5dBFS -93

fIN = 32.5MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Third Harmonic HD3

= 175MHz at -0.5dBFS

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

-88

Two-Tone Intermodulation Distortion (Note 2)

TTIMD

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

3rd-Order Intermodulation Distortion

IM3

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

Two-Tone Spurious-Free Dynamic Range

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

Full-Power Bandwidth FPBW Input at -0.2dBFS, -3dB rolloff

MHz

Aperture Delay t

Figure 5 1.2 ns

Aperture Jitter t

RMS

Output Noise n

OUT

INAP = INAN = COMA INBP = INBN = COMB

LSB

RMS

SYMBOL

SFDR

MIN TYP MAX

71.8 74.4

73.10

73.4

71.5

75.5 86.6

82.8

83.4

79.5

-84.5 -74.5

-80.7

-81.7

-78.3

-89.5

-84.2

-84.7

-79.5

-85.5

-86.5

-87.2

-82.4

-91.5

-87.6

82.4

750

<0.15

1.02

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, VIN= -0.5dBFS (differential), DIFFCLK/SECLK = OV

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 65MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

Overdrive Recovery Time ±10% beyond full scale 1

Clock

Cycle

INTERCHANNEL CHARACTERISTICS

INA

or f

INB

= 70MHz at -0.5dBFS 90

Crosstalk Rejection

INA

or f

INB

= 175MHz at -0.5dBFS 85

Gain Matching

Offset Matching

%FSR

INTERNAL REFERENCE (REFOUT)

REFOUT Output Voltage

REFOUT Load Regulation -1mA < I

REFOUT

< +1mA 35

mV/mA

REFOUT Temperature Coefficient

REF

ppm/°C

Short to VDD—sinking

REFOUT Short-Circuit Current

Short to GND—sourcing 2.1

BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source; V

REFAP/VREFAN/VCOMA

and V

REFBP/VREFBN/VCOMB

are generated internally)

REFIN Input Voltage V

REFIN

REFIN Input Resistance R

REFIN

MΩ

COM_ Output Voltage

COMA

COMB

VDD / 2

REF_P Output Voltage

REFAP

VDD / 2 + (V

REFIN

x 3/8)

REF_N Output Voltage

REFAN

VDD / 2 - (V

REFIN

x 3/8)

Differential Reference Voltage

REFA

REFB

REFA

= V

REFAP

- V

REFAN

REFB

= V

REFBP

- V

REFBN

Differential Reference Temperature Coefficient

REF

ppm/°C

UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V

REFAP/VREFAN/VCOMA

and V

REFBP/VREFBN/VCOMB

are applied

externally, V

COMA

= V

COMB

= VDD / 2)

REF_P Input Voltage

REFAP

REF_P

- V

COM

REF_N Input Voltage

REFAN

REF_N

- V

COM

COM_ Input Voltage V

COM

VDD / 2

Differential Reference Voltage

REFA

REFB

REF_

= V

REF_P

- V

REF_N

= V

REFIN

x 3/4

SYMBOL

MIN TYP MAX

±0.01 ±0.1

±0.01

REFOUT

2.000 2.048 2.080

REFBP

REFBN

1.60 1.65 1.70

1.460 1.536 1.580

±50

0.24

2.048

>50

2.418

0.882

±25

REFBP

REFBN

+0.768

-0.768

1.65

1.536

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, VIN= -0.5dBFS (differential), DIFFCLK/SECLK = OV

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 65MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

REF_P Sink Current

REFAP

REFBP

REF_P

= 2.418V 1.2 mA

REF_N Source Current

REFAN

REFBN

REF_N

= 0.882V

COM_ Sink Current

COMA

COMB

COM_

= 1.65V

REF_P, REF_N Capacitance

REF_P

13 pF

COM_ Capacitance C

COM_

6pF

CLOCK INPUTS (CLKP, CLKN)

Single-Ended Input High Threshold

DIFFCLK/SECLK = GND, CLKN = GND

0.8 x V

Single-Ended Input Low Threshold

DIFFCLK/SECLK = GND, CLKN = GND

0.2 x V

Minimum Differential Clock Input Voltage Swing

DIFFCLK/SECLK = OV

0.2 V

P-P

Differential Input Common-Mode Voltage

DIFFCLK/SECLK = OV

CLK_ Input Resistance R

CLK

Each input, Figure 4 5 kΩ

CLK_ Input Capacitance C

CLK

2pF

DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4)

Input High Threshold V

0.8 x V

Input Low Threshold V

0.2 x V

OVDD applied to input ±5

Input Leakage Current

Input connected to ground ±5

µA

Digital Input Capacitance C

DIN

5pF

DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)

D0A–D13A, D0B–D13B, DORA, DORB: I

SINK

= 200µA

0.2

Output-Voltage Low V

DAV: I

SINK

= 600µA 0.2

D0A–D13A, D0B–D13B, DORA, DORB: I

SOURCE

= 200µA

0.2

Output-Voltage High V

DAV: I

SOURCE

= 600µA

0.2

OVDD applied to input ±5

Tri-State Leakage Current (Note 3)

LEAK

Input connected to ground ±5

µA

SYMBOL

REF_N

MIN TYP MAX

0.85

/ 2

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, VIN= -0.5dBFS (differential), DIFFCLK/SECLK = OV

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 65MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

D 0A–D 13A, D O RA, D 0B–D 13B and D ORB Tr i - S tate O utp ut C ap aci tance ( N ote 3)

OUT

3pF

DAV Tri-State Output Capacitance (Note 3)

DAV

6pF

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Output Supply Voltage OV

2.0

Normal operating mode f

= 175MHz at -0.5dBFS,

single-ended clock (DIFFCLK/SECLK = GND)

Normal operating mode f

= 175MHz at -0.5dBFS

differential clock (DIFFCLK/SECLK = OV

)

Analog Supply Current I

VDD

Power-down mode (PD = OVDD) clock idle

Normal operating mode f

= 175MHz at -0.5dBFS

single-ended clock (DIFFCLK/SECLK = GND)

Normal operating mode f

= 175MHz at -0.5dBFS

differential clock (DIFFCLK/SECLK = OV

)

Analog Power Dissipation P

VDD

Power-down mode (PD = OVDD) clock idle

Normal operating mode f

= 175MHz at -0.5dBFS

Digital Output Supply Current I

OVDD

Power-down mode (PD = OVDD) clock idle

SYMBOL

MIN TYP MAX

3.15 3.30 3.60

1.70

185

193 210

0.05

610

637 693

0.165

21.3

0.001

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, VIN= -0.5dBFS (differential), DIFFCLK/SECLK = OV

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 65MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (Figure 5)

Clock Pulse-Width High t

7.7 ns

Clock Pulse-Width Low t

7.7 ns

Data-Valid Delay t

DAV

5.4 ns

Data Setup Time Before Rising Edge of DAV

SETUP

(Note 6) 7.0 ns

Data Hold Time After Rising Edge of DAV

HOLD

(Note 6) 7.0 ns

WAKE

REFIN

= 2.048V 10 ms

Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Note 2: Guaranteed by design and characterization. Device tested for performance during product test. Note 3: Specification guaranteed by production test for ≥+25°C. Note 4: Two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input

power of both input tones.

Note 5: During power-down, D0A–D13A, D0B–D13B, DORA, DORB, and DAV are high impedance. Note 6: Guaranteed by design and characterization.

Typical Operating Characteristics

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, VIN= -0.5dBFS, DIFFCLK/SECLK = OV

, PD = GND, G/T = GND, f

CLK

= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

FFT PLOT (32,768-POINT DATA RECORD)

MAX12557 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

-100

-80

-60

-40

-20

-120

HD3

CLK

= 65MHz

= 3.00125MHz

= -0.48dBFS SNR = 74.45dB SINAD = 74.33dB THD = -90.06dBc SFDR = 92.47dBc

HD2

-10

-30

-50

-70

-90

-110

2515 201050

FFT PLOT (32,768-POINT DATA RECORD)

MAX12557 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

-100

-80

-60

-40

-20

-120

HD3

CLK

= 65.00352MHz

= 32.40058MHz

= -0.424dBFS SNR = 74.77dB SINAD = 74.62dB THD = -87.22dBc SFDR = 91.88dBc

HD2

-10

-30

-50

-70

-90

-110

2515 201050

FFT PLOT (32,768-POINT DATA RECORD)

MAX12557 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

-100

-80

-60

-40

-20

-120

CLK

= 65.00352MHz

= 70.00852MHz

= -0.498dBFS SNR = 74.41dB SINAD = 74.00dB THD = -84.50dBc SFDR = 86.25dBc

HD2

-10

-30

-50

-70

-90

-110

HD3

2515 201050

Wake-Up Time from Power-Down

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

8 _______________________________________________________________________________________

-2.0

-1.0

-1.5

-0.5

0.5

1.0

1.5

2.0

0 4096 61442048 8192 10240 12288 14336 16384

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

(4,194,304-POINT DATA RECORD)

MAX12557 toc07

DIGITAL OUTPUT CODE

INL (LSB)

fIN = 3.00123MHz

-1.00

-0.50

-0.75

-0.25

0.25

0.50

0.75

1.00

0 4096 61442048 8192 10240 12288 14336 16384

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

(4,194,304-POINT DATA RECORD)

MAX12557 toc08

DIGITAL OUTPUT CODE

DNL (LSB)

fIN = 3.00123MHz

0 100 15050 200 250 300 350 400

SNR, SINAD vs. ANALOG INPUT FREQUENCY

CLK

= 65.00352MHz, AIN = -0.5dBFS)

MAX12557 toc09

fIN (MHz)

SNR, SINAD (dB)

SNR

SINAD

0 150 20050 100 250 300 350 400

-THD, SFDR vs. ANALOG INPUT FREQUENCY (f

CLK

= 65.00352MHz, AIN = -0.5dBFS)

MAX12557 toc10

fIN (MHz)

-THD, SFDR (dBc)

SFDR

-THD

-55 -45 -40 -35-50 -30 -25 -20 -15 -10 -5 0

MAX12557 toc11

AIN (dBFS)

SNR, SINAD (dB)

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

CLK

= 65.00352MHz, fIN = 70MHz)

SINAD

SNR

-55 -45 -40 -35-50 -30 -25 -20 -15 -10 -5 0

MAX12557 toc12

AIN (dBFS)

-THD, SFDR (dBc)

-THD, SFDR vs. ANALOG INPUT AMPLITUDE (f

CLK

= 65.00352MHz, fIN = 70MHz)

-THD

SFDR

FFT PLOT (32,768-POINT DATA RECORD)

MAX12557 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

-100

-80

-60

-40

-20

-120

CLK

= 65.00352MHz

= 174.98857MHz

= -0.476dBFS SNR = 72.37dB SINAD = 70.48dB THD = -75.62dBc SFDR = 76.37dBc

HD2

-10

-30

-50

-70

-90

-110

HD3

2515 201050

TWO-TONE IMD PLOT

(16,384-POINT DATA RECORD)

MAX12557 toc05

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

-100

-80

-60

-40

-20

-120

CLK

= 65.00352MHz

IN1

= 68.49987MHz

IN1

= -6.97dBFS

IN2

= 71.49930dB

IN2

= -6.99dBFS IM3 = -91.54dBc IMD = -87.97dBc

-10

-30

-50

-70

-90

-110

HD3

IN2

+ f

IN1

+ f

IN2

IN1

302515 201050

TWO-TONE IMD PLOT

(16,384-POINT DATA RECORD)

MAX12557 toc06

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

-100

-80

-60

-40

-20

-120

CLK

= 65.00352MHz

IN1

= 172.49995MHz

IN1

= -6.95dBFS

IN2

= 177.49900688MHz

IN2

= -6.97dBFS IM3 = -87.61dBc IMD = -82.37dBc

-10

-30

-50

-70

-90

-110

HD3

IN1

+ f

IN2

IN1

IN2

HD2

2515 201050

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, VIN= -0.5dBFS, DIFFCLK/SECLK = OV

, PD = GND, G/T = GND, f

CLK

= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 9

-55 -45 -40 -35-50 -30 -25 -20 -15 -10 -5 0

MAX12557 toc13

AIN (dBFS)

SNR, SINAD (dB)

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

CLK

= 65.00352MHz, fIN = 175MHz)

SINAD

SNR

-55 -45 -40 -35-50 -30 -25 -20 -15 -10 -5 0

MAX12557 toc14

AIN (dBFS)

-THD, SFDR (dBc)

-THD, SFDR vs. ANALOG INPUT AMPLITUDE (f

CLK

= 65.00352MHz, fIN = 175MHz)

-THD

SFDR

20 35 4025 30 45 50 55 60 65

SNR, SINAD vs. CLOCK SPEED (f

= 70MHz, AIN = -0.5dBFS)

MAX12557 toc15

CLK

(MHz)

SNR, SINAD (dB)

SNR

SINAD

20 35 4025 30 45 50 55 60 65

-THD, SFDR vs. CLOCK SPEED (f

= 70MHz, AIN = -0.5dBFS)

MAX12557 toc16

CLK

(MHz)

-THD, SFDR (dBc)

SFDR

-THD

20 35 4025 30 45 50 55 60 65

SNR, SINAD vs. CLOCK SPEED

= 175MHz, AIN = -0.5dBFS)

MAX12557 toc17

CLK

(MHz)

SNR, SINAD (dB)

SNR

SINAD

20 35 4025 30 45 50 55 60 65

-THD, SFDR vs. CLOCK SPEED

= 175MHz, AIN = -0.5dBFS)

MAX12557 toc18

CLK

(MHz)

-THD, SFDR (dBc)

-THD

SFDR

3.0 3.23.1 3.3 3.4 3.5 3.6

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 70MHz)

MAX12557 toc19

VDD (V)

SNR, SINAD (dB)

SNR

SINAD

3.0 3.2 3.33.1 3.4 3.5 3.6

MAX12557 toc20

VDD (V)

-THD, SFDR (dBc)

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE (f

CLK

= 65.00352MHz, fIN = 70MHz)

SFDR

-THD

3.0 3.23.1 3.3 3.4 3.5 3.6

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 175MHz)

MAX12557 toc21

VDD (V)

SNR, SINAD (dB)

SNR

SINAD

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, VIN= -0.5dBFS, DIFFCLK/SECLK = OV

, PD = GND, G/T = GND, f

CLK

= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

10 ______________________________________________________________________________________

3.0 3.23.1 3.3 3.4 3.5 3.6

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 175MHz)

MAX12557 toc22

VDD (V)

-THD, SFDR (dBc)

SFDR

-THD

1.5 2.11.8 2.4 2.7 3.0 3.3

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 70MHz)

MAX12557 toc23

OVDD (V)

SNR, SINAD (dB)

SNR

SINAD

3.6

1.5 2.1 2.41.8 2.7 3.0 3.3 3.6

MAX12557 toc24

OVDD (V)

-THD, SFDR (dBc)

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (f

CLK

= 65.00352MHz, fIN = 70MHz)

SFDR

-THD

1.5 2.11.8 2.4 2.7 3.0 3.3

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 175MHz)

MAX12557 toc25

OVDD (V)

SNR, SINAD (dB)

SNR

SINAD

3.6

1.5 2.11.8 2.4 2.7 3.0 3.3

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (f

CLK

= 65.00352MHz, fIN = 175MHz)

MAX12557 toc26

OVDD (V)

-THD, SFDR (dBc)

SFDR

-THD

3.6

200

100

500

400

300

800

700

600

900

3.0 3.23.1 3.3 3.4 3.5 3.6

DISS

, I

VDD

(ANALOG) vs. ANALOG SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 175MHz)

MAX12557 toc27

VDD (V)

DISS

, I

VDD

(mW, mA)

DISS

(ANALOG)

VDD

1.5 2.11.8 2.4 2.7 3.0 3.3 3.6

MAX12557 toc28

OVDD (V)

DISS

, I

OVDD

(DIGITAL)

vs. DIGITAL SUPPLY VOLTAGE

CLK

= 65.00352MHz, fIN = 175MHz)

DISS

, I

OVDD

(mW, mA)

DISS

(DIGITAL)

CL ≈ 5pF

OVDD

25 4535 55 65 75

SNR, SINAD vs. CLOCK DUTY CYCLE

= 70MHz, AIN = -0.5dBFS)

MAX12557 toc29

CLOCK DUTY CYCLE (%)

SNR, SINAD (dB)

SINGLE-ENDED CLOCK DRIVE

SNR

SINAD

25 4535 55 65 75

-THD, SFDR vs. CLOCK DUTY CYCLE (f

= 70MHz, AIN = -0.5dBFS)

MAX12557 toc30

CLOCK DUTY CYCLE (%)

-THD, SFDR (dBc)

SINGLE-ENDED CLOCK DRIVE

SFDR

-THD

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, VIN= -0.5dBFS, DIFFCLK/SECLK = OV

, PD = GND, G/T = GND, f

CLK

= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 11

-40 10-15 35 60 85

SNR, SINAD vs. TEMPERATURE (f

= 175MHz, AIN = -0.5dBFS)

MAX12557 toc31

TEMPERATURE (°C)

SNR, SINAD (dB)

SNR

SINAD

-40 10-15 35 60 85

-THD, SFDR vs. TEMPERATURE (f

= 175MHz, AIN = -0.5dBFS)

MAX12557 toc32

TEMPERATURE (°C)

-THD, SFDR (dBc)

SFDR

-THD

-3

-1

-2

-40 10-15 35 60 85

GAIN ERROR vs. TEMPERATURE

MAX12557 toc33

TEMPERATURE (°C)

GAIN ERROR (%FSR)

-0.3

-0.2

-0.1

0.1

0.2

0.3

-40 -15 10 35 60 85

OFFSET ERROR vs. TEMPERATURE

MAX12557 toc34

TEMPERATURE (°C)

OFFSET ERROR (%FSR)

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, VIN= -0.5dBFS, DIFFCLK/SECLK = OV

, PD = GND, G/T = GND, f

CLK

= 65MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

12 ______________________________________________________________________________________

PIN NAME FUNCTION

1, 4, 5, 9,

13, 14, 17

GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together.

2 INAP Channel A Positive Analog Input

3 INAN Channel A Negative Analog Input

6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.

7 REFAP

Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V

REFAP

- V

REFAN

). Bypass REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the

same side of the PC board.

8 REFAN

Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (V

REFAP

- V

REFAN

). Bypass REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the

same side of the PC board.

10 REFBN

Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (V

REFBP

- V

REFBN

). Bypass REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the

same side of the PC board.

11 REFBP

Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (V

REFBP

- V

REFBN

). Bypass REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the

same side of the PC board.

12 COMB Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.

15 INBN Channel B Negative Analog Input

16 INBP Channel B Positive Analog Input

SECLK

Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock input drives. DIFFCLK/SECLK = GND: Selects single-ended clock input drive. DIFFCLK/SECLK = OV

: Selects differential clock input drive.

19 CLKN

Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV

), connect a differential

clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the clock signal to CLKP and connect CLKN to GND.

20 CLKP

Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV

), connect a differential

clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND.

21 DIV2 Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.

22 DIV4 Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.

23–26, 61,

62, 63

Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of ≥10µF and 0.1µF. Connect all V

pins to the same potential.

27, 43, 60

Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of ≥10µF and 0.1µF.

Pin Description

DIFFCLK/

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 13

PIN NAME FUNCTION

28 D0B Channel B CMOS Digital Output, Bit 0 (LSB)

29 D1B Channel B CMOS Digital Output, Bit 1

30 D2B Channel B CMOS Digital Output, Bit 2

31 D3B Channel B CMOS Digital Output, Bit 3

32 D4B Channel B CMOS Digital Output, Bit 4

33 D5B Channel B CMOS Digital Output, Bit 5

34 D6B Channel B CMOS Digital Output, Bit 6

35 D7B Channel B CMOS Digital Output, Bit 7

36 D8B Channel B CMOS Digital Output, Bit 8

37 D9B Channel B CMOS Digital Output, Bit 9

38 D10B Channel B CMOS Digital Output, Bit 10

39 D11B Channel B CMOS Digital Output, Bit 11

40 D12B Channel B CMOS Digital Output, Bit 12

41 D13B Channel B CMOS Digital Output, Bit 13 (MSB)

42 DORB

Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog input voltage is out of range. DORB = 1: Digital outputs exceed full-scale range. DORB = 0: Digital outputs are within full-scale range.

44 DAV

Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs. The MAX12557 evaluation kit utilizes DAV to latch data into any external back-end digital logic.

45 D0A Channel A CMOS Digital Output, Bit 0 (LSB)

46 D1A Channel A CMOS Digital Output, Bit 1

47 D2A Channel A CMOS Digital Output, Bit 2

48 D3A Channel A CMOS Digital Output, Bit 3

49 D4A Channel A CMOS Digital Output, Bit 4

50 D5A Channel A CMOS Digital Output, Bit 5

51 D6A Channel A CMOS Digital Output, Bit 6

52 D7A Channel A CMOS Digital Output, Bit 7

53 D8A Channel A CMOS Digital Output, Bit 8

54 D9A Channel A CMOS Digital Output, Bit 9

55 D10A Channel A CMOS Digital Output, Bit 10

56 D11A Channel A CMOS Digital Output, Bit 11

57 D12A Channel A CMOS Digital Output, Bit 12

58 D13A Channel A CMOS Digital Output, Bit 13 (MSB)

59 DORA

Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog input voltage is out of range. DORA = 1: Digital outputs exceed full-scale range. DORA = 0: Digital outputs are within full-scale range.

64 G/T

Output Format Select Digital Input. G/T = GND: Two’s-complement output format selected. G/T = OV

: Gray-code output format selected.

Pin Description (continued)

MAX12557

Detailed Description

The MAX12557 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output the total latency is 8 clock cycles.

Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX12557 functional diagram.

Dual, 65Msps, 14-Bit, IF/Baseband ADC

14 ______________________________________________________________________________________

PIN NAME FUNCTION

65 PD

Power-Down Digital Input. PD = GND: ADCs are fully operational. PD = OV

: ADCs are powered down.

66 SHREF

Shared Reference Digital Input. SHREF = V

: Shared reference enabled. SHREF = GND: Shared reference disabled. When sharing the reference, externally connect REFAP and REFBP together to ensure that V

REFAP

REFBP

. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure

that V

REFAN

= V

REFBN

Inter nal Refer ence V ol tag e O utp ut. The RE FOU T outp ut vol tag e i s 2.048V and RE FO U T can d el i ver 1m A. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor. For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥0.1µF capacitor.

68 REFIN

Single-Ended Reference Analog Input. For i nter nal r efer ence and b uffer ed exter nal r efer ence op er ati on, ap p l y a 0.7V to 2.3V D C r efer ence vol tag e to RE FIN . B y p a s s REF I N t o GN D w it h a 4 . 7 µ F c a p a c i t o r . W i thi n i ts sp eci fi ed op er ati ng vol tag e, RE FIN has a > 50M Ω i np ut i m p ed ance, and the d i ffer enti al r efer ence vol tag e ( V

R E F_ P

- V

R E F_ N

) i s g ener ated fr om RE FIN . For unb uffer ed exter nal r efer ence op er ati on, connect RE FIN to G N D . In thi s m od e, RE F_P , RE F_N , and C O M _ ar e hi g h- i m p ed ance i np uts that accep t the exter nal r efer ence vol tag es.

—EP

Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified dynamic performance.

Pin Description (continued)

MAX12557

−

DIGITAL ERROR CORRECTION

FLASH

ADC

DAC

STAGE 2

IN_P

IN_N

STAGE 1 STAGE 9

STAGE 10

END OF PIPELINE

D0_ THROUGH D13_

Figure 1. Pipeline Architecture—Stage Blocks

REFOUT

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 15

INBP

14-BIT

PIPELINE

ADC

DIGITAL

ERROR

CORRECTION

CHANNEL A REFERENCE

SYSTEM

COMA REFAN

REFAP

DAV

OUTPUT DRIVERS

DORA

CLOCK

DIVIDER

DATA

FORMAT

14-BIT

PIPELINE

ADC

DIGITAL

ERROR

CORRECTION

OUTPUT DRIVERS

DATA

FORMAT

DIV2 DIV4

INBN

D0B TO D13B

DORB

CHANNEL B REFERENCE

SYSTEM

COMB REFBN

REFBP

INAP

INAN

CLKP

CLKN

DUTY-CYCLE

EQUALIZER

CLOCK

POWER

CONTROL

AND

BIAS CIRCUITS

GND

CLOCK

REFIN

INTERNAL

REFERENCE

GENERATOR

REFOUT

SHREF

DIFFCLK/SECLK

D0A TO D13A

G/T

MAX12557

T/H

Figure 2. Functional Diagram

MAX12557

Analog Inputs and Input Track-and-Hold

(T/H) Amplifier

Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a VDD/ 2 common-mode input voltage.

The MAX12557 sampling clock controls the switchedcapacitor input T/H architecture (Figure 3) allowing the analog input signals to be stored as charge on the sampling capacitors. These switches are closed (track mode) when the sampling clock is high and open (hold mode) when the sampling clock is low (Figure 4). The analog input signal source must be able to provide the dynamic currents necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX12557 supports differential or singleended input drive. For optimum performance with differential inputs, balance the input impedance of IN_P and IN_N and set the common-mode voltage to midsupply (V

/ 2). The MAX12557 provides the optimum common-mode voltage of VDD/ 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 9, 10, and 11.

Reference Output

An internal bandgap reference is the basis for all the internal voltages and bias currents used in the

MAX12557. The power-down logic input (PD) enables and disables the reference circuit. REFOUT has approximately 17kΩ to GND when the MAX12557 is powered down. The reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12557 or when PD transitions from high to low.

The internal bandgap reference produces a buffered reference voltage of 2.048V ±1% at the REFOUT pin with a ±50ppm/°C temperature coefficient. Connect an external ≥0.1µF bypass capacitor from REFOUT to GND for stability. REFOUT sources up to 1mA and sinks up to 0.1mA for external circuits with a 35mV/mA load regulation. Short-circuit protection limits I

REFOUT

to a 2.1mA source current when shorted to GND and a

0.24mA sink current when shorted to VDD. Similar to REFOUT, REFIN should be bypassed with a 4.7µF capacitor to GND.

Reference Configurations

The MAX12557 full-scale analog input range is ±2/3 x V

REF

with a VDD/ 2 ±0.5V common-mode input range.

REF

is the voltage difference between REFAP (REFBP) and REFAN (REFBN). The MAX12557 provides three modes of reference operation. The voltage at REFIN (V

REFIN

) selects the reference operation mode (Table 1).

Connect REFOUT to REFIN either with a direct short or through a resistive divider to enter internal reference mode. COM_, REF_P, and REF_N are low-impedance outputs with V

COM_

= VDD/ 2, V

REFP

= VDD/ 2 + 3/8 x

REFIN

, and V

REF_N

= VDD/ 2 - 3/8 x V

REFIN

. Bypass

REF_P, REF_N, and COM_ each with a 0.1µF capacitor

Dual, 65Msps, 14-Bit, IF/Baseband ADC

16 ______________________________________________________________________________________

REFIN

REFERENCE MODE

35% V

REFOUT

to 100%

REFOUT

Internal Reference Mode. REFIN is driven by REFOUT either through a direct short or a resistive divider. V

COM_

= VDD / 2

REF_P

= VDD / 2 + 3/8 x V

REFIN

REF_N

= VDD / 2 - 3/8 x V

REFIN

0.7V to 2.3V

Buffered External Reference Mode. An external 0.7V to 2.3V reference voltage is applied to REFIN. V

COM_

= VDD / 2

REF_P

= VDD / 2 + 3/8 x V

REFIN

REF_N

= VDD / 2 - 3/8 x V

REFIN

<0.5V

U nb uffer ed E xter nal Refer ence M od e. RE F_P , RE F_N , and C O M _ ar e d r i ven b y exter nal r efer ence sour ces. The ful l - sc al e

anal og i np ut r ang e i s ± ( V

R E F _P

- V

R E F _N

) x 2/3.

Table 1. Reference Modes

MAX12557

PAR

2pF

BOND WIRE

INDUCTANCE

1.5nH

IN_P

SAMPLING

CLOCK

*THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS:

SAMPLE

4.5pF

PAR

2pF

BOND WIRE

INDUCTANCE

1.5nH

IN_N

SAMPLE

4.5pF

RIN =

CLK

x C

SAMPLE

Figure 3. Internal T/H Circuit

to GND. Bypass REF_P to REF_N with a 10µF capacitor. Bypass REFIN and REFOUT to GND with a 0.1µF capacitor. The REFIN input impedance is very large (>50MΩ). When driving REFIN through a resistive divider, use resistances ≥10kΩ to avoid loading REFOUT.

Buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12557’s internal bandgap reference. In buffered external reference mode, apply a stable reference voltage source between 0.7V to 2.3V at REFIN. Pins COM_, REF_P, and REF_N are low-impedance outputs with V

COM_

= VDD/ 2, V

REF_P

= VDD/ 2 + 3/8 x V

REFIN

, and

REF_N

= VDD/ 2 - 3/8 x V

REFIN

. Bypass REF_P, REF_N, and COM_ each with a 0.1µF capacitor to GND. Bypass REF_P to REF_N with a 10µF capacitor.

Connect REFIN to GND to enter unbuffered external reference mode. Connecting REFIN to GND deactivates the on-chip reference buffers for COM_, REF_P, and REF_N. With their buffers deactivated, COM_, REF_P, and REF_N become high-impedance inputs and must be driven with separate, external reference sources. Drive V

COM_

to VDD/ 2 ±5%, and drive REF_P and

REF_N so V

COM_

= (V

REF_P_

+ V

REF_N_

) / 2. The analog

input range is ±(V

REF_P_

- V

REF_N

) x 2/3. Bypass REF_P, REF_N, and COM_ each with a 0.1µF capacitor to GND. Bypass REF_P to REF_N with a 10µF capacitor.

For all reference modes, bypass REFOUT with a 0.1µF and REFIN with a 4.7µF capacitor to GND.

The MAX12557 also features a shared reference mode, in which the user can achieve better channel-to-channel matching. When sharing the reference (SHREF = VDD), externally connect REFAP and REFBP together to ensure that V

REFAP

= V

REFBP

. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that V

REFAN

= V

REFBN

Connect SHREF to GND to disable the shared reference mode of the MAX12557. In this independent reference mode, a better channel-to-channel isolation is achieved.

For detailed circuit suggestions and how to drive the ADC in buffered/unbuffered external reference mode, see the Applications Information section.

Clock Duty-Cycle Equalizer

The MAX12557 has an internal clock duty-cycle equalizer, which makes the converter insensitive to the duty cycle of the signal applied to CLKP and CLKN. The converters allow clock duty-cycle variations from 25% to 75% without negatively impacting the dynamic performance.

The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX12557 requires approximately 100 clock cycles to acquire and lock to new clock frequencies.

Clock Input and Clock Control Lines

The MAX12557 accepts both differential and singleended clock inputs with a wide 25% to 75% input clock duty cycle. For single-ended clock input operation, connect DIFFCLK/SECLK and CLKN to GND. Apply an external single-ended clock signal to CLKP. To reduce clock jitter, the external single-ended clock must have sharp falling edges. For differential clock input operation, connect DIFFCLK/SECLK to OVDD. Apply an external differential clock signal to CLKP and CLKN. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN enter high impedance when the MAX12557 is powered down (Figure 4).

Low clock jitter is required for the specified SNR performance of the MAX12557. The analog inputs are sampled on the falling (rising) edge of CLKP (CLKN), requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship:

where f

represents the analog input frequency and t

is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For instance, assuming that clock jitter is the only noise source, to obtain the specified 72.5dB of SNR with an input frequency of 175MHz the system must have less than

0.21ps of clock jitter. However, in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.14ps to obtain the specified 72.5dBc of SNR at 175MHz.

Clock-Divider Control Inputs (DIV2, DIV4)

The MAX12557 features three different modes of sampling/clock operation (see Table 2). Pulling both control lines low, the clock-divider function is disabled and the converters sample at full clock speed. Pulling DIV4 low and DIV2 high enables the divide-by-two feature, which sets the sampling speed to one-half the selected clock frequency. In divide-by-four mode, the converter sampling speed is set to one-fourth the clock speed of the MAX12557. Divide-by-four mode is achieved by applying a high level to DIV4 and a low level to DIV2. The option to

SNR

IN J

log

=×

×× ×

 



 



2 π

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 17

MAX12557

select either one-half or one-fourth of the clock speed for sampling provides design flexibility, relaxes clock requirements, and can minimize clock jitter.

System Timing Requirements

Figure 5 shows the timing relationship between the clock, analog inputs, DAV indicator, DOR_ indicators, and the resulting output data. The analog input is sampled on the falling (rising) edge of CLKP (CLKN) and the resulting data appears at the digital outputs 8 clock cycles later.

The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end cir-

cuitry can be latched with the rising edge of the conversion clock (CLKP - CLKN).

Data-Valid Output

DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. The MAX12557 output data changes on the falling edge of DAV, and DAV rises once the output data is valid. The falling edge of DAV is synchronized to have a 5.4ns delay from the falling edge of the input clock. Output data at D0A/B–D13A/B and DORA/B are valid from 7ns before the rising edge of DAV to 7ns after the rising edge of DAV.

DAV enters high impedance when the MAX12557 is powered down (PD = OVDD). DAV enters its highimpedance state 10ns after the rising edge of PD and becomes active again 10ns after PD transitions low.

DAV is capable of sinking and sourcing 600µA and has three times the driving capabilities of D0A/B–D13A/B and DORA/B. DAV is typically used to latch the MAX12557 output data into an external digital back-end circuit. Keep the capacitive load on DAV as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12557, thereby degrading its dynamic performance. Buffering DAV

Dual, 65Msps, 14-Bit, IF/Baseband ADC

18 ______________________________________________________________________________________

MAX12557

CLKP

CLKN

GND

10kΩ

DUTY-CYCLE

EQUALIZER

SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S

ARE OPEN IN

SINGLE-ENDED CLOCK MODE.

Figure 4. Siimplified Clock Input Circuit

DIV4 DIV2 FUNCTION

Clock Divider Disabled f

SAMPLE

= f

CLK

Divide-by-Two Clock Divider f

SAMPLE

= f

CLK

/ 2

Divide-by-Four Clock Divider f

SAMPLE

= f

CLK

/ 4

11Not Allowed

Table 2. Clock-Divider Control Inputs

DAV

N + 1

N +2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

DAV

SETUP

N - 1

N - 2

N - 3

HOLD

DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)

CLKN

CLKP

REF_P

- V

REF_N

) x 2/3

REF_N

- V

REF_P

) x 2/3

N + 4

D0_–D13_

DOR

8.0 CLOCK-CYCLE DATA LATENCY

SETUP

HOLD

NN + 1 N + 2 N + 3 N + 5 N + 6 N + 7N - 1N - 2N - 3 N + 9N + 8

Figure 5. System Timing Diagram

externally isolates it from heavy capacitive loads. Refer to the MAX12557 EV kit schematic for recommendations of how to drive the DAV signal through an external buffer.

Data Out-of-Range Indicator

The DORA and DORB digital outputs indicate when the analog input voltage is out of range. When DOR_ is high, the analog input is out of range. When DOR_ is low, the analog input is within range. The valid differential input range is from (V

REF_P

- V

REF_N

) x 2/3 to (V

REF_N

REF_P

) x 2/3. Signals outside of this valid differential

range cause DOR_ to assert high as shown in Table 1.

DOR is synchronized with DAV and transitions along with the output data D13–D0. There is an 8 clock-cycle latency in the DOR function as is with the output data (Figure 5). DOR_ is high impedance when the MAX12557 is in power-down (PD = high). DOR_ enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD’s falling edge.

Digital Output Data and Output Format Selection

The MAX12557 provides two 14-bit, parallel, tri-state output buses. D0A/B–D13A/B and DORA/B update on

the falling edge of DAV and are valid on the rising edge of DAV.

The MAX12557 output data format is either Gray code or two’s complement depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is set to two’s com- plement. See Figure 8 for a binary-to-Gray and Gray-tobinary code conversion example.

The following equations, Table 3, Figure 6, and Figure 7 define the relationship between the digital output and the analog input.

Gray Code (G/T = 1):

IN_P

- V

IN_N

= 2/3 x (V

REF_P

- V

REF_N

) x 2 x

(CODE10- 8192) / 16,384

Two’s Complement (G/T = 0):

IN_P

- V

IN_N

= 2/3 x (V

REF_P

- V

REF_N

) x 2 x

CODE

/ 16,384

where CODE10is the decimal equivalent of the digital output code as shown in Table 3.

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 19

GRAY-CODE OUTPUT CODE

(G/T = 1)

TWO’S-COMPLEMENT OUTPUT CODE

(G/T = 0)

BINARY D13A–D0A D13B–D0B

EQUIVALENT

D13A–D0A

DECIMAL

EQUIVALENT

(CODE10)

BINARY D13A–D0A D13B–D0B

EQUIVALENT

OF D13A–D0A D13B–D0B

DECIMAL

EQUIVALENT

(CODE10)

IN_P

- V

IN_N

REF_P

= 2.418V

REF_N

= 0.882V

10 0000 0000 0000

0x2000 +16,383

0x1FFF +8191

>+1.023875V

(DATA OUT OF

RANGE)

10 0000 0000 0000

0x2000 +16,383

0x1FFF +8191 +1.023875V

10 0000 0000 0001

0x2001 +16,382

0x1FFE +8190 +1.023750V

11 0000 0000 0011

0x3003 +8194

0x0002 +2 +0.000250V

11 0000 0000 0001

0x3001 +8193

0x0001 +1 +0.000125V

11 0000 0000 0000

0x3000 +8192

0x0000 0 +0.000000V

01 0000 0000 0000

0x1000 +8191

0x3FFF -1 -0.000125V

01 0000 0000 0001

0x1001 +8190

0x3FFE -2 -0.000250V

00 0000 0000 0001

0x0001 +1

0x2001 -8191 -1.023875V

00 0000 0000 0000

0x0000 0

0x2000 -8192 -1.024000V

00 0000 0000 0000

0x0000 0

0x2000 -8192

<-1.024000V

(DATA OUT OF

RANGE)

Table 3. Output Codes vs. Input Voltage

H EXA D ECIM A L

DOR

D13B–D0B

D13A–D0A D13B–D0B

HEXADECIMAL

DOR

01 1111 1111 1111 1

01 1111 1111 1111 0

01 1111 1111 1110 0

00 0000 0000 0010 0

00 0000 0000 0001 0

00 0000 0000 0000 0

11 1111 1111 1111 0

11 1111 1111 1110 0

10 0000 0000 0001 0

10 0000 0000 0000 0

10 0000 0000 0000 1

D13A–D0A D13B–D0B

MAX12557

The digital outputs D0A/B–D13A/B are high impedance when the MAX12557 is in power-down (PD = 1) mode. D0A/B–D13A/B enter this state 10ns after the rising edge of PD and become active again 10ns after PD transitions low.

Keep the capacitive load on the MAX12557 digital outputs D0A/B–D13A/B as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12557 and degrading its dynamic performance. Adding external digital buffers on the digital outputs helps isolate the MAX12557 from heavy capacitive loads. To improve the dynamic performance of the MAX12557, add 220Ω resistors in series with the digital outputs close to the MAX12557. Refer to the MAX12557 EV kit schematic for guidelines of how to drive the digital outputs through 220Ω series resistors and external digital output buffers.

Power-Down Input

The MAX12557 has two power modes that are controlled with a power-down digital input (PD). With PD low, the MAX12557 is in its normal operating mode. With PD high, the MAX12557 is in power-down mode.

The power-down mode allows the MAX12557 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX12557 parallel output bus goes high-impedance in power-down mode, allowing other devices on the bus to be accessed.

In power-down mode all internal circuits are off, the analog supply current reduces to less than 50µA, and the digital supply current reduces to 1µA. The following list shows the state of the analog inputs and digital outputs in power-down mode.

1) INAP/B, INAN/B analog inputs are disconnected from the internal input amplifier (Figure 3).

2) REFOUT has approximately 17kΩ to GND.

3) REFAP/B, COMA/B, REFAN/B enter a high-impedance state with respect to V

and GND, but there

is an internal 4kΩ resistor between REFAP/B and COMA/B as well as an internal 4kΩ resistor between REFAN/B and COMA/B.

4) D0A–D13A, D0B–D13B, DORA, and DORB enter a high-impedance state.

5) DAV enters a high-impedance state.

6) CLKP, CLKN clock inputs enter a high-impedance state (Figure 4).

The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REF_P, REF_N, and COM_. In internal reference mode and buffered external reference mode the wake-up time is typically 10ms. When operating in the unbuffered external reference mode the wake-up time is dependent on the external reference drivers.

Dual, 65Msps, 14-Bit, IF/Baseband ADC

20 ______________________________________________________________________________________

DIFFERENTIAL INPUT VOLTAGE (LSB)

TWO'S-COMPLEMENT OUTPUT CODE (LSB)

-8189 +8191+8189-1 0 +1-8191

0x2000

0x2001

0x2002

0x2003

0x1FFF 0x1FFE

0x1FFD

0x3FFF

0x0000

0x0001

2/3 x (V

REFP

- V

REFN

) 2/3 x (V

REFP

- V

REFN

)

1 LSB = 4/3 x (V

REFP

- V

REFN

) / 16,384

Figure 6. Two’s-Complement Transfer Function (G/T= 0)

DIFFERENTIAL INPUT VOLTAGE (LSB)

GRAY OUTPUT CODE (LSB)

-8189 +8191+8189-1 0 +1-8191

0x0000

0x0001

0x0003

0x0002

0x2000 0x2001 0x2003

0x1000

0x3000

0x3001

2/3 x (V

REFP

- V

REFN

) 2/3 x (V

REFP

- V

REFN

)

1 LSB = 4/3 x (V

REFP

- V

REFN

) / 16,384

Figure 7. Gray-Code Transfer Function (G/T= 1)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 21

BINARY-TO-GRAY CODE CONVERSION

1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT.

01 10 0100 1100 BINARY

GRAY CODE0

2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

D13 D7 D3 D0

GRAYX = BINARYX +BINARY

X + 1

BIT POSITION

0110 0100 1100 BINARY

GRAY CODE0

BIT POSITION

GRAY

= BINARY12BINARY

GRAY12 = 1 0

GRAY

= 1

3) REPEAT STEP 2 UNTIL COMPLETE:

01 10 0100 1100 BINARY

GRAY CODE0

BIT POSITION

GRAY

= BINARY11BINARY

GRAY11 = 1 1

GRAY

= 0

4) THE FINAL GRAY-CODE CONVERSION IS:

01 10 0100 1100 BINARY

GRAY CODE0

BIT POSITION

101 11 01 1010

GRAY-TO-BINARY CODE CONVERSION

1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT.

2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

BINARY

= BINARY

X+1

BIT POSITION

BINARY

= BINARY13GRAY

BINARY12 = 0 1

BINARY

= 1

3) REPEAT STEP 2 UNTIL COMPLETE:

4) THE FINAL BINARY CONVERSION IS:

01 0 0 1110 1010

BINARY

GRAY CODE

BIT POSITION

0 BINARY

GRAY CODE01 0 0 11 01 1010

BINARY

= BINARY12GRAY

BINARY11 = 1 0

BINARY

= 1

GRAY

0101 1110 1010

BINARY

GRAY CODE

BIT POSITION

01 0 1110 1010

BINARY

GRAY CODE

BIT POSITION

01 1 1 0100 1100

AB Y=AB

00 01 10 11

0 1 1 0

EXCLUSIVE OR TRUTH TABLE

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION:

FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT FORMAT OF THE MAX12557 IS TWO'S-COMPLEMENT BINARY, HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT.

D11

D13 D7 D3 D0

D11

110

D13 D7 D3 D0

D11

D13 D7 D3 D0

D11

D13 D7 D3 D0

D11

D13 D7 D3 D0

D11

D13 D7 D3 D0

D11

D13 D7 D3 D0

D11

Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion

MAX12557

Applications Information

Using Transformer Coupling

In general, the MAX12557 provides better SFDR and THD with fully differential input signals than singleended input drive, especially for input frequencies above 125MHz. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode.

An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12557 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/ 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the

overall distortion. The configuration of Figure 9 is good for frequencies up to Nyquist (f

CLK

/ 2).

The circuit of Figure 10 converts a single-ended input signal to fully differential just as Figure 9. However, Figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75Ω and 113Ω termination resistors provide an equivalent 50Ω termination to the signal source. The second set of termination resistors connects to COM_ providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input frequencies. These 0Ω resistors can be replaced with lowvalue resistors to limit the input bandwidth.

Single-Ended AC-Coupled Input Signal

Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.

Dual, 65Msps, 14-Bit, IF/Baseband ADC

22 ______________________________________________________________________________________

MAX12557

N.C.

0.1µF

MINICIRCUITS

TT1-6

T1-1T

24.9Ω

5.6pF

0.1µF

IN_P

COM_

IN_N

Figure 9. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist

N.C.

0.1µF

MINICIRCUITS

ADT1-1WT

5.6pF

IN_P

COM_

IN_N

*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.

N.C.

MINICIRCUITS

ADT1-1WT

N.C.

75Ω 1%

113Ω

0.5%

113Ω

0.5%

0.1µF

0Ω*

MAX12557

Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist

MAX12557

MAX4108

0.1µF

0Ω

5.6pF

IN_P

COM_

IN_N

100Ω

24.9Ω

5.6pF

Figure 11. Single-Ended, AC-Coupled Input Drive

Buffered External Reference Drives

Multiple ADCs

The buffered external reference mode allows for more control over the MAX12557 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ.

Figure 12 shows the MAX6029 precision 2.048V bandgap reference used as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a single-pole 10Hz LP filter to the MAX4230.

The MAX4250 buffers the 2.048V reference and provides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12557.

Unbuffered External Reference Drives

Multiple ADCs

The unbuffered external reference mode allows for precise control over the MAX12557 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal refer-

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 23

MAX4230

0.1µF

1µF

REFIN

GND

0.1µF

47Ω

3.3V

2.048V

16.2kΩ

REFOUT

0.1µF

REF_P

REF_N

COM_

0.1µF

2.2µF

0.1µF

3.3V

1.47kΩ

300µF 6V

NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT.

10µF

0.1µF

REFIN

GND

REFOUT

0.1µF

REF_P

REF_N

COM_

0.1µF

2.2µF

0.1µF

10µF

0.1µF

MAX12557

MAX6029

(EUK21)

MAX12557

Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference

MAX12557

ence, allowing REF_P, REF_N, and COM_ to be driven directly by a set of external reference sources.

Figure 13 uses a MAX6029 precision 3.000V bandgap reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47µF capacitor along this chain creates a 10Hz LP filter. Three MAX4230 amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12557 REF_P, REF_N, and COM_ reference inputs. The feedback around the MAX4230 op amps provides additional 10Hz LP filtering. Reference voltages 2.413V and 0.880V set the full-scale analog input

range for the converter to ±1.022V (±[V

REF_P

- V

REF_N

]

x 2/3).

Note that one single power supply for all active circuit components removes any concern regarding powersupply sequencing when powering up or down.

Grounding, Bypassing, and

Board Layout

The MAX12557 requires high-speed board layout design techniques. Refer to the MAX12557 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-

Dual, 65Msps, 14-Bit, IF/Baseband ADC

24 ______________________________________________________________________________________

MAX12557

MAX4230

MAX6029

(EUK30)

0.1µF

0.47µF

10µF

47Ω

1.47kΩ

2.413V

330µF 6V

MAX4230

10µF

47Ω

1.47kΩ

1.647V

330µF 6V

MAX4230

10µF

47Ω

1.47kΩ

0.880V

330µF 6V

REF_P

REF_N

COM_

GND

REFIN

3.3V

REFOUT

0.1µF

10µF

0.1µF

2.2µF

0.1µF

20kΩ 1%

52.3kΩ 1%

0.1µF

MAX12557

REF_P

REF_N

COM_

GND

REFIN

REFOUT

0.1µF

10µF

0.1µF

2.2µF

0.1µF

Figure 13. External Unbuffered Reference Driving Multiple ADCs

mount devices for minimum inductance. Bypass VDDto GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor. Bypass OVDDto GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor. High-frequency bypassing/decoupling capacitors should be located as close as possible to the converter supply pins.

Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All grounds and the exposed backside paddle of the MAX12557 must be connected to the same ground plane. The MAX12557 relies on the exposed backside paddle connection for a low-inductance ground connection. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground.

Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns.

Ensure that the differential, analog input network layout is symmetric and that all parasitic components are balanced equally. Refer to the MAX12557 EV kit data sheet for an example of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer function from a straight line. For the MAX12557, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX12557, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX12557 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive fullscale MAX12557 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.

Small-Signal Noise Floor (SSNF)

SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with a -35dBFS amplitude. This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digital receiver signal path.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):

SNR

[max]

= 6.02 × N + 1.76

In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 through HD7), and the DC offset.

SNR = 20 x log (SIGNAL

RMS

/ NOISE

RMS

)

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 25

MAX12557

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V7are the amplitudes of the 2nd- through 7th-order harmonics (HD2 through HD7).

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.

Intermodulation Distortion (IMD)

IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f

IN1

and f

IN2

. The individual input tone levels are at -7dBFS. The intermodulation products are as follows:

2nd-Order Intermodulation Products (IM2):

IN1

+ f

IN2

, f

IN2

- f

IN1

3rd-Order Intermodulation Products (IM3):

2 x f

IN1

- f

IN2

, 2 x f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

2 x f

IN2

+ f

IN1

4th-Order Intermodulation Products (IM4):

3 x f

IN1

- f

IN2

, 3 x f

IN2

- f

IN1

, 3 x f

IN1

+ f

IN2

3 x f

IN2

+ f

IN1,

2 x f

IN1

- 2 x f

IN2,

2 x f

IN1

+ 2 x f

IN2,

2 x f

IN2

- 2 x f

IN1

5th-Order Intermodulation Products (IM5):

3 x f

IN1

- 2 x f

IN2

, 3 x f

IN2

- 2 x f

IN1

, 3 x f

IN1

+ 2 x f

IN2

3 x f

IN2

+ 2 x f

IN1,

4 x f

IN1

- f

IN2,

4 x f

IN2

- f

IN1,

4 x f

IN1

+ f

IN2,

4 x f

IN2

+ f

IN1

3rd-Order Intermodulation (IM3)

IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f

IN1

and f

IN2

. The individual input tone levels are at -7dBFS. The 3rdorder intermodulation products are 2 x f

IN1

- f

IN2

, 2 x

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

Aperture Jitter

Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14).

Full-Power Bandwidth

A large -0.2dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as the full-power input bandwidth frequency.

Output Noise (n

OUT

)

The output noise (n

OUT

) parameter is similar to thermal plus quantization noise and is an indication of the converter’s overall noise performance.

No fundamental input tone is used to test for n

OUT

. IN_P, IN_N, and COM_ are connected together and 1024k data points are collected. n

OUT

is computed by taking the RMS value of the collected data points after the mean is removed.

Overdrive Recovery Time

Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX12557 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%. The MAX12557 requires one clock cycle to recover from the overdrive condition.

Crosstalk

Coupling onto one channel being driven by a (-0.5dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components.

THD

VVVVVV

log

=×

+++++





 





 

324

Dual, 65Msps, 14-Bit, IF/Baseband ADC

26 ______________________________________________________________________________________

T/H

TRACKHOLD HOLD

CLKN

CLKP

ANALOG

INPUT

SAMPLED

DATA

Figure 14. T/H Aperture Timing

Gain Matching

Gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in gain is reported (typically in dB) as gain matching.

Offset Matching

Like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %FSR) as offset matching.

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

______________________________________________________________________________________ 27

5859606162 5455565763

REFBP

CLKN

THIN QFN

TOP VIEW

VDDVDDOVDDDORA

D13A

D12A

D11A

D10A

D9A

5253

D8A

D7A

DIV2

CLKP

DIV4

DDVDD

D1B

D0B

D3B

D2B

D4B

D2A

D1A

D0A

DAV

DORB

D13B

D12B

D11B

D10B

D9B

D8B

D7B

EXPOSED PADDLE (GND)

REFBN

GND

REFAN

REFAP

COMA

INBP

INBN

GND

COMB

GND

INAN

INAP

48 D3A

GND

G/T

656667

REFOUT

SHREF

REFIN

2322212019 2726252418 2928 323130

D5B

D6B

3433

D5A

D4A

51 D6A

GND 17

MAX12557

DIFFCLK/SECLK

Pin Configuration

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

68L QFN THIN.EPS

21-0142

PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm

21-0142

PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm

Maxim MAX12557 Specifications

Specifications and Main Features

Frequently Asked Questions

User Manual