MAXIM MAX12554 Technical data

General Description

The MAX12554 is a 3.3V, 14-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX12554 is optimized for high dynamic performance, low power, and small size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12554 ideal for intermediatefrequency (IF) sampling applications.

Powered from a single 3.3V supply, the MAX12554 consumes only 429mW while delivering a typical 70.9dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX12554 features a 300µW power-down mode to conserve power during idle periods.

A flexible reference structure allows the MAX12554 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12554 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.

The MAX12554 supports either a single-ended or differential input clock. Wide variations in the clock duty cycle are compensated with the ADC’s internal dutycycle equalizer (DCE).

ADC conversion results are available through a 14-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX12554 to interface with various logic levels.

The MAX12554 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range.

See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs.

Applications

IF and Baseband Communication Receivers

Cellular, Point-to-Point Microwave, HFC, WLAN

Medical Imaging Including Positron Emission

Tomography (PET)

Video Imaging

Portable Instrumentation

Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz

♦ Excellent Dynamic Performance

72.4dB/70.9dB SNR at fIN= 3MHz/175MHz

86.2dBc/82.5dBc SFDR at fIN= 3MHz/175MHz

♦ Low Noise Floor: -74.8dBFS

♦ 3.3V Low-Power Operation

396mW (Single-Ended Clock Mode) 429mW (Differential Clock Mode) 300µW (Power-Down Mode)

♦ Fully Differential or Single-Ended Analog Input

♦ Adjustable Full-Scale Analog Input Range

±0.35V to ±1.10V

♦ Common-Mode Reference

♦ CMOS-Compatible Outputs in Two’s Complement

or Gray Code

♦ Data-Valid Indicator Simplifies Digital Interface

♦ Data Out-of-Range Indicator

♦ Miniature, 6mm x 6mm x 0.8mm 40-Pin Thin QFN

Package with Exposed Paddle

♦ Evaluation Kit Available (Order MAX12555EVKIT)

MAX12554

14-Bit, 80Msps, 3.3V ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3440; Rev 0; 10/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART* PIN-PACKAGE PKG CODE

MAX12554ETL 40 Thin QFN T4066-3

MAX12554ETL+ 40 Thin QFN T4066-3

Pin-Compatible Versions

PART

SAMPLING

RATE

(Msps)

RESOLUTION

(BITS)

TARGET

APPLICATION

MAX12555

95 14

IF/Baseband

MAX12554

80 14

IF/Baseband

MAX12553

65 14

IF/Baseband

MAX19538

95 12

IF/Baseband

MAX1209

80 12 IF

MAX1211

65 12 IF

MAX1208

80 12 Baseband

MAX1207

65 12 Baseband

MAX1206

40 12 Baseband

Pin Configuration appears at end of data sheet.

+Denotes lead-free package. *All devices specified over the -40°C to +85°C operating range.

MAX12554

14-Bit, 80Msps, 3.3V ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

T = low, f

CLK

= 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND...........................................................-0.3V to +3.6V

to GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V

INP, INN to GND ...-0.3V to the lower of (V

+ 0.3V) and +3.6V

REFIN, REFOUT, REFP, REFN, COM

to GND................-0.3V to the lower of (V

+ 0.3V) and +3.6V

CLKP, CLKN, CLKTYP, G/T, DCE,

PD to GND ........-0.3V to the lower of (V

+ 0.3V) and +3.6V

D13–D0, DAV, DOR to GND....................-0.3V to (OV

+ 0.3V)

Continuous Power Dissipation (TA= +70°C)

40-Pin Thin QFN 6mm x 6mm x 0.8mm

(derated 26.3mW/°C above +70°C)........................2105.3mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering 10s) ..................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY (Note 2)

Resolution 14 Bits

Integral Nonlinearity INL fIN = 3MHz (Note 3)

LSB

Differential Nonlinearity DNL

= 3MHz, no missing codes over

temperature (Note 4)

-1

LSB

Offset Error V

REFIN

= 2.048V

%FS

Gain Error V

REFIN

= 2.048V

%FS

ANALOG INPUT (INP, INN)

Differential Input Voltage Range V

DIFF

Differential or single-ended inputs

Common-Mode Input Voltage

PAR

Fixed capacitance to ground 2

Input Capacitance (Figure 3)

Switched capacitance 4.5

CONVERSION RATE

Maximum Clock Frequency f

CLK

MHz

Minimum Clock Frequency 5

MHz

Data Latency Figure 6 8.0

Clock

cycles

DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)

Small-Signal Noise Floor SSNF Input at less than -35dBFS

dBFS

fIN = 3MHz at -0.5dBFS (Note 5)

72.4

fIN = 40MHz at -0.5dBFS 72.0

fIN = 70MHz at -0.5dBFS 71.9

Signal-to-Noise Ratio SNR

= 175MHz at -0.5dBFS (Note 5)

70.9

fIN = 3MHz at -0.5dBFS (Note 5)

72.1

fIN = 40MHz at -0.5dBFS 71.7

fIN = 70MHz at -0.5dBFS 71.6

Signal-to-Noise and Distortion SINAD

= 175MHz at -0.5dBFS (Note 5)

70.3

±2.4 ±4.9

±0.5 +1.3

±0.1 ±0.72

SAMPLE

69.0

68.0

68.9

66.2

±0.5 ±4.9

±1.024

/ 2

-74.8

MAX12554

14-Bit, 80Msps, 3.3V ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

fIN = 3MHz at -0.5dBFS (Note 5)

86.2

fIN = 40MHz at -0.5dBFS 84.6

fIN = 70MHz at -0.5dBFS 85.4

Spurious-Free Dynamic Range SFDR

= 175MHz at -0.5dBFS (Note 5)

82.5

dBc

fIN = 3MHz at -0.5dBFS

fIN = 40MHz at -0.5dBFS

fIN = 70MHz at -0.5dBFS

Total Harmonic Distortion THD

= 175MHz at -0.5dBFS

dBc

fIN = 3MHz at -0.5dBFS -91

fIN = 40MHz at -0.5dBFS -91

fIN = 70MHz at -0.5dBFS -86

Second Harmonic HD2

= 175MHz at -0.5dBFS -85

dBc

fIN = 3MHz at -0.5dBFS -89

fIN = 40MHz at -0.5dBFS -85

fIN = 70MHz at -0.5dBFS -88

Third Harmonic HD3

= 175MHz at -0.5dBFS -85

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

-83

Intermodulation Distortion IMD

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

-80

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

-87

Third-Order Intermodulation IM3

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

-84

dBc

IN1

= 68.5MHz at -7dBFS

IN2

= 71.5MHz at -7dBFS

Two-Tone Spurious-Free Dynamic Range

IN1

= 172.5MHz at -7dBFS

IN2

= 177.5MHz at -7dBFS

dBc

Aperture Delay t

Figure 4 1.2 ns

Aperture Jitter t

Figure 4 <0.2

Output Noise n

OUT

INP = INN = COM 1.05

Overdrive Recovery Time ±10% beyond full scale 1

Clock

SFDR

76.5

69.0

-84.8 -75.9

-84.0

-82.6

-79.4 -69.0

RMS

LSB

cycles

RMS

MAX12554

14-Bit, 80Msps, 3.3V ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

INTERNAL REFERENCE (REFIN = REFOUT; V

R EF P

, V

R EF N

, and V

C OM

are generated internally)

REFOUT Output Voltage

COM Output Voltage V

COM

/ 2

Differential-Reference Output Voltage

REF

= V

REFP

- V

REFN

= V

REFIN

x 3/4

REFOUT Load Regulation -1.0mA < I

REFOUT

< +0.1mA 35

mV/mA

REFOUT Temperature Coefficient

REF

ppm/°C

Short to VDD—sinking

REFOUT Short-Circuit Current

Short to GND—sourcing 2.1

B U F F ER ED EXT ER N A L R EF ER EN C E ( R EF IN d r iv e n e x t e r n a lly ; V

R EF IN

= 2.0 4 8 V, V

R EF P

, V

R EF N

, a n d V

C OM

a r e g e n e r a t e d in t e r n a lly )

REFIN Input Voltage V

REFIN

REFP Output Voltage V

REFP

/ 2) + (V

REFIN

x 3/8)

REFN Output Voltage V

REFN

/ 2) - (V

REFIN

x 3/8)

COM Output Voltage V

COM

/ 2

Differential-Reference Output Voltage

REF

= V

REFP

- V

REFN

= V

REFIN

x 3/4

Differential-Reference Temperature Coefficient

ppm/°C

REFIN Input Resistance

MΩ

UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V

REFP

, V

REFN

, and V

COM

are applied externally)

COM Input Voltage V

COM

VDD/2

REFP Input Voltage V

REFP

- V

COM

REFN Input Voltage V

REFN

- V

COM

Differential-Reference Input Voltage

REF

= V

REFP

- V

REFN

= V

REFIN

x 3/4

REFP Sink Current I

REFP

= 2.418V 1.2 mA

REFN Source Current I

REFN

= 0.882V

COM Sink Current I

COM

= 1.650V

REFP, REFN Capacitance 13 pF

COM Capacitance 6pF

CLOCK INPUTS (CLKP, CLKN)

Single-Ended Input High Threshold

CLKTYP = GND, CLKN = GND

0.8 x V

Single-Ended Input Low Threshold

CLKTYP = GND, CLKN = GND

0.2 x V

Minimum Differential Input Voltage Swing

CLKTYP = high 0.2 V

P-P

SYMBOL

MIN TYP MAX

REFOUT

1.979 2.048 2.068

1.65

1.60 1.65 1.70

1.462 1.595

1.536

+50

0.24

2.048

2.418

0.882

±25

>50

1.65

0.768

-0.768

1.536

0.85

MAX12554

14-Bit, 80Msps, 3.3V ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

Differential Input Common-Mode Voltage

CLKTYP = high

Input Resistance R

CLK

Figure 5 5 kΩ

Input Capacitance C

CLK

2pF

DIGITAL INPUTS (CLKTYP, G/TTTT, PD)

Input High Threshold V

0.8 x V

Input Low Threshold V

0.2 x V

VIH = OV

±5

Input Leakage Current

= 0 ±5

µA

Input Capacitance C

DIN

5pF

DIGITAL OUTPUTS (D13–D0, DAV, DOR)

D13–D0, DOR, I

SINK

= 200µA 0.2

Output-Voltage Low V

DAV, I

SINK

= 600µA 0.2

D13–D0, DOR, I

SOURCE

= 200µA

0.2

Output-Voltage High V

DAV, I

SOURCE

= 600µA

0.2

Tri-State Leakage Current I

LEAK

(Note 6) ±5 µA

D13–D0, DOR Tri-State Output Capacitance

OUT

(Note 6) 3 pF

D AV Tr i - S tate O utp ut C ap aci tance

DAV

(Note 6) 6 pF

POWER REQUIREMENTS

Analog Supply Voltage V

3.3

Digital Output Supply Voltage OV

1.7 1.8

Normal operating mode, f

= 175MHz at -0.5dBFS,

CLKTYP = GND, single-ended clock

Normal operating mode, f

= 175MHz at -0.5dBFS,

CLKTYP = OV

DD,

differential clock

145

Analog Supply Current I

VDD

Power-down mode clock idle, PD = OV

0.1

MIN TYP MAX

/ 2

SYMBOL

OVDD -

3.15

120

130

3.60

VDD +

0.3V

MAX12554

14-Bit, 80Msps, 3.3V ADC

6 _______________________________________________________________________________________

Note 1: Specifications ≥+25°C guaranteed by production test; <+25°C guaranteed by design and characterization. Note 2: See definitions in the Parameter Definitions section at the end of this data sheet. Note 3: Guaranteed by design and characterization. Note 4: Specifications guaranteed by design and characterization. Devices tested to ensure no missing codes during production

test.

Note 5: Due to test-equipment-jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from

the spectral analysis.

Note 6: During power-down, D13–D0, DOR, and DAV are high impedance. Note 7: Digital outputs settle to V

or VIL.

ELECTRICAL CHARACTERISTICS (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at

= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

Normal operating mode, f

= 175MHz at -0.5dBFS,

CLKTYP = GND, single-ended clock

Normal operating mode, f

= 175MHz at -0.5dBFS,

CLKTYP = OV

, differential clock

Analog Power Dissipation P

DISS

Power-down mode clock idle, PD = OV

0.3

Normal operating mode, f

= 175MHz at -0.5dBFS,

= 1.8V, CL ≈ 5pF

8.6 mA

Digital Output Supply Current I

OVDD

Power-down mode clock idle, PD = OV

8µA

TIMING CHARACTERISTICS (Figure 6)

Clock Pulse-Width High t

6.2 ns

Clock Pulse-Width Low t

6.2 ns

Data-Valid Delay t

DAV

CL = 5pF (Note 7) 5.2 ns

Data Setup Time Before Rising Edge of DAV

SETUP

CL = 5pF (Note 3, Note 7) 5.5 ns

Data Hold Time After Rising Edge of DAV

HOLD

CL = 5pF (Note 3, Note 7) 5.5 ns

Wake-Up Time from Power-Down

WAKE

REFIN

= 2.048V 10 ms

SYMBOL

MIN TYP MAX

396

429 479

MAX12554

14-Bit, 80Msps, 3.3V ADC

_______________________________________________________________________________________ 7

-110

-100

-20

-80

-90

-70

-60

-40

-10

-50

-30

0101520525303540

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

FREQUENCY (MHz)

AMPLITUDE (dBFS)

MAX12554toc02

CLK

= 80MHz

= 39.89257813MHz

= -0.4dBFS SNR = 73.00dB SINAD = 72.02dB THD = -78.9dBc SFDR = 79.6dBc

HD3

-110

-100

-20

-80

-90

-70

-60

-40

-10

-50

-30

0101520525303540

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

AMPLITUDE (dBFS)

MAX12554toc03

CLK

= 80MHz

= 69.87304688MHz

= -0.6dBFS SNR = 72.65dB SINAD = 72.23dB THD = -82.6dBc SFDR = 84.6dBc

HD3

HD2

-3

-1

-2

081924096 12288 16384

INTEGRAL NONLINEARITY

MAX12554toc08

DIGITAL OUTPUT CODE

INL (LSB)

-1.0

-0.4

-0.8

0.4

0.8

-0.6

0.2

-0.2

0.6

1.0

0 81924096 12288 16384

DIFFERENTIAL NONLINEARITY

MAX12554toc09

DIGITAL OUTPUT CODE

DNL (LSB)

Typical Operating Characteristics

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = +25°C, unless otherwise noted.)

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

= 80MHz

CLK

= 2.99804688MHz

= -0.5dBFS

HD2

HD3

SNR = 73.49dB SINAD = 73.26dB THD = -86.2dBc SFDR = 89.2dBc

MAX12554toc01

0101520525303540

FREQUENCY (MHz)

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

= 80MHz

CLK

= 175.1074219MHz

= -0.5dBFS

HD5

SNR = 71.17dB SINAD = 70.50dB THD = -78.9dBc SFDR = 80.7dBc

HD2

MAX12554toc04

HD3

0101520525303540

FREQUENCY (MHz)

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110 0101520525303540

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

= 80MHz

CLK

= 225.1074219MHz

= -0.5dBFS

SNR = 70.37dB SINAD = 69.83dB THD = -79.2dBc SFDR = 83.6dBc

HD3HD2HD5

FREQUENCY (MHz)

MAX12554toc05

TWO-TONE FFT PLOT

(16,384-POINT DATA RECORD)

-10

-20

IN2

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110 0101520525303540

= 80MHz

CLK

= 68.49121MHz

IN1

= -7.0dBFS

IN1

= 71.48926MHz

IN2

= -7.0dBFS

IN2

= 84.6dBc

SFDR

IMD = -81.5dBc IM3 = -82.5dBc

2 x f

- f

IN2

IN1

2 x f

- f

IN1

IN2

+ f

IN1

IN2

FREQUENCY (MHz)

2 x f

IN2

2 x f

MAX12554toc06

+ f

IN1

+ f

IN1

IN2

TWO-TONE FFT PLOT

(16,384-POINT DATA RECORD)

-10 f

-20

IN1

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

IN2

0101520525303540

= 80.0017MHz

CLK

= 172.4695MHz

IN1

= -7.0dBFS

IN1

= 177.4696MHz

IN2

= -7.0dBFS

IN2

SFDR

IMD = -80.7dBc IM3 = -95.3dBc

3 x f

+ 2 x f

IN1

FREQUENCY (MHz)

= 80.3dBc

IN2

+ f

IN1

IN2

MAX12554toc07

MAX12554

14-Bit, 80Msps, 3.3V ADC

8 _______________________________________________________________________________________

25 45 65 85 105 125

SNR, SINAD

vs. SAMPLING RATE

MAX12554 toc10

CLK

(MHz)

SNR, SINAD (dB)

fIN = 70MHz

SNR SINAD

100

25 45 65 85 105 125

SFDR, -THD

vs. SAMPLING RATE

MAX12554 toc11

CLK

(MHz)

SFDR, -THD (dBc)

fIN = 70MHz

SFDR

-THD

200

250

300

350

400

450

500

550

600

25 45 65 85 105 125

POWER DISSIPATION

vs. SAMPLING RATE

MAX12554 toc12

CLK

(MHz)

POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK f

= 70MHz

≈ 5pF

ANALOG + DIGITAL POWER ANALOG POWER

25 45 65 85 105 125

SNR, SINAD

vs. SAMPLING RATE

MAX12554toc13

CLK

(MHz)

SNR, SINAD (dB)

fIN = 175MHz

SNR SINAD

100

25 45 65 85 105 125

SFDR, -THD

vs. SAMPLING RATE

MAX12554toc14

CLK

(MHz)

SFDR, -THD (dBc)

fIN = 175MHz

SFDR

-THD

200

250

300

350

400

450

500

550

600

25 45 65 85 105 125

POWER DISSIPATION

vs. SAMPLING RATE

MAX12554toc15

CLK

(MHz)

POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK f

= 175MHz

≈ 5pF

ANALOG + DIGITAL POWER ANALOG POWER

0 100 200 30050 150 250 350 400

SNR, SINAD

vs. ANALOG INPUT FREQUENCY

MAX12554toc16

ANALOG INPUT FREQUENCY (MHz)

SNR, SINAD (dB)

SNR SINAD

100

050 150 250100 200 300 350 400

SFDR, -THD

vs. ANALOG INPUT FREQUENCY

MAX12554toc17

ANALOG INPUT FREQUENCY (MHz)

SFDR, -THD (dBc)

SFDR

-THD

200

250

300

350

400

450

500

550

600

050 150 250100 200 300 350 400

POWER DISSIPATION

vs. ANALOG INPUT FREQUENCY

MAX12554toc18

ANALOG INPUT FREQUENCY (MHz)

POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK C

≈ 5pF

ANALOG + DIGITAL POWER ANALOG POWER

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = +25°C, unless otherwise noted.)

MAX12554

14-Bit, 80Msps, 3.3V ADC

_______________________________________________________________________________________ 9

-40 -30 -20 -10-35 -25 -15 -5 0

SNR, SINAD

vs. ANALOG INPUT AMPLITUDE

MAX12554toc19

ANALOG INPUT AMPLITUDE (dBFS)

SNR, SINAD (dB)

SNR SINAD

fIN = 175MHz

-40 -35 -25 -15-30 -20 -10 -5 0

SFDR, -THD

vs. ANALOG INPUT AMPLITUDE

MAX12554toc20

ANALOG INPUT AMPLITUDE (dBFS)

SFDR, -THD (dBc)

SFDR

-THD

fIN = 175MHz

200

250

300

350

400

450

500

550

600

-40 -35 -25 -15-30 -20 -10 -5 0

POWER DISSIPATION

vs. ANALOG INPUT AMPLITUDE

MAX12554toc21

ANALOG INPUT AMPLITUDE (dBFS)

POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK f

= 175MHz

≈ 5pF

ANALOG + DIGITAL POWER ANALOG POWER

2.8 3.0 3.2 3.4 3.6

SNR, SINAD

vs. ANALOG SUPPLY VOLTAGE

MAX12554toc22

AVDD (V)

SNR, SINAD (dB)

SNR SINAD

fIN = 175MHz

100

2.8 3.0 3.2 3.4 3.6

SFDR, -THD

vs. ANALOG SUPPLY VOLTAGE

MAX12554toc23

AVDD (V)

SFDR, -THD (dBc)

SFDR

-THD

fIN = 175MHz

200

250

300

350

400

450

550

500

600

2.8 3.0 3.2 3.4 3.6

POWER DISSIPATION

vs. ANALOG SUPPLY VOLTAGE

MAX12554toc24

AVDD (V)

POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK f

= 175MHz

≈ 5pF

ANALOG + DIGITAL POWER ANALOG POWER

1.4 2.2 3.01.8 2.6 3.4 3.8

SNR, SINAD

vs. DIGITAL SUPPLY VOLTAGE

MAX12554toc25

OVDD (V)

SNR, SINAD (dB)

SNR SINAD

fIN = 175MHz

100

1.4 2.2 3.01.8 2.6 3.4 3.8

SFDR, -THD

vs. DIGITAL SUPPLY VOLTAGE

MAX12554toc26

OVDD (V)

SFDR, -THD (dBc)

SFDR

-THD

fIN = 175MHz

200

250

300

350

400

450

550

500

600

1.4 2.2 3.01.8 2.6 3.4 3.8

POWER DISSIPATION

vs. DIGITAL SUPPLY VOLTAGE

MAX12554toc27

OVDD (V)

POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK f

= 175MHz

≈ 5pF

ANALOG + DIGITAL POWER ANALOG POWER

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = +25°C, unless otherwise noted.)

MAX12554

14-Bit, 80Msps, 3.3V ADC

10 ______________________________________________________________________________________

SNR, SINAD vs. TEMPERATURE

MAX12554 toc28

TEMPERATURE (°C)

SNR, SINAD (dB)

603510-15

-40 85

SNR SINAD

fIN = 175MHz

100

SFDR, -THD vs. TEMPERATURE

MAX12554 toc29

SFDR, -THD (dBc)

TEMPERATURE (°C)

603510-15-40 85

SFDR

-THD

fIN = 175MHz

200

250

300

350

400

450

500

550

600

POWER DISSIPATION

vs. TEMPERATURE

MAX12554toc30

ANALOG POWER DISSIPATION (mW)

DIFFERENTIAL CLOCK

= 175MHz

≈ 5pF

TEMPERATURE (°C)

603510-15-40 85

ANALOG + DIGITAL POWER ANALOG POWER

OFFSET ERROR vs. TEMPERATURE

MAX12554 toc31

OFFSET ERROR (%FS)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

TEMPERATURE (°C)

603510-15-40 85

REFIN

= 2.048V

-2.0

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

GAIN ERROR vs. TEMPERATURE

MAX12554toc32

GAIN ERROR (%FS)

TEMPERATURE (°C)

603510-15-40 85

REFIN

= 2.048V

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = +25°C, unless otherwise noted.)

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 11

REFERENCE OUTPUT VOLTAGE

LOAD REGULATION

MAX12554 toc33

REFOUT

SINK CURRENT (mA)

REFOUT

(V)

0-0.5-1.0-1.5

1.96

1.97

1.98

1.99

2.00

2.01

2.02

2.03

2.04

2.05

1.95

-2.0 0.5

+85°C

+25°C

-40°C

REFERENCE OUTPUT VOLTAGE

SHORT-CIRCUIT PERFORMANCE

MAX12554 toc34

REFOUT

SINK CURRENT (mA)

REFOUT

(V)

0-1.0-2.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-3.0 1.0

+85°C

+25°C

-40°C

REFERENCE OUTPUT VOLTAGE

vs. TEMPERATURE

MAX12554 toc35

TEMPERATURE (°C)

REFOUT

(V)

603510-15

2.031

2.033

2.035

2.037

2.039

2.029

-40 85

REFP, COM, REFN LOAD REGULATION

MAX12554 toc36

SINK CURRENT (mA)

VOLTAGE (V)

10-1

0.5

1.0

1.5

2.0

2.5

3.0

-2 2

REFP

COM

REFN

INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE

REFP, COM, REFN

SHORT-CIRCUIT PERFORMACE

MAX12554 toc37

SINK CURRENT (mA)

VOLTAGE (V)

40-4

0.5

1.0

1.5

2.0

2.5

3.5

3.0

-8 128

REFP

COM

REFN

INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE

Typical Operating Characteristics (continued)

= 3.3V, OV

= 1.8V, GND = 0, REFIN = REFOUT (internal reference), V

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 80MHz (50% duty cycle, 1.4V

P-P

square wave), TA = +25°C, unless otherwise noted.)

MAX12554

14-Bit, 80Msps, 3.3V ADC

12 ______________________________________________________________________________________

PIN NAME FUNCTION

1 REFP

Positive Reference I/O. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3. Bypass REFP to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same

side of the PC board.

2 REFN

Negative Reference I/O. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3. Bypass REFN to GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same

side of the PC board.

3 COM

Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the opposite side of the PC board and connected to the MAX12554 through a via.

4, 7, 16,

GND Ground. Connect all ground pins and EP together.

5 INP Positive Analog Input

6INN Negative Analog Input

8 DCE

Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OV

or VDD) to enable the internal duty-cycle equalizer.

9 CLKN

Negative Clock Input. In differential clock input mode (CLKTYP = OV

or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND.

10 CLKP

Positive Clock Input. In differential clock input mode (CLKTYP = OV

or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND.

11 CLKTYP

Clock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OV

or VDD to define the differential clock input.

12–15, 36

Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of ≥2.2µF and 0.1µF. Connect all V

pins to the same potential.

17, 34 OV

Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of ≥2.2µF and 0.1µF.

18 DOR

Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6).

19 D13 CMOS Digital Output Bit 13 (MSB)

20 D12 CMOS Digital Output Bit 12

21 D11 CMOS Digital Output Bit 11

22 D10 CMOS Digital Output Bit 10

23 D9 CMOS Digital Output Bit 9

24 D8 CMOS Digital Output Bit 8

25 D7 CMOS Digital Output Bit 7

26 D6 CMOS Digital Output Bit 6

27 D5 CMOS Digital Output Bit 5

Pin Description

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 13

PIN NAME FUNCTION

28 D4 CMOS Digital Output Bit 4

29 D3 CMOS Digital Output Bit 3

30 D2 CMOS Digital Output Bit 2

31 D1 CMOS Digital Output Bit 1

32 D0 CMOS Digital Output Bit 0 (LSB)

33 DAV

Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the MAX12554 output data into an external back-end digital circuit.

37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.

38 REFOUT

Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor.

39 REFIN

Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a ≥0.1µF capacitor. In these modes, V

REFP

- V

REFN

= V

REFIN

x 3/4. For unbuffered external

reference mode operation, connect REFIN to GND.

40 G/T

Output-Format-Select Input. Connect G/T to GND for the two’s-complement digital output format. Connect G/T to OV

or VDD for the Gray code digital output format.

—EP

Exposed Paddle. The MAX12554 relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane.

Pin Description (continued)

MAX12554

−

DIGITAL ERROR CORRECTION

FLASH

ADC

T/H

DAC

STAGE 2

D13–D0

INP

INN

STAGE 1

T/H

STAGE 9

STAGE 10

END OF PIPE

OUTPUT DRIVERS

D13–D0

Figure 1. Pipeline Architecture—Stage Blocks

MAX12554

Detailed Description

The MAX12554 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output, the total clock-cycle latency is 8.0 clock cycles.

Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX12554 functional diagram.

Input Track-and-Hold (T/H) Circuit

Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a common-mode input voltage of V

/ 2 ±0.5V.

The MAX12554 sampling clock controls the ADC’s switched-capacitor T/H architecture (Figure 3) allowing the analog input signal to be stored as a charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these

capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle.

The analog input of the MAX12554 supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (V

/ 2). The MAX12554 provides the optimum

common-mode voltage of V

/ 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 10, 11, and 12.

Reference Output (REFOUT)

An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX12554. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires 10ms to power up and settle when power is applied to the MAX12554 or when PD transitions from high to low. REFOUT has approximately 17kΩ to GND when the MAX12554 is in power-down.

The internal bandgap reference and its buffer generate V

REFOUT

to be 2.048V. The reference temperature coeffi-

cient is typically +50ppm/°C. Connect an external ≥0.1µF bypass capacitor from REFOUT to GND for stability.

14-Bit, 80Msps, 3.3V ADC

14 ______________________________________________________________________________________

MAX12554

INP

INN

14-BIT

PIPELINE

ADC

DEC

REFERENCE

SYSTEM

COM

REFOUT

REFN

REFP

DAV

OUTPUT

DRIVERS

D13–D0

DOR

REFIN

T/H

POWER CONTROL

AND

BIAS CIRCUITS

CLKP

CLOCK

GENERATOR

AND

DUTY-CYCLE

EQUALIZER

CLKN

CLKTYP

GND

DCE

G/T

Figure 2. Simplified Functional Diagram

MAX12554

PAR

2pF

BOND WIRE

INDUCTANCE

1.5nH

INP

SAMPLING

CLOCK

*THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS:

SAMPLE

4.5pF

PAR

2pF

BOND WIRE

INDUCTANCE

1.5nH

INN

SAMPLE

4.5pF

SAMPLE

CLK

x C

SAMPLE

Figure 3. Simplified Input T/H Circuit

REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I

REFOUT

to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD.

Analog Inputs and Reference

Configurations

The MAX12554 full-scale analog input range is adjustable from ±0.35V to ±1.10V with a V

/ 2 ±0.5V commonmode input range. The MAX12554 provides three modes of reference operation. The voltage at REFIN (V

REFIN

)

sets the reference operation mode (Table 1).

To operate the MAX12554 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with V

COM

/ 2, V

REFP

= V

/ 2 + V

REFIN

x 3/8, and V

REFN

/ 2 - V

REFIN

x 3/8. The REFIN input impedance is

very large (>50MΩ). When driving REFIN through a

resistive divider, use resistances ≥10kΩ to avoid loading REFOUT.

Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX12554 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.2V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V

COM

= V

/ 2, V

REFP

= V

/ 2 + V

REFIN

x 3/8, and V

REFN

= V

/ 2 - V

REFIN

x 3/8.

To operate the MAX12554 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive V

COM

to V

/ 2

±5%, and drive REFP and REFN so V

COM

= (V

REFP

REFN

) / 2. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3.

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 15

T/H

CLKN

CLKP

TRACK HOLDTRACK HOLDTRACK HOLDTRACKHOLD

ANALOG

INPUT

SAMPLED

DATA

Figure 4. T/H Aperture Timing

REFIN

REFERENCE MODE

35% V

REFOUT

to 100%

REFOUT

Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is ±V

REFIN

/ 2:

COM

= V

/ 2

REFP

= V

/ 2 + V

REFIN

x 3/8

REFN

= V

/ 2 - V

REFIN

x 3/8

0.7V to 2.2V

Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN. The full-scale analog input range is ±V

REFIN

/ 2:

COM

= V

/ 2

REFP

= V

/ 2 + V

REFIN

x 3/8

REFN

= V

/ 2 - V

REFIN

x 3/8

<0.4V

Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is ±(V

REFP

- V

REFN

) x 2/3.

Table 1. Reference Modes

MAX12554

All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2µF capacitor to GND. Bypass REFP and REFN each with a 0.1µF capacitor to GND. Bypass REFP to REFN with a 1µF capacitor in parallel with a 10µF capacitor. Place the 1µF capacitor as close to

the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a

0.1µF capacitor.

For detailed circuit suggestions, see Figure 13 and Figure 14.

Clock Input and Clock Control Lines

(CLKP, CLKN, CLKTYP)

The MAX12554 accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock input operation, connect CLKTYP to OV

or VDD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines.

CLKP and CLKN are high impedance when the MAX12554 is powered down (Figure 5).

Low clock jitter is required for the specified SNR performance of the MAX12554. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship:

where fINrepresents the analog input frequency and t

is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 70.9dB of SNR with a 175MHz input frequency, the system must have less than 0.26ps of clock jitter. In actuality, there are other noise sources such as thermal noise and quantization noise that contribute to the system noise, requiring the clock jitter to be less than 0.14ps to obtain the specified 70.9dB of SNR at 175MHz.

Clock Duty-Cycle Equalizer (DCE)

Connect DCE high to enable the clock duty-cycle equalizer (DCE = OVDDor VDD). Connect DCE low to disable the clock duty-cycle equalizer (DCE = GND). With the clock duty-cycle equalizer enabled, the MAX12554 is insensitive to the duty cycle of the signal applied to CLKP and CLKN. Duty cycles from 35% to 65% are acceptable with the clock duty-cycle equalizer enabled.

The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX12554 requires approximately 100 clock cycles to acquire and lock to new clock frequencies.

Although not recommended, disabling the clock dutycycle equalizer reduces the analog supply current by

1.5mA. With the clock duty-cycle equalizer disabled, the MAX12554’s dynamic performance varies depending on the duty cycle of the signal applied to CLKP and CLKN.

SNR

IN J

log

=×

×π ×













14-Bit, 80Msps, 3.3V ADC

16 ______________________________________________________________________________________

MAX12554

CLKP

CLKN

GND

10kΩ

DUTY-CYCLE

EQUALIZER

SWITCHES S

AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S

ARE OPEN IN

SINGLE-ENDED CLOCK MODE.

Figure 5. Simplified Clock Input Circuit

System-Timing Requirements

Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.0 clock cycles later.

The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN).

Data-Valid Output (DAV)

DAV is a single-ended version of the input clock (CLKP) with a delay (t

DAV

). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6).

The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is a single-ended version of CLKP delayed by 5.2ns (t

DAV

With the duty-cycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D13–D0 and DOR are valid from 5.5ns before the rising edge of DAV to 5.5ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a

5.2ns (t

DAV

) delay from the falling edge of CLKP.

DAV is high impedance when the MAX12554 is in power-down (PD = high). DAV is capable of sinking and sourcing 600µA and has three times the drive strength of D13–D0 and DOR. DAV is typically used to latch the MAX12554 output data into an external backend digital circuit.

Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX12554 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX12555 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer.

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 17

DAV

N + 1

N +2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

DAV

SETUP

N - 1

N - 2

N - 3

HOLD

DIFFERENTIAL ANALOG INPUT (INP–INN)

CLKN

CLKP

REFP

- V

REFN

) x 2/3

REFN

- V

REFP

) x 2/3

N + 4

D0–D11

DOR

8.0 CLOCK-CYCLE DATA LATENCY

SETUP

HOLD

NN + 1 N + 2 N + 3 N + 5 N + 6 N + 7N - 1N - 2N - 3 N + 9N + 8

Figure 6. System Timing Diagram

MAX12554

Data Out-of-Range Indicator (DOR)

The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (V

REFP

- V

REFN

) x 3/4 to (V

REFN

- V

REFP

) x 3/4. Signals outside this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6.

DOR is synchronized with DAV and transitions along with the output data D13–D0. There is an 8.0 clockcycle latency in the DOR function as is with the output data (Figure 6).

DOR is high impedance when the MAX12554 is in power-down (PD = high). DOR enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD’s falling edge.

Digital Output Data (D13–D0), Output Format (G/T)

The MAX12554 provides a 14-bit, parallel, tri-state output bus. D13–D0 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV.

The MAX12554 output data format is either Gray code or two’s complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two’s complement. See Figure 9 for a binary-to-Gray and Gray-tobinary code-conversion example.

The following equations, Table 2, Figure 7, and Figure 8 define the relationship between the digital output and the analog input:

for Gray code (G/T = 1).

for two’s complement (G/T = 0).

where CODE

is the decimal equivalent of the digital

output code as shown in Table 2.

Digital outputs D13–D0 are high impedance when the MAX12554 is in power-down (PD = high). D13–D0 transition high 10ns after the rising edge of PD and become active 10ns after PD’s falling edge.

Keep the capacitive load on the MAX12554 digital outputs D13–D0 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12554 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the MAX12554 from heavy capacitive loading. To improve the dynamic performance of the MAX12554, add 220Ω resistors in series with the digital outputs close to the MAX12554. Refer to the MAX12555 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220Ω series resistors.

Power-Down Input (PD)

The MAX12554 has two power modes that are controlled with the power-down digital input (PD). With PD low, the MAX12554 is in normal operating mode. With PD high, the MAX12554 is in power-down mode.

The power-down mode allows the MAX12554 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX12554 parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed.

VV V V

CODE

INP INN REFP REFN

−−=××()

4 3 16384

VV V V

CODE

INP INN REFP REFN

−−

−

=×× ()

8192

16384

14-Bit, 80Msps, 3.3V ADC

18 ______________________________________________________________________________________

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 19

GRAY-CODE

OUTPUT CODE

(G/T = 1)

TWO’S-COMPLEMENT

OUTPUT CODE

(G/T = 0)

BINARY

D13 ➝ D0

EQUIVALENT

D13 ➝ D0

DECIMAL

EQUIVALENT

D13 ➝ D0

(CODE

)

BINARY

D13 ➝ D0

EQUIVALENT

D13➝ D0

DECIMAL

EQUIVALENT

D13 ➝ D0

(CODE

)

INP

- V

INN

REFP

= 2.418V

REFN

= 0.882V

10 0000 0000 0000

1 0x2000 +16383

1 0x1FFF +8191

>+1.023875V

(DATA OUT OF

RANGE)

10 0000 0000 0000

0 0x2000 +16383

0 0x1FFF +8191 +1.023875V

10 0000 0000 0001

0 0x2001 +16382

0 0x1FFE +8190 +1.023750V

11 0000 0000 0011

0 0x3003 +8194

0 0x0002 +2 +0.000250V

11 0000 0000 0001

0 0x3001 +8193

0 0x0001 +1 +0.000125V

11 0000 0000 0000

0 0x3000 +8192

0 0x0000 0 +0.000000V

01 0000 0000 0000

0 0x1000 +8191

0 0x3FFF -1 -0.000125V

01 0000 0000 0001

0 0x1001 +8190

0 0x3FFE -2 -0.000250V

00 0000 0000 0001

0 0x0001 +1

0 0x2001 -8191 -1.023875V

00 0000 0000 0000

0 0x0000 0

0 0x2000 -8192 -1.024000V

00 0000 0000 0000

1 0x0000 0

1 0x2000 -8192

<-1.024000V

(DATA OUT OF

RANGE)

)

Table 2. Output Codes vs. Input Voltage

(

HEXADECIMAL

DOR

HEXADECIMAL

DOR

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0010

00 0000 0000 0000

11 1111 1111 1111

00 0000 0000 0001

11 1111 1111 1110

10 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

MAX12554

14-Bit, 80Msps, 3.3V ADC

20 ______________________________________________________________________________________

In power-down mode, all internal circuits are off, the analog supply current reduces to 0.1mA, and the digital supply current reduces to 0.008mA. The following list shows the state of the analog inputs and digital outputs in power-down mode:

• INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3).

• REFOUT has approximately 17kΩ to GND.

• REFP, COM, REFN go high impedance with respect to V

and GND, but there is an internal 4kΩ resistor

between REFP and COM, as well as an internal 4kΩ resistor between REFN and COM.

• D13–D0, DOR, and DAV go high impedance.

• CLKP, CLKN go high impedance (Figure 5).

The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 10ms with the recommended capacitor array (Figure 13). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers.

Applications Information

Using Transformer Coupling

In general, the MAX12554 provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to singleended input mode.

An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12554 for optimum performance. Connecting the center tap of the transformer to COM provides a V

/ 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 10 is good for frequencies up to Nyquist (f

CLK

/ 2).

The circuit of Figure 11 converts a single-ended input signal to fully differential just as Figure 10. However, Figure 11 utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency

DIFFERENTIAL INPUT VOLTAGE (LSB)

TWO'S-COMPLEMENT OUTPUT CODE (LSB)

-8189 +8191+8189-1 0 +1-8191

0x2000

0x2001

0x2002

0x2003

0x1FFF 0x1FFE

0x1FFD

0x3FFF

0x0000

0x0001

REFP

- V

REFN

) x 2/3 (V

REFP

- V

REFN

) x 2/3

1 LSB =

REFP

- V

REFN

16384

4 3

Figure 7. Two’s-Complement Transfer Function (G/T= 0)

DIFFERENTIAL INPUT VOLTAGE (LSB)

GRAY OUTPUT CODE (LSB)

+1 +8191+8189-1

-8191 -8189

0x0000

0x0001

0x0003

0x0002

0x2000 0x2001 0x2003

0x1000

0x3000

0x3001

REFP

- V

REFN

) x 2/3 (V

REFP

- V

REFN

) x 2/3

1 LSB =

REFP

- V

REFN

16384

4 3

Figure 8. Gray-Code Transfer Function (G/T= 1)

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 21

BINARY-TO-GRAY-CODE CONVERSION

1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT.

2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

BINARY

GRAY CODE

BIT POSITION

3) REPEAT STEP 2 UNTIL COMPLETE.

BINARY

GRAY CODE

BIT POSITION

4) THE FINAL GRAY-CODE CONVERSION IS:

BINARY

BIT POSITION

GRAY-TO-BINARY-CODE CONVERSION

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION.

011 10100 1100

D11 D7 D3 D0

D13

01 1 1 0100 1100

D11 D7 D3 D0

1100

D13

01 1 1 0100 1100

D11 D7 D3 D0

D13

1011 0100 1100 BINARY

GRAY CODE0

D11 D7 D3 D0

BIT POSITION

D13

GRAY CODE0 101101110 1010

GRAYX = BINARYX BINARY

X+1

GRAY12 = BINARY12 BINARY

GRAY12 = 1 0

GRAY

= 1

GRAY11 = BINARY11 BINARY

GRAY11 = 1 1

GRAY

= 0

1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT.

2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

GRAY CODE

BINARY

BIT POSITION

3) REPEAT STEP 2 UNTIL COMPLETE.

GRAY CODE

BINARY

BIT POSITION

4) THE FINAL GRAY-CODE CONVERSION IS:

GRAY CODE

BIT POSITION

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION.

001110 1010

D11 D7 D3 D0

D13

01 0 1110 1010

D11 D7 D3 D0

D13

01 0 0 1110 1010

D11 D7 D3 D0

D13

0110 1110 1010 GRAY CODE

BINARY0

D11 D7 D3 D0

BIT POSITION

D13

BINARY0 111010100 1100

BINARYX = BINARY

X+1

GRAY

BINARY12 = BINARY13 GRAY

BINARY12 = 0 1

BINARY

= 1

BINARY11 = BINARY12 GRAY

BINARY11 = 1 0

BINARY

= 1

AB 00 01 10 11

0 1 1 0

EXCULSIVE OR TRUTH TABLE

Y = A B

Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion

MAX12554

14-Bit, 80Msps, 3.3V ADC

22 ______________________________________________________________________________________

signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent 50Ω termi- nation to the signal source. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input frequencies. These 0Ω resistors can be replaced with low-value resistors to limit the input bandwidth.

Single-Ended, AC-Coupled Input Signal

Figure 12 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.

MAX12554

N.C.

0.1µF

MINI-CIRCUITS TT1-6 OR T1-1T

24.9Ω

12pF

2.2µF

INP

COM

INN

Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist

MAX12554

N.C. N.C.

MINI-CIRCUITS

ADT1-1WT

N.C.

0.1µF

MINI-CIRCUITS

ADT1-1WT

0Ω*

5.6pF

2.2µF

INP

COM

INN

110Ω

0.1%

110Ω

0.1%

75Ω

0.5%

75Ω

0.5%

*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE BANDWIDTH.

Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist

MAX12554

5.6pF

2.2µF

INP

COM

INN

24.9Ω

100Ω

0.1µF

MAX4108

Figure 12. Single-Ended, AC-Coupled Input Drive

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 23

Buffered External Reference

Drives Multiple ADCs

The buffered external reference mode allows for more control over the MAX12554 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ.

Figure 13 uses the MAX6029EUK21 precision 2.048V reference as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a one-pole 10Hz lowpass filter to the MAX4230. The MAX4230 buffers the 2.048V reference and provides additional 10Hz lowpass filtering before its output is applied to the REFIN input of the MAX12554.

MAX12554

NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT.

*PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.

16.2kΩ

0.1µF

1µF

2.048V

+3.3V

47Ω

1.47kΩ

+3.3V

10µF 6V

330µF 6V

+3.3V

2.2µF

0.1µF

1µF* 10µF

0.1µF

REFP

REFN

COM

GND

REFIN

REFOUT

MAX12554

+3.3V

2.2µF

0.1µF

1µF* 10µF

0.1µF

REFP

REFN

COM

GND

REFIN

REFOUT

MAX6029EUK21

MAX4230

Figure 13. External Buffered Reference Driving Multiple ADCs

MAX12554

14-Bit, 80Msps, 3.3V ADC

24 ______________________________________________________________________________________

Unbuffered External

Reference Drives Multiple ADCs

The unbuffered external reference mode allows for precise control over the MAX12554 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources.

Figure 14 uses the MAX6029EUK30 precision 3.000V reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47µF capacitor along this chain creates a 10Hz lowpass filter. Three MAX4230 operational amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12554’s REFP, COM, REFN reference inputs,

MAX12554

*PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.

0.1µF

2.413V

+3.3V

47Ω

1.47kΩ

+3.3V

10µF 6V

330µF 6V

+3.3V

2.2µF

0.1µF

1µF*

10µF

0.1µF

REFOUT

REFN

REFIN

GND

COM

REFP

MAX6029EUK30

MAX4230

0.1µF

0.47µF

1.647V

47Ω

1.47kΩ

+3.3V

10µF 6V

330µF 6V

MAX4230

0.1µF

0.880V

47Ω

1.47kΩ

+3.3V

10µF 6V

330µF 6V

MAX4230

MAX12554

+3.3V

2.2µF

0.1µF

1µF*10µF

0.1µF

REFOUT

REFN

REFIN

GND

COM

REFP

3.000V

20kΩ 1%

52.3kΩ 1%

20kΩ 1%

0.1µF

2.2µF

Figure 14. External Unbuffered Reference Driving Multiple ADCs

MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 25

respectively. The feedback around the MAX4230 op amps provides additional 10Hz lowpass filtering. The

2.413V and 0.880V reference voltages set the full-scale analog input range to ±1.022V = ±(VREFP - VREFN) x 2/3. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down.

Grounding, Bypassing, and

Board Layout

The MAX12554 requires high-speed board layout design techniques. Refer to the MAX12555 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass VDDto GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass OV

to GND with a 0.1µF ceramic capacitor in parallel with a

2.2µF ceramic capacitor.

Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX12554 GNDs and the exposed back-side paddle must be connected to the same ground plane. The MAX12554 relies on the exposed back-side paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground.

Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns.

Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX12555 evaluation kit data sheet for an example of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX12554, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no

missing codes and a monotonic transfer function. For the MAX12554, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX12554 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX12554 transition occurs at 1.5 LSBs below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.

Small-Signal Noise Floor (SSNF)

Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to www.maxim-ic.com for application notes on thermal + quantization noise floor.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):

SNR

[max]

= 6.02 x N + 1.76

In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the

MAX12554

14-Bit, 80Msps, 3.3V ADC

26 ______________________________________________________________________________________

fundamental, the first six harmonics (HD2–HD7), and the DC offset:

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. RMS distortion includes the first six harmonics (HD2–HD7):

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from:

Single-Tone Spurious-Free Dynamic

Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V7are the amplitudes of the 2nd- through 7th-order harmonics (HD2–HD7).

Intermodulation Distortion (IMD)

IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as:

The fundamental input tone amplitudes (V1and V2) are at -7dBFS. Fourteen intermodulation products (VIM_) are used in the MAX12554 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where f

IN1

and

IN2

are the fundamental input tone frequencies:

• Second-order intermodulation products: f

IN1

+ f

IN2

, f

IN2

- f

IN1

• Third-order intermodulation products: 2 x f

IN1

- f

IN2

, 2 x f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

• Fourth-order intermodulation products: 3 x f

IN1

- f

IN2

, 3 x f

IN2

- f

IN1

, 3 x f

IN1

+ f

IN2

, 3 x f

IN2

+ f

IN1

•Fifth-order intermodulation products: 3 x f

IN1

- 2 x f

IN2

, 3 x f

IN2

- 2 x f

IN1

, 3 x f

IN1

+ 2 x

IN2

, 3 x f

IN2

+ 2 x f

IN1

Third-Order Intermodulation (IM3)

IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f

IN1

and f

IN2

. The individual input tone levels are at -7dBFS. The thirdorder intermodulation products are 2 x f

IN1

- f

IN2

, 2 x

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

Two-Tone Spurious-Free Dynamic Range

(SFDR

)

SFDRTTrepresents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic.

Aperture Delay

The MAX12554 samples data on the falling edge of its sampling clock. In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (t

) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 4).

VV V V

IM IM IM IM

log

.......

=×

+++ +





 





 

THD

VVVVVV

log

=×

+++++





  







  



ENOB

SINAD

 



 



− 176

602

SIGNAL

NOISE DISTORTION

RMS

RMS RMS

log

=×





 





 

SNR

SIGNAL

NOISE

RMS

log

=×

 



 



MAX12554

14-Bit, 80Msps, 3.3V ADC

______________________________________________________________________________________ 27

Aperture Jitter

Figure 4 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Output Noise (n

OUT

)

The output noise (n

OUT

) parameter is similar to the thermal + quantization noise parameter and is an indication of the ADC’s overall noise performance.

No fundamental input tone is used to test for n

OUT

; INP, INN, and COM are connected together and 1024k data points collected. n

OUT

is computed by taking the RMS value of the collected data points after the mean is removed.

Overdrive Recovery Time

Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX12554 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ±10%.

REFP 1

REFN 2

COM 3

GND 4

INP 5

INN 6

GND 7

DCE 8

CLKN 9

CLKP 10

D230

D329

D428

D527

D626

D725

D824

D923

D1022

D1121

REFIN39REFOUT38PD37V

GND35OV

DAV33D032D1

CLKTYP

GND

DOR

D1319D12

G/T

TOP VIEW

MAX12554

EXPOSED PADDLE (GND)

THIN QFN

6mm x 6mm x 0.8mm

Pin Configuration

MAX12554

14-Bit, 80Msps, 3.3V ADC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

QFN THIN 6x6x0.8.EPS

e e

A1 A2

E/2

D/2

E2/2

(NE-1) X e

(ND-1) X e

D2/2

C L

21-0141

PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

3. N IS THE TOTAL NUMBER OF TERMINALS.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

21-0141

PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm

MAXIM MAX12554 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual