MAXIM MAX12553 User Manual

General Description

The MAX12553 is a 3.3V, 14-bit, 65Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noise
internal quantizer. The analog input stage accepts single­ended or differential signals. The MAX12553 is optimized
for low-power, small size, and high dynamic perfor­mance. Excellent dynamic performance is maintained
from baseband to input frequencies of 175MHz and
beyond, making the MAX12553 ideal for intermediate­frequency (IF) sampling applications.

Powered from a single 3.15V to 3.60V supply, the
MAX12553 consumes only 363mW while delivering a
typical signal-to-noise (SNR) performance of 71dB at
an input frequency of 175MHz. In addition to low oper­ating power, the MAX12553 features a 150µW power­down mode to conserve power during idle periods.

A flexible reference structure allows the MAX12553 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.10V. The MAX12553 provides a com­mon-mode reference to simplify design and reduce exter­nal component count in differential analog input circuits.

The MAX12553 supports both a single-ended and dif­ferential input clock drive. Wide variations in the clock
duty cycle are compensated with the ADC’s internal
duty-cycle equalizer (DCE).

ADC conversion results are available through a 14-bit,
parallel, CMOS-compatible output bus. The digital out­put format is pin selectable to be either two’s comple­ment or Gray code. A data-valid indicator eliminates
external components that are normally required for reli­able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing the
MAX12553 to interface with various logic levels.

The MAX12553 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.

See the Pin-Compatible Versions table for a complete

family of 14-bit and 12-bit high-speed ADCs.

Applications

IF and Baseband Communication Receivers

Cellular, Point-to-Point Microwave, HFC, WLAN
Ultrasound and Medical Imaging
Portable Instrumentation
Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance

74.0dB/71dB SNR at fIN= 3MHz/175MHz

90.6dBc/80.7dBc SFDR at fIN= 3MHz/175MHz

♦ Low Noise Floor: -76dBFS
♦ 3.3V Low-Power Operation

337mW (Single-Ended Clock Mode)
363mW (Differential Clock Mode)
150µW (Power-Down Mode)

♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Full-Scale Analog Input Range: ±0.35V

to ±1.10V

♦ Common-Mode Reference
♦ CMOS-Compatible Outputs in Two’s Complement

or Gray Code

♦ Data-Valid Indicator Simplifies Digital Interface
♦ Data Out-of-Range Indicator
♦ Miniature, 40-Pin Thin QFN Package with Exposed

Paddle

♦ Evaluation Kit Available (Order MAX12555EVKIT)

MAX12553

14-Bit, 65Msps, 3.3V ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3343; Rev 0; 8/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin-Compatible Versions

Pin Configuration appears at end of data sheet.

PART

MAX12553ETL

PART

MAX12553 65 14 IF/Baseband
MAX1209 80 12 IF
MAX1211 65 12 IF
MAX1208 80 12 Baseband
MAX1207 65 12 Baseband
MAX1206 40 12 Baseband

TEMP

RANGE

-40°C to
+85°C

SAMPLING

RATE (Msps)

PIN-PACKAGE

40 Thin QFN
(6mm x 6mm x 0.8mm)

RESOLUTION

(BITS)

APPLICATION

PKG

CODE

T4066-3

TARGET

MAX12553

14-Bit, 65Msps, 3.3V ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND...........................................................-0.3V to +3.6V

OV

DD

to GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V

INP, INN to GND ...-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

REFIN, REFOUT, REFP, REFN, COM

to GND................-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

CLKP, CLKN, CLKTYP, G/T, DCE,

PD to GND ........-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

D13–D0, DAV, DOR to GND....................-0.3V to (OV

DD

+ 0.3V)

Continuous Power Dissipation (TA= +70°C)

40-Pin Thin QFN 6mm x 6mm x 0.8mm

(derated 26.3mW/°C above +70°C)........................2105.3mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering 10s) ..................................+300°C

DC ACCURACY (Note 2)

Resolution 14 Bits
Integral Nonlinearity INL fIN = 3MHz (Note 5) ±1.4 ±4.2 LSB

Differential Nonlinearity DNL

Offset Error V
Gain Error V

ANALOG INPUT (INP, INN)

Differential Input Voltage Range V
Common-Mode Input Voltage VDD/2 V

Input Capacitance
(Figure 3)

CONVERSION RATE

Maximum Clock Frequency f
Minimum Clock Frequency 5 MHz

Data Latency Figure 6 8.5

DYNAMIC CHARACTERISTICS (differential inputs, Note 2)
Small-Signal Noise Floor SSNF Input at less than -35dBFS -76.0 dBFS

Signal-to-Noise Ratio SNR

Signal-to-Noise and Distortion SINAD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

f

= 3MHz, no missing codes over

IN

temperature (Note 3)

= 2.048V ±0.1 ±0.55 %FS

REFIN

= 2.048V ±0.5 ±4.9 %FS

REFIN

DIFF

C

PAR

C

SAMPLE

CLK

Differential or single-ended inputs ±1.024 V

Fixed capacitance to ground 2
Switched capacitance 4.5

fIN = 3MHz at -0.5dBFS (Note 8) 69.3 74.0
fIN = 32.5MHz at -0.5dBFS 73.9
fIN = 70MHz at -0.5dBFS 73.4
f

= 175MHz at -0.5dBFS (Notes 7, 8) 68.0 71.0

IN

fIN = 3MHz at -0.5dBFS (Note 8) 69.2 73.9
fIN = 32.5MHz at -0.5dBFS 73.1
fIN = 70MHz at -0.5dBFS 73.1
f

= 175MHz at -0.5dBFS (Notes 7, 8) 67.6 70.0

IN

±0.5 ±1.0 LSB

65 MHz

pF

Clock

cycles

dB

dB

MAX12553

14-Bit, 65Msps, 3.3V ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Second Harmonic HD2

Third Harmonic HD3

Intermodulation Distortion IMD

Third-Order Intermodulation IM3

Two-Tone Spurious-Free
Dynamic Range

Aperture Delay t
Aperture Jitter t
Output Noise n

Overdrive Recovery Time ±10% beyond full scale 1

fIN = 3MHz at -0.5dBFS 79.8 90.6
fIN = 32.5MHz at -0.5dBFS 84.0
fIN = 70MHz at -0.5dBFS 87.8

= 175MHz at -0.5dBFS (Note 7) 75.9 80.7

f

IN

fIN = 3MHz at -0.5dBFS -90.6 -80.2
fIN = 32.5MHz at -0.5dBFS -81.0
fIN = 70MHz at -0.5dBFS -85.4
f

= 175MHz at -0.5dBFS -78.9 -71.3

IN

fIN = 3MHz at -0.5dBFS -99
fIN = 32.5MHz at -0.5dBFS -91
fIN = 70MHz at -0.5dBFS -92
f

= 175MHz at -0.5dBFS -81

IN

fIN = 3MHz at -0.5dBFS -94
fIN = 32.5MHz at -0.5dBFS -84
fIN = 70MHz at -0.5dBFS -88
f

= 175MHz at -0.5dBFS -86

IN

f

= 68.5MHz at -7dBFS

IN1

f

= 71.5MHz at -7dBFS

IN2

f

= 172.5MHz at -7dBFS

IN1

f

= 177.5MHz at -7dBFS

IN2

f

= 68.5MHz at -7dBFS

IN1

f

= 71.5MHz at -7dBFS

IN2

f

= 172.5MHz at -7dBFS

IN1

f

= 177.5MHz at -7dBFS

IN2

f

= 68.5MHz at -7dBFS

IN1

f

= 71.5MHz at -7dBFS

SFDR

AD

AJ

OUT

IN2

TT

f

= 172.5MHz at -7dBFS

IN1

f

= 177.5MHz at -7dBFS

IN2

Figure 4 1.2 ns
Figure 4 <0.2 ps
INP = INN = COM 0.95 LSB

dBc

dBc

dBc

dBc

-87
dBc

-80

-91
dBc

-83

90

dBc

81

RMS

RMS

Clock

cycles

MAX12553

14-Bit, 65Msps, 3.3V ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INTERNAL REFERENCE (REFIN = REFOUT; V

REFOUT Output Voltage V
COM Output Voltage V

Differential Reference Output
Voltage

REFOUT Load Regulation 35 mV/mA
REFOUT Temperature Coefficient TC

REFOUT Short-Circuit Current

B U F F ER ED EXT ER N A L R EF ER EN C E ( R EF IN d r iv e n e x t e r n a lly ; V
REFIN Input Voltage V
REFP Output Voltage V
REFN Output Voltage V
COM Output Voltage V

Differential Reference Output
Voltage

Differential Reference
Temperature Coefficient

REFIN Input Resistance >50 MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V
COM Input Voltage V
REFP Input Voltage V
REFN Input Voltage V

Differential Reference Input
Voltage

REFP Sink Current I
REFN Source Current I
COM Sink Current I
REFP, REFN Capacitance 13 pF
COM Capacitance 6pF

CLOCK INPUTS (CLKP, CLKN)

Single-Ended Input High
Threshold

Single-Ended Input Low
Threshold

Differential Input Voltage Swing CLKTYP = high 1.4 V
Differential Input Common-Mode

Voltage

, V

REFOUT

COM

V

REF

REF

REFIN

REFP
REFN

COM

V

REF

REFN

, and V

REFP

VDD/2 1.65 V

V

REF

= V

REFP

- V

Short to VDD—sinking 0.24
Short to GND—sourcing 2.1

R EF IN

(VDD/2) + (V
(VDD/2) - (V

REFIN

REFIN

VDD/2 1.60 1.65 1.70 V

V

REF

= V

REFP

- V

are generated internally)

COM

2.002 2.048 2.066 V

REFN

= V

x 3/4 1.536 V

REFIN

+50 ppm/°C

mA

= 2.0 4 8 V, V

R EF P

, V

R EF N

, a n d V

a r e g e n e r a t e d in t e r n a lly )

C OM

2.048 V

x 3/8) 2.418 V

x 3/8) 0.882 V

REFN

= V

x 3/4 1.463 1.536 1.601 V

REFIN

±25 ppm/°C

, V

COM

V

REF

REFP
REFN
COM

V

V

REFN

, and V

REFP

VDD/2 1.65 V

- V

REFP

COM

- V

REFN

V

REF

V

REFP

V

REFN

CLKTYP = GND, CLKN = GND

IH

CLKTYP = GND, CLKN = GND

IL

COM

= V

REFP

- V

REFN

= V

REFIN

= 2.418V 1 mA

= 0.882V 0.7 mA

CLKTYP = high V

are applied externally)

COM

0.768 V

-0.768 V

x 3/4 1.536 V

0.7 mA

0.8 x
V

DD

0.2 x
V

DD

/ 2 V

DD

V

V

P-P

MAX12553

14-Bit, 65Msps, 3.3V ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Resistance R
Input Capacitance C

DIGITAL INPUTS (CLKTYP, G/T, PD)

Input High Threshold V

Input Low Threshold V

Input Leakage Current

Input Capacitance C

DIGITAL OUTPUTS (D13–D0, DAV, DOR)

Output Voltage Low V

Output Voltage High V

Tri-State Leakage Current I
D13–D0, DOR Tri-State Output

Capacitance
DAV Tri-State Output

Capacitance

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Output Supply Voltage OV

Analog Supply Current I

CLK
CLK

DIN

OH

LEAK

C

OUT

C

DAV

OL

DD

Figure 5 5 kΩ

IH

IL

VIH = OV
V

D13–D0, DOR, I
DAV, I

D13–D0, DOR, I

DAV, I

DD

= 0 ±5

IL

SINK

= 600µA 0.2

SINK

SOURCE

= 600µA

SOURCE

(Note 4) ±5 µA

(Note 4) 3 pF

(Note 4) 6 pF

DD

Normal operating mode,
f

= 175MHz at -0.5dBFS, CLKTYP = GND,

IN

single-ended clock

VDD

Normal operating mode,

= 175MHz at -0.5dBFS,

f

IN

CLKTYP = OV

differential clock

DD,

Power-down mode clock idle, PD = OV

2pF

0.8 x

OV

DD

0.2 x

OV

±5

5pF

= 200µA 0.2

OV

-

= 200µA

0.2
OV

DD

DD

-

0.2

3.15 3.3 3.60 V
V

1.7 2.0

DD

0.3V

102

110 123

DD

0.045

DD

+

V

V

µA

V

V

V

mA

MAX12553

14-Bit, 65Msps, 3.3V ADC

6 _______________________________________________________________________________________

Note 1: Specifications ≥+25°C guaranteed by production test; <+25°C guaranteed by design and characterization.
Note 2: See definitions in the Parameter Definitions section at the end of this data sheet.
Note 3: Specifications guaranteed by design and characterization. Devices tested for performance during production test.
Note 4: During power-down, D13–D0, DOR, and DAV are high impedance.
Note 5: Guaranteed by design and characterization.
Note 6: Digital outputs settle to V

IH

or VIL.

Note 7: Due to test-equipment-jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from

the spectral analysis.

Note 8: Limit specifications include performance degradations due to a production test socket. Performance is improved when the

MAX12553 is soldered directly to the PC board.

ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

= 65MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

Analog Power Dissipation P

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Digital Output Supply Current I

TIMING CHARACTERISTICS (Figure 6)

Clock Pulse-Width High t
Clock Pulse-Width Low t
Data-Valid Delay t

Data Setup Time Before Rising
Edge of DAV

Data Hold Time After Rising Edge
of DAV

Wake-Up Time from Power-Down t

Normal operating mode,
f

= 175MHz at -0.5dBFS, CLKTYP = GND,

IN

single-ended clock

DISS

OVDD

CH

CL

DAV

t

SETUP

t

HOLD

WAKE

Normal operating mode,

= 175MHz at -0.5dBFS,

f

IN

CLKTYP = OV
Power-down mode clock idle, PD = OV
Normal operating mode,

f

= 175MHz at -0.5dBFS, OVDD = 2.0V,

IN

≈ 5pF

C

L

Power-down mode clock idle, PD = OV

CL = 5pF (Note 6) 6.9 ns

CL = 5pF (Notes 5, 6) 8.5 ns

CL = 5pF (Notes 5, 6) 6.3 ns

V

= 2.048V 10 ms

REFIN

, differential clock

DD

337

363 406

DD

DD

0.15

8.2 mA

20 µA

7.7 ns

7.7 ns

mW

MAX12553

14-Bit, 65Msps, 3.3V ADC

_______________________________________________________________________________________ 7

Typical Operating Characteristics

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

f

= 65MHz

CLK

= 3.00720215MHz

f

IN

= -0.542dBFS

A

IN

SNR = 74.223dB
SINAD = 74.147dB
THD = -91.794dBc
SFDR = 91.499dBc

MAX12553 toc01

-60

-70

AMPLITUDE (dBFS)

-80

HD2

HD3

-90

-100

-110

-120
032

24 2881216204

FREQUENCY (MHz)

0

f

CLK

-10

f

IN

-20

A

IN

SNR = 74.206dB

-30

SINAD = 73.534dB

-40

THD = -81.965dBc

-50

SFDR = 86.015dBc

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

0

f

= 65MHz

CLK

-10

= 174.9017334MHz

f

IN

-20

= -0.499dBFS

A

IN

SNR = 70.971dB

-30

SINAD = 70.260dB

-40

THD = -78.475dBc

-50

SFDR = 80.267dBc

-60

-70

AMPLITUDE (dBFS)

-80

HD2

MAX12553 toc04

HD5

-90

-100

-110

-120
032

24 2881216204

FREQUENCY (MHz)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

= 65MHz

= 32.39685059MHz

= -0.469dBFS

HD2

FREQUENCY (MHz)

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

f

= 64.96256MHz

CLK

= 250.00911MHz

f

IN

= -0.494dBFS

A

IN

SNR = 69.39dB
SINAD = 68.67dB
THD = -76.8dBc
SFDR = 78.6dBc

HD3

HD2

FREQUENCY (MHz)

SINGLE-TONE FFT PLOT

(8192-POINT DATA RECORD)

0

-10

-20

MAX12553 toc02

-30

-40

-50

-60

-70

HD3

AMPLITUDE (dBFS)

-80

-90

-100

-110

24 2881216204

-120
032

f

= 65MHz

CLK

= 69.89562988MHz

f

IN

= -0.460dBFS

A

IN

SNR = 73.772dB
SINAD = 73.615dB
THD = -88.110dBc
SFDR = 88.325dBc

HD3

HD2

FREQUENCY (MHz)

24 2881216204

TWO-TONE FFT PLOT

(16,384-POINT DATA RECORD)

0

-10

-20

MAX12553 toc05

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

2 x f

-90

-100

-110

-120

24 2881216204

032

f

= 65MHz

CLK

= 68.50311279MHz

f

IN1

f

IN1

IN2

A

f

IN2

f
A
SFDR
IMD = -87.812dBc
IM3 = -91.844dBc

- f

IN1

= -7.018dBFS

IN1

= 71.50238037MHz

IN2

= -7.087dBFS

IN2

FREQUENCY (MHz)

= 90.085dBc

TT

24 2881216204

MAX12553 toc03

MAX12553 toc06

TWO-TONE FFT PLOT

(16,384-POINT DATA RECORD)

MAX12553 toc07

2.0

1.5

1.0

0.5

0

INL (LSB)

-0.5

-1.0

-1.5

-2.0

0

f

= 65.00352MHz

CLK

-10

= 172.4870625MHz

f

IN1

-20

= -7.047dBFS

A

IN1

= 177.4861125MHz

f

IN2

-30

= -6.984dBFS

A

IN2

-40

SFDR

-50

-60

-70

AMPLITUDE (dBFS)

-80

TT

IMD = -80.035dBc
IM3 = -83.511dBc

- f

IN2

IN1

= 81.484dBc

2 x f

IN2

- f

IN1f

f

IN2

f

IN1

f

+ f

IN1

IN2

-90

-100

-110

-120
032

24 2881216204

FREQUENCY (MHz)

INTEGRAL NONLINEARITY

0 16384

DIGITAL OUTPUT CODE

DIFFERENTIAL NONLINEARITY

1.0

0.8

MAX12553 toc08

0.6

0.4

0.2
0

DNL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0

1228881924096

0 16384

1228881924096

DIGITAL OUTPUT CODE

MAX12553 toc09

MAX12553

14-Bit, 65Msps, 3.3V ADC

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

75

fIN ≈ 70MHz

74
73
72
71
70
69

SNR, SINAD (dB)

68
67
66
65

080

75

fIN ≈ 175MHz

74
73
72
71
70
69

SNR, SINAD (dB)

68
67
66
65

080

SNR, SINAD

vs. SAMPLING RATE

100

fIN ≈ 70MHz

95

MAX12553 toc10

90

85

80

75

SFDR, -THD (dB)

70

SNR
SINAD

604020

f

(MHz)

CLK

65

60

080

SNR, SINAD

vs. SAMPLING RATE

100

fIN ≈ 175MHz

MAX12553 toc13

SNR
SINAD

604020

f

(MHz)

CLK

95

90

85

80

75

SFDR, -THD (dB)

70

65

60

080

SFDR, -THD

vs. SAMPLING RATE

f

(MHz)

CLK

SFDR, -THD

vs. SAMPLING RATE

f

(MHz)

CLK

POWER DISSIPATION

vs. SAMPLING RATE

500

DIFFERENTIAL CLOCK

≈ 70MHz

f

IN

450

≈ 5pF

C

MAX12553 toc11

SFDR

-THD

604020

L

400

350

300

POWER DISSIPATION (mW)

250

200

080

ANALOG + DIGITAL POWER
ANALOG POWER

604020

f

(MHz)

CLK

POWER DISSIPATION

vs. SAMPLING RATE

500

DIFFERENTIAL CLOCK

≈ 175MHz

f

IN

450

≈ 5pF

C

MAX12553 toc14

SFDR

-THD

604020

L

400

350

300

POWER DISSIPATION (mW)

250

200

080

ANALOG + DIGITAL POWER
ANALOG POWER

604020

f

(MHz)

CLK

MAX12553 toc12

MAX12553 toc15

vs. ANALOG INPUT FREQUENCY

SNR, SINAD

75
73
71
69
67
65
63

SNR, SINAD (dB)

61
59
57
55

SNR
SINAD

0 400

ANALOG INPUT FREQUENCY (MHz)

f

CLK

300200100

≈ 65MHz

MAX12553 toc16

vs. ANALOG INPUT FREQUENCY

95

90

85

80

75

70

SFDR, -THD (dBc)

65

60

55

0 400

SFDR, -THD

f

≈ 65MHz

CLK

SFDR

-THD

300200100

ANALOG INPUT FREQUENCY (MHz)

500

450

MAX12553 toc17

400

350

300

POWER DISSIPATION (mW)

250

200

0 400

POWER DISSIPATION

vs. ANALOG INPUT FREQUENCY

DIFFERENTIAL CLOCK

≈ 65MHz

f

CLK

≈ 5pF

C

L

ANALOG + DIGITAL POWER
ANALOG POWER

ANALOG INPUT FREQUENCY (MHz)

MAX12553 toc18

300200100

MAX12553

14-Bit, 65Msps, 3.3V ADC

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

SNR, SINAD

vs. ANALOG INPUT AMPLITUDE

75

f

= 64.96256MHz

CLK

70

= 175.0071MHz

f

IN

65
60
55
50
45

SNR, SINAD (dB)

40
35
30
25

-40 0
ANALOG INPUT AMPLITUDE (dBFS)

SNR, SINAD

vs. ANALOG SUPPLY VOLTAGE

75

f

= 64.96256MHz

CLK

74

= 175.00717MHz

f

IN

73
72
71
70
69

SNR, SINAD (dB)

68
67
66
65

2.6 3.6
VDD (V)

SNR, SINAD

vs. DIGITAL SUPPLY VOLTAGE

75
74
73
72
71
70
69

SNR, SINAD (dB)

68
67
66
65

SNR
SINAD

1.4 3.8

f
f

OVDD (V)

CLK
IN

SNR
SINAD

-5-10-20 -15-30 -25-35

SNR
SINAD

3.43.0 3.22.8

= 65MHz

= 174.9007416MHz

3.43.02.62.21.8

MAX12553 toc19

MAX12553 toc22

MAX12553 toc25

vs. ANALOG INPUT AMPLITUDE

SFDR, -THD

100

f

= 64.96256MHz

CLK

= 175.0071MHz

f

IN

90

80

70

60

SFDR, -THD (dBc)

50

40

30

-40 0
ANALOG INPUT AMPLITUDE (dBFS)

SFDR, -THD

vs. ANALOG SUPPLY VOLTAGE

100

f

= 64.96256MHz

CLK

= 175.00717MHz

f

95

IN

90

85

80

75

SFDR, -THD (dBc)

70

65

60

2.6 3.6

VDD (V)

SFDR, -THD

vs. DIGITAL SUPPLY VOLTAGE

100

95

90

85

80

75

SFDR, -THD (dBc)

70

65

60

SFDR

-THD

1.4 3.8

f

CLK

= 174.9007416MHz

f

IN

OVDD (V)

= 65MHz

500

450

MAX12553 toc20

400

350

300

POWER DISSIPATION (mW)

SFDR

-THD

-5-10-20 -15-30 -25-35

SFDR

-THD

3.43.0 3.22.8

3.43.02.62.21.8

250

200

-40 0

500

450

MAX12553 toc23

400

350

300

POWER DISSIPATION (mW)

250

200

2.6 3.6

500

450

MAX12553 toc26

400

350

300

POWER DISSIPATION (mW)

250

200

1.4 3.8

POWER DISSIPATION

vs. ANALOG INPUT AMPLITUDE

DIFFERENTIAL CLOCK

= 64.96256MHz

f

CLK

= 175.0071MHz

f

IN

≈ 5pF

C

L

ANALOG + DIGITAL POWER
ANALOG POWER

ANALOG INPUT AMPLITUDE (dBFS)

POWER DISSIPATION

vs. ANALOG SUPPLY VOLTAGE

DIFFERENTIAL CLOCK

= 64.96256MHz

f

CLK

= 175.00717MHz

f

IN

≈ 5pF

C

L

ANALOG + DIGITAL POWER
ANALOG POWER

VDD (V)

POWER DISSIPATION

vs. DIGITAL SUPPLY VOLTAGE

DIFFERENTIAL CLOCK
f

CLK

f

IN

C

L

ANALOG + DIGITAL POWER
ANALOG POWER

OVDD (V)

-5-10-20 -15-30 -25-35

3.43.0 3.22.8

= 65MHz

= 174.9007416MHz

≈ 5pF

3.43.02.62.21.8

MAX12553 toc21

MAX12553 toc24

MAX12553 toc27

MAX12553

14-Bit, 65Msps, 3.3V ADC

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

SNR, SINAD vs. TEMPERATURE

75

f

= 65MHz

CLK

74

= 175MHz

f

IN

73
72
71
70
69

SNR, SINAD (dB)

68
67
66
65

-40 85

SFDR, -THD vs. TEMPERATURE

90

f

= 65MHz

CLK

88

= 175MHz

f

IN

86
84
82
80
78

SFDR, -THD (dBc)

76
74
72
70

-40 85

TEMPERATURE (°C)

603510-15

SNR
SINAD

MAX12553 toc28

TEMPERATURE (°C)

ANALOG POWER DISSIPATION

vs. TEMPERATURE

500

DIFFERENTIAL CLOCK

= 65MHz

f

CLK

450

= 175MHz

f

MAX12553 toc29

SFDR

-THD

603510-15

IN

400

350

300

ANALOG POWER DISSIPATION (mW)

250

200

-40 85
TEMPERATURE (°C)

603510-15

MAX12553 toc30

OFFSET ERROR

vs. TEMPERATURE

0.3

0.2

0.1

0

-0.1

OFFSET ERROR (%FS)

-0.2

-0.3

-40 85
TEMPERATURE (°C)

V

REFIN

= 2.048V

603510-15

MAX12553 toc31

GAIN ERROR

vs. TEMPERATURE

3

2

1

0

GAIN ERROR (%FS)

-1

-2

-3

-40 85
TEMPERATURE (°C)

V

REFIN

= 2.048V

MAX12553 toc32

603510-15

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 11

Typical Operating Characteristics (continued)

(V

DD

= 3.3V, OV

DD

= 2.0V, GND = 0, REFIN = REFOUT (internal reference), V

IN

= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,

G/T = low, f

CLK

≈ 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

REFERENCE OUTPUT VOLTAGE

LOAD REGULATION

2.05

2.04

2.03

2.02

2.01

(V)

2.00

REFOUT

V

1.99

1.98

1.97

1.96

1.95

+85°C

-40°C

+25°C

-2.0 0.5
I

SINK CURRENT (mA)

REFOUT

3.0

2.5

2.0

1.5

VOLTAGE (V)

1.0

0.5

0

-2 2

MAX12553 toc33

0-0.5-1.0-1.5

REFP, COM, REFN
LOAD REGULATION

V

REFP

V

REFN

INTERNAL REFERENCE
MODE AND BUFFERED EXTERNAL
REFERENCE MODE

SINK CURRENT (mA)

REFERENCE OUTPUT VOLTAGE

SHORT-CIRCUIT PERFORMANCE

3.5

3.0

2.5

+85°C

(V)

2.0

REFOUT

1.5

V

1.0

0.5

0

-3.0 1.0

MAX12553 toc36

V

COM

10-1

+25°C

I

SINK CURRENT (mA)

REFOUT

-40°C

2.039

MAX12553 toc34

2.037

2.035

(V)

REFOUT

V

2.033

2.031

0-1.0-2.0

2.029

REFP, COM, REFN

SHORT-CIRCUIT PERFORMACE

3.5

3.0

2.5

V

REFP

2.0

1.5

VOLTAGE (V)

1.0

0.5

0

-8 128
SINK CURRENT (mA)

REFERENCE OUTPUT VOLTAGE

vs. TEMPERATURE

-40 85
TEMPERATURE (°C)

V

COM

V

REFN

INTERNAL REFERENCE
MODE AND BUFFERED
EXTERNAL REFERENCE MODE

40-4

603510-15

MAX12553 toc37

MAX12553 toc35

MAX12553

14-Bit, 65Msps, 3.3V ADC

12 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 REFP

2 REFN

3 COM

4, 7, 16,

35

5 INP Positive Analog Input
6 INN Negative Analog Input

8 DCE

9 CLKN

10 CLKP

11 CLKTYP

12–15, 36 V

17, 34 OV

18 DOR

19 D13 CMOS Digital Output, Bit 13 (MSB)
20 D12 CMOS Digital Output, Bit 12
21 D11 CMOS Digital Output, Bit 11
22 D10 CMOS Digital Output, Bit 10
23 D9 CMOS Digital Output, Bit 9
24 D8 CMOS Digital Output, Bit 8
25 D7 CMOS Digital Output, Bit 7
26 D6 CMOS Digital Output, Bit 6
27 D5 CMOS Digital Output, Bit 5

GND Ground. Connect all ground pins and EP together.

DD

DD

- V

Positive Reference I/O. The full-scale analog input range is ±(V
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same

side of the PC board.

Negative Reference I/O. The full-scale analog input range is ±(V
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same

side of the PC board.
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to

GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the

opposite side of the PC board and connected to the MAX12553 through a via.

Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OV

Negative Clock Input. In differential clock input mode (CLKTYP = OV
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single­ended clock signal to CLKP and connect CLKN to GND.

Positive Clock Input. In differential clock input mode (CLKTYP = OV
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single­ended clock signal to CLKP and connect CLKN to GND.

Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OV

Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all V

Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF.

Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).

or VDD to define the differential clock input.

DD

or VDD) to enable the internal duty-cycle equalizer.

DD

REFP

REFP

DD

pins to the same potential.

DD

) x 2/3. Bypass REFP to

REFN

- V

) x 2/3. Bypass REFN to

REFN

or VDD), connect the differential

DD

or VDD), connect the differential

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 13

Pin Description (continued)

Figure 1. Pipeline Architecture—Stage Blocks

PIN NAME FUNCTION

28 D4 CMOS Digital Output, Bit 4
29 D3 CMOS Digital Output, Bit 3
30 D2 CMOS Digital Output, Bit 2
31 D1 CMOS Digital Output, Bit 1
32 D0 CMOS Digital Output, Bit 0 (LSB)

Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for

33 DAV

37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.

38 REFOUT

39 REFIN

40 G/T

—EP

any input clock duty-cycle variations. DAV is typically used to latch the MAX12553 output data into an
external back-end digital circuit.

Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.

Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes,V
reference mode operation, connect REFIN to GND.

Output Format Select Input. Connect G/T to GND for the two’s complement digital output format.
Connect G/T to OV

Exposed Paddle. The MAX12553 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.

or VDD for the Gray code digital output format.

DD

REFP

- V

REFN

= V

x 3/4. For unbuffered external

REFIN

MAX12553

INP

INN

T/H

STAGE 1

T/H

FLASH

ADC

STAGE 2

DIGITAL ERROR CORRECTION

D13–D0

DAC

+

STAGE 9

Σ

−

OUTPUT

DRIVERS

STAGE 10

END OF PIPE

D13–D0

MAX12553

Detailed Description

The MAX12553 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high­speed conversion while minimizing power consump­tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
From input to output, the total clock-cycle latency is 8.5
clock cycles.

Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12553 functional diagram.

Input Track-and-Hold (T/H) Circuit

Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a common-mode input voltage of VDD/2 ±0.5V.

The MAX12553 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3) allowing
the analog input signal to be stored as charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynam­ic current necessary to charge and discharge the sam­pling capacitors. To avoid signal degradation, these

capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.

The analog input of the MAX12553 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid­supply (V

DD

/2). The MAX12553 provides the optimum
common-mode voltage of VDD/2 through the COM out­put when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.

Reference Output (REFOUT)

An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12553. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX12553 or when PD transitions from
high to low. REFOUT has approximately 17kΩ to GND
when the MAX12553 is in power-down.

The internal bandgap reference and its buffer generate
V

REFOUT

to be 2.048V. The reference temperature coeffi­cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.

14-Bit, 65Msps, 3.3V ADC

14 ______________________________________________________________________________________

Figure 2. Simplified Functional Diagram

Figure 3. Simplified Input T/H Circuit

CLKP
CLKN

DCE

CLKTYP

INP

INN

REFOUT

REFIN

REFP

COM

REFN

CLOCK

GENERATOR

AND

DUTY-CYCLE

EQUALIZER

T/H

14-BIT

PIPELINE

ADC

REFERENCE

SYSTEM

MAX12553

OUTPUT

DEC

DRIVERS

POWER CONTROL

AND

BIAS CIRCUITS

V

DD

GND

OV

DD

D13–D0
DAV
DOR

G/T

PD

V

BOND WIRE

INDUCTANCE

1.5nH

INP

BOND WIRE

INDUCTANCE

1.5nH

INN

SAMPLING

CLOCK

*THE EFFECTIVE RESISTANCE OF THE

SWITCHED SAMPLING CAPACITORS IS:

DD

C

PAR

2pF

V

DD

C

PAR

2pF

R

SAMPLE

MAX12553

=

f

CLK

x C

*C

4.5pF

*C

4.5pF

1

SAMPLE

SAMPLE

SAMPLE

REFOUT sources up to 1.0mA and sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
Short-circuit protection limits I

REFOUT

to a 2.1mA
source current when shorted to GND and a 0.24mA
sink current when shorted to VDD.

Analog Inputs and Reference

Configurations

The MAX12553 full-scale analog input range is
adjustable from ±0.35V to ±1.10V with a common­mode input range of VDD/2 ±0.5V. The MAX12553 pro­vides three modes of reference operation. The voltage
at REFIN (V

REFIN

) sets the reference operation mode

(Table 1).
To operate the MAX12553 with the internal reference,

connect REFOUT to REFIN either with a direct short or
through a resistive divider. In this mode, COM, REFP,
and REFN are low-impedance outputs with V

COM

=

VDD/2, V

REFP

= VDD/2 + V

REFIN

x 3/8, and V

REFN

=

VDD/2 - V

REFIN

x 3/8. The REFIN input impedance is

very large (>50MΩ). When driving REFIN through a

resistive divider, use resistances ≥10kΩ to avoid load­ing REFOUT.

Buffered external reference mode is virtually identical to
internal reference mode except that the reference
source is derived from an external reference and not
the MAX12553 REFOUT. In buffered external reference
mode, apply a stable 0.7V to 2.2V source at REFIN. In
this mode, COM, REFP, and REFN are low-impedance
outputs with V

COM

= VDD/2, V

REFP

= VDD/2 + V

REFIN

x

3/8, and V

REFN

= VDD/2 - V

REFIN

x 3/8.

To operate the MAX12553 in unbuffered external refer­ence mode, connect REFIN to GND. Connecting REFIN
to GND deactivates the on-chip reference buffers for
COM, REFP, and REFN. With the respective buffers
deactivated, COM, REFP, and REFN become high­impedance inputs and must be driven through sepa­rate, external reference sources. Drive V

COM

to VDD/2

±5%, and drive REFP and REFN such that V

COM

=

(V

REFP

+ V

REFN

)/2. The full-scale analog input range is

±(V

REFP

- V

REFN

) x 2/3.

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 15

Figure 4. T/H Aperture Timing

Table 1. Reference Modes

CLKP

CLKN

ANALOG

INPUT

SAMPLED

DATA

T/H

TRACK HOLDTRACK HOLDTRACK HOLDTRACKHOLD

t

AD

t

AJ

35% V

V

REFIN

to 100%

REFOUT

V

REFOUT

0.7V to 2.2V

<0.4V

Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider.
The full-scale analog input range is ±V

= VDD/2

V

COM

V

= VDD/2 + V

REFP

= VDD/2 - V

V

REFN

Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN.
The full-scale analog input range is ±V
V

= VDD/2

COM

= VDD/2 + V

V

REFP

V

= VDD/2 - V

REFN

Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources.
The full-scale analog input range is ±(V

REFIN

REFIN

REFIN

REFIN

x 3/8

x 3/8

x 3/8

x 3/8

REFERENCE MODE

/2:

REFIN

/2:

REFIN

- V

REFN

) x 2/3.

REFP

MAX12553

All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to

the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a

0.1µF capacitor.
For detailed circuit suggestions, see Figure 13 and

Figure 14.

Clock Input and Clock Control Lines

(CLKP, CLKN, CLKTYP)

The MAX12553 accepts both differential and single­ended clock inputs. For single-ended clock input oper­ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock input operation, connect CLKTYP
to OVDDor VDD, and drive CLKP and CLKN with the
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.

CLKP and CLKN are high impedance when the
MAX12553 is powered down (Figure 5).

Low clock jitter is required for the specified SNR perfor­mance of the MAX12553. Analog input sampling
occurs on the falling edge of the clock signal, requiring
this edge to have the lowest possible jitter. Jitter limits
the maximum SNR performance of any ADC according
to the following relationship:

where f

IN

represents the analog input frequency and t

J

is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 71dB of SNR with an input frequen­cy of 175MHz, the system must have less than 0.25ps

of clock jitter. In actuality, there are other noise sources
such as thermal noise and quantization noise that con­tribute to the system noise, requiring the clock jitter to
be less than 0.2ps to obtain the specified 71dB of SNR
at 175MHz.

Clock Duty-Cycle Equalizer (DCE)

The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12553 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.

Disabling the clock duty-cycle equalizer reduces the
analog supply current by 1.5mA.

14-Bit, 65Msps, 3.3V ADC

16 ______________________________________________________________________________________

Figure 5. Simplified Clock-Input Circuit

20

log

=×

SNR




2



1

ft

× π ×

IN J






V

DD

S

1H

10kΩ

CLKP

10kΩ

S

2H

S

1L

CLKN

10kΩ

SWITCHES S
DURING POWER-DOWN, MAKING

S

2L

CLKP AND CLKN HIGH IMPEDANCE.

GND

SWITCHES S
SINGLE-ENDED CLOCK MODE.

10kΩ

MAX12553

DUTY-CYCLE

EQUALIZER

AND S2_ ARE OPEN

1_

ARE OPEN IN

2_

System-Timing Requirements

Figure 6 shows the relationship between the clock, ana­log inputs, DAV indicator, DOR indicator, and the result­ing output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.5 clock cycles later.

The DAV indicator is synchronized with the digital out­put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir­cuitry can be latched with the falling edge of the con­version clock (CLKP-CLKN).

Data-Valid Output (DAV)

DAV is a single-ended version of the input clock (CLKP).
Output data changes on the falling edge of DAV, and
DAV rises once output data is valid (Figure 6).

The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle
equalizer disabled (DCE = low), the DAV signal is the
inverse of the signal at CLKP delayed by 6.8ns (t

DAV

).

With the duty-cycle equalizer enabled (DCE = high), the

DAV signal has a fixed pulse width that is independent of
CLKP. In either case, with DCE high or low, output data
at D13–D0 and DOR are valid from 8.5ns before the ris­ing edge of DAV to 6.3ns after the rising edge of DAV,
and the rising edge of DAV is synchronized to have a

6.9ns (t

DAV

) delay from the falling edge of CLKP.

DAV is high impedance when the MAX12553 is in
power-down (PD = high). DAV is capable of sinking
and sourcing 600µA and has three times the drive
strength of D13–D0 and DOR. DAV is typically used to
latch the MAX12553 output data into an external back­end digital circuit.

Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back
into the analog portion of the MAX12553 and degrading
its dynamic performance. An external buffer on DAV
isolates it from heavy capacitive loads. Refer to the
MAX12555 evaluation kit schematic for an example of
DAV driving back-end digital circuitry through an exter­nal buffer.

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 17

DIFFERENTIAL ANALOG INPUT (INP–INN)

Figure 6. System-Timing Diagram

(V

- V

) x 2/3

REFP

REFN

- V

REFN

REFP

) x 2/3

D13–D0

(V

CLKN
CLKP

DAV

DOR

N-3

N-2

N-1

t

AD

t

DAV

N+4

t

SETUP

N+5

N+6

N+7

t

CH

t

HOLD

N+9

N+8

N N+1 N+2 N+3 N+5 N+6 N+7N-1N-2N-3 N+9N+4 N+8

t

SETUP

t

HOLD

N+3

N

N+2

N+1

t

CL

8.5 CLOCK-CYCLE DATA LATENCY

MAX12553

Data Out-of-Range Indicator (DOR)

The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (V

REFP

- V

REFN

) x 3/4 to (V

REFN

- V

REFP

) x 3/4.
Signals outside this valid differential range cause DOR
to assert high as shown in Table 2 and Figure 6.

DOR is synchronized with DAV and transitions along
with the output data D13–D0. There is an 8.5 clock­cycle latency in the DOR function as is with the output
data (Figure 6).

DOR is high impedance when the MAX12553 is in
power-down (PD = high). DOR enters a high-imped­ance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.

Digital Output Data (D13–D0), Output Format (G/T)

The MAX12553 provides a 14-bit, parallel, tri-state out­put bus. D13–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.

The MAX12553 output data format is either Gray code
or two’s complement, depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is two’s comple­ment. See Figure 8 for a binary-to-Gray and Gray-to­binary code-conversion example.

The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:

for Gray code (G/T = 1)

for two’s complement (G/T = 0)
where CODE

10

is the decimal equivalent of the digital

output code as shown in Table 2.
Digital outputs D13–D0 are high impedance when the

MAX12553 is in power-down (PD = high). D13–D0 tran­sition high 10ns after the rising edge of PD and
become active 10ns after PD’s falling edge.

Keep the capacitive load on the MAX12553 digital out­puts D13–D0 as low as possible (<15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12553 and degrading its dynamic perfor­mance. The addition of external digital buffers on the
digital outputs isolates the MAX12553 from heavy
capacitive loading. To improve the dynamic perfor­mance of the MAX12553, add 220Ω resistors in series
with the digital outputs close to the MAX12553. Refer to
the MAX12555 evaluation kit schematic for an example
of the digital outputs driving a digital buffer through
220Ω series resistors.

Power-Down Input (PD)

The MAX12553 has two power modes that are con­trolled with the power-down digital input (PD). With PD

14-Bit, 65Msps, 3.3V ADC

18 ______________________________________________________________________________________

−

4

VV V V

−−

INP INN REFP REFN

=×× ()

VV V V

−−=××()

INP INN REFP REFN

CODE

3

CODE

4
3 16384

10

16384

10

8192

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 19

INN

Table 2. Output Codes vs. Input Voltage

- V

= 0.882V

= 2.418V

INP

V

REFP

REFN

V

V

()

OF

DECIMAL

(G/T = 0)

OUTPUT CODE

TWO’S-COMPLEMENT

D13 ➝ D0

EQUIVALENT

OF

D13➝ D0

EQUIVALENT

HEXADECIMAL

DOR

>+1.023875V

)

10

(CODE

RANGE)

(DATA OUT OF

RANGE)

<-1.024000V

(DATA OUT OF

BINARY

D13 ➝ D0

)

10

OF

DECIMAL

(G/T = 1)

GRAY CODE

OUTPUT CODE

EQUIVALENT

HEXADECIMAL

(CODE

D13 ➝ D0

OF

D13 ➝ D0

EQUIVALENT

DOR

BINARY

D13 ➝ D0

10 0000 0000 0000 1 0x2000 [phone] 1111 1 0x1FFF +8191

10 0000 0000 0000 0 0x2000 [phone] 1111 0 0x1FFF +8191 +1.023875V

10 0000 0000 0001 0 0x2001 [phone] 1110 0 0x1FFE +8190 +1.023750V

11 0000 0000 0011 0 0x3003 [phone] 0010 0 0x0002 +2 +0.000250V

11 0000 0000 0001 0 0x3001 [phone] 0001 0 0x0001 +1 +0.000125V

11 0000 0000 0000 0 0x3000 [phone] 0000 0 0x0000 0 +0.000000V

01 0000 0000 0000 0 0x1000 [phone] 1111 0 0x3FFF -1 -0.000125V

01 0000 0000 0001 0 0x1001 [phone] 1110 0 0x3FFE -2 -0.000250V

00 0000 0000 0000 0 0x0000 0 10 0000 0000 0000 0 0x2000 -8192 -1.024000V

00 0000 0000 0001 0 0x0001 [phone] 0 0x2001 -8191 -1.023875V

00 0000 0000 0000 1 0x0000 0 10 0000 0000 0000 1 0x2000 -8192

MAX12553

14-Bit, 65Msps, 3.3V ADC

20 ______________________________________________________________________________________

low, the MAX12553 is in normal operating mode. With
PD high, the MAX12553 is in power-down mode.

The power-down mode allows the MAX12553 to effi­ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12553 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.

In power-down mode, all internal circuits are off, the
analog supply current reduces to 0.045mA, and the
digital supply current reduces to 0.02mA. The following
list shows the state of the analog inputs and digital out­puts in power-down mode:

• INP, INN analog inputs are disconnected from the
internal input amplifier (Figure 3).

• REFOUT has approximately 17kΩ to GND.

• REFP, COM, REFN go high impedance with respect
to V

DD

and GND, but there is an internal 4kΩ resistor
between REFP and COM, as well as an internal 4kΩ
resistor between REFN and COM.

• D13–D0, DOR, and DAV go high impedance.

• CLKP, CLKN go high impedance (Figure 5).
The wake-up time from power-down mode is dominat-

ed by the time required to charge the capacitors at
REFP, REFN, and COM. In internal reference mode and
buffered external reference mode, the wake-up time is

typically 10ms with the recommended capacitor array
(Figure 13). When operating in unbuffered external ref­erence mode, the wake-up time is dependent on the
external reference drivers.

Applications Information

Using Transformer Coupling

In general, the MAX12553 provides better SFDR and THD
performance with fully differential input signals as
opposed to single-ended input drive. In differential input
mode, even-order harmonics are lower as both inputs are
balanced, and each of the ADC inputs only requires half
the signal swing compared to single-ended input mode.

An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12553
for optimum performance. Connecting the center tap of
the transformer to COM provides a VDD/2 DC level shift
to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 10 is good
for frequencies up to Nyquist (f

CLK

/2).
The circuit of Figure 11 converts a single-ended input
signal to fully differential just as Figure 10. However,
Figure 11 utilizes an additional transformer to improve

Figure 7. Two’s Complement Transfer Function (G/T= 0)

Figure 8. Gray Code Transfer Function (G/T= 1)

V

0x1FFF
0x1FFE

0x1FFD

1 LSB =

(V

- V

REFP

REFN

16384

) x 2/3 (V

- V

REFP

REFN

x

REFP

4
3

- V

) x 2/3

REFN

0x2000
0x2001
0x2003

- V

V

REFP

1 LSB =

(V

- V

REFP

REFN

16384

) x 2/3 (V

REFN

x

REFP

4
3

- V

) x 2/3

REFN

0x0001
0x0000
0x3FFF

0x2003

TWO'S COMPLEMENT OUTPUT CODE (LSB)

0x2002
0x2001
0x2000

-8189 +8191+8189-1 0 +1-8191
DIFFERENTIAL INPUT VOLTAGE (LSB)

0x3001
0x3000
0x1000

GRAY OUTPUT CODE (LSB)

0x0002
0x0003
0x0001
0x0000

-8191 -8189
DIFFERENTIAL INPUT VOLTAGE (LSB)

+1 +8191+8189-1

0

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 21

Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion

BINARY-TO-GRAY CODE CONVERSION

1) THE MOST SIGNIFICANT GRAY CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.

D11 D7 D3 D0

D13

01

1011 0100 1100 BINARY

2) SUBSEQUENT GRAY CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:

GRAYX = BINARYX BINARY

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION.

GRAY12 = BINARY12 BINARY
GRAY12 = 1 0

= 1

GRAY

12

D13

011 101001100

0

3) REPEAT STEP 2 UNTIL COMPLETE.
GRAY11 = BINARY11 BINARY

GRAY11 = 1 1
GRAY

11

D13

01 1 1 0100 1100

D11 D7 D3 D0

1

= 0

D11 D7 D3 D0

X+1

13

10

12

BIT POSITION

GRAY CODE0

BIT POSITION

BINARY

GRAY CODE

BIT POSITION
BINARY

GRAY-TO-BINARY CODE CONVERSION

1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME
AS THE MOST SIGNIFICANT GRAY CODE BIT.

D11 D7 D3 D0

D13

01

0110 1110 1010 GRAY CODE

2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:

BINARYX = BINARY

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION.

BINARY12 = BINARY13 GRAY
BINARY12 = 0 1

= 1

BINARY

12

D13

0

0

3) REPEAT STEP 2 UNTIL COMPLETE.
BINARY11 = BINARY12 GRAY

BINARY11 = 1 0

= 1

BINARY

11

D13

01 0 1110 1010

GRAY

X+1

D11 D7 D3 D0

1

001110 1010

1

D11 D7 D3 D0

11

0

X

12

11

11

BIT POSITION

BINARY0

BIT POSITION

GRAY CODE

BINARY

BIT POSITION
GRAY CODE

0

1100

4) THE FINAL GRAY CODE CONVERSION IS:
D11 D7 D3 D0

D13
01 1 1 0100 1100

10

GRAY CODE

BIT POSITION
BINARY

GRAY CODE0 101101110 1010

EXCULSIVE OR TRUTH TABLE

AB

00
01
10
11

0

11

4) THE FINAL GRAY CODE CONVERSION IS:
D11 D7 D3 D0

D13

01 0 0 1110 1010

Y = A B

0
1
1
0

11

BINARY

BIT POSITION
GRAY CODE

BINARY0 111010100 1100

MAX12553

14-Bit, 65Msps, 3.3V ADC

22 ______________________________________________________________________________________

the common-mode rejection, allowing high-frequency
signals beyond the Nyquist frequency. The two sets of
termination resistors provide an equivalent 75Ω termi-
nation to the signal source. The second set of termina­tion resistors connects to COM, providing the correct
input common-mode voltage. Two 0Ω resistors in series
with the analog inputs allow high IF input frequencies.
These 0Ω resistors can be replaced with low-value
resistors to limit the input bandwidth.

Single-Ended, AC-Coupled Input Signal

Figure 12 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.

Figure 10. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist

Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist

Figure 12. Single-Ended, AC-Coupled Input Drive

24.9Ω

0.1µF

V

IN

N.C.

MINICIRCUITS

TT1-6 OR T1-1T

6

1

T1

2

5

3

4

12pF

2.2µF

24.9Ω

12pF

0.1µF

V

IN

N.C.

1

T1

2

3

MINICIRCUITS

ADT1-1WT

6

5

4

*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE
RESISTORS TO LIMIT THE BANDWIDTH.

INP

COM

INN

MAX12553

75Ω

0.5%

N.C. N.C.

75Ω

0.5%

1

T2

2

3

MINICIRCUITS

ADT1-1WT

V

MAX4108

IN

100Ω

100Ω

0.1µF

24.9Ω

24.9Ω

5.6pF

2.2µF

5.6pF

0Ω*

6

5

4

110Ω

0.1%

110Ω

0.1%

5.6pF

2.2µF

0Ω*

5.6pF

INP

MAX12553

COM

INN

INP

MAX12553

COM

INN

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 23

Buffered External Reference

Drives Multiple ADCs

The buffered external reference mode allows for more
control over the MAX12553 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is >50MΩ.

Figure 13 uses the MAX6029EUK21 precision 2.048V
reference as a common reference for multiple convert­ers. The 2.048V output of the MAX6029 passes through
a one-pole 10Hz lowpass filter to the MAX4230. The
MAX4230 buffers the 2.048V reference and provides
additional 10Hz lowpass filtering before its output is
applied to the REFIN input of the MAX12553.

Figure 13. External Buffered Reference Driving Multiple ADCs

+3.3V

1

2

MAX6029EUK21

0.1µF

*PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.

16.2kΩ

1µF

5

2.048V

NOTE: ONE FRONT-END REFERENCE
CIRCUIT IS CAPABLE OF SOURCING 15mA
AND SINKING 30mA OF OUTPUT CURRENT.

+3.3V

0.1µF

5

2

MAX4230

4

47Ω

10µF
6V

1.47kΩ

2.048V

330µF
6V

1

3

0.1µF

0.1µF

38

39

38

0.1µF

REFOUT

REFIN

0.1µF

REFOUT

+3.3V

2.2µF

V

DD

MAX12553

GND

+3.3V

2.2µF

V

DD

MAX12553

REFP

REFN

COM

REFP

REFN

0.1µF

1

1µF* 10µF

2

0.1µF

3

2.2µF

0.1µF

1

1µF* 10µF

2

0.1µF

39

REFIN

GND

COM

3

2.2µF

MAX12553

14-Bit, 65Msps, 3.3V ADC

24 ______________________________________________________________________________________

Unbuffered External

Reference Drives Multiple ADCs

The unbuffered external reference mode allows for pre­cise control over the MAX12553 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer­ence, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.

Figure 14 uses the MAX6029EUK30 precision 3.000V
reference as a common reference for multiple convert­ers. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz lowpass filter. Three
MAX4230 operational amplifiers buffer taps along this
resistor chain providing 2.413V, 1.647V, and 0.880V to
the MAX12553’s REFP, COM, REFN reference inputs,

Figure 14. External Unbuffered Reference Driving Multiple ADCs

+3.3V

1

0.1µF

MAX6029EUK30

2

3.000V

0.47µF

5

20kΩ
1%

20kΩ
1%

52.3kΩ
1%

52.3kΩ
1%

20kΩ
1%

20kΩ
1%

20kΩ
1%

0.1µF

1

3

0.1µF

1

3

0.1µF

1

3

+3.3V

+3.3V

+3.3V

5

2

5

2

5

2

MAX4230

4

MAX4230

4

MAX4230

4

47Ω

10µF
6V

1.47kΩ

47Ω

10µF
6V

1.47kΩ

47Ω

10µF
6V

2.413V

330µF
6V

1.647V

330µF
6V

0.880V

330µF
6V

10µF

10µF

0.1µF

0.1µF

0.1µF

0.1µF

1µF*

1µF*

2.2µF

1

2

3

1

2

REFP

REFN

COM

REFP

REFN

+3.3V

0.1µF

V

DD

MAX12553

GND

+3.3V

0.1µF

V

DD

MAX12553

2.2µF

REFOUT

2.2µF

REFOUT

REFIN

38

0.1µF

0.1µF

39

38

0.1µF

2.2µF

3

COM

1.47kΩ

*PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.

GND

REFIN

39

MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 25

respectively. The feedback around the MAX4230 op
amps provides additional 10Hz lowpass filtering. The

2.413V and 0.880V reference voltages set the full-scale
analog input range to ±1.022V = ±(V

REFP

- V

REFN

) x 2/3.
A common power source for all active components
removes any concern regarding power-supply
sequencing when powering up or down.

Grounding, Bypassing, and

Board Layout

The MAX12553 requires high-speed board layout
design techniques. Refer to the MAX12555 evaluation
kit. data sheet for a board layout reference. Locate all
bypass capacitors as close to the device as possible,
preferably on the same side of the board as the ADC,
using surface-mount devices for minimum inductance.
Bypass VDDto GND with a 0.1µF ceramic capacitor in
parallel with a 2.2µF ceramic capacitor. Bypass OV

DD

to GND with a 0.1µF ceramic capacitor in parallel with a

2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes

produce the highest level of signal integrity. All
MAX12553 GNDs and the exposed backside paddle
must be connected to the same ground plane. The
MAX12553 relies on the exposed backside paddle con­nection for a low-inductance ground connection. Use
multiple vias to connect the top-side ground to the bot­tom-side ground. Isolate the ground plane from any
noisy digital system ground planes such as a DSP or
output buffer ground.

Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.

Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equal­ly. Refer to the MAX12555 evaluation kit data sheet for
an example of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX12553, this straight line is between the end points
of the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step of the transfer function and the worst-case devia­tion is reported in the Electrical Characteristics table.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no

missing codes and a monotonic transfer function. For
the MAX12553, DNL deviations are measured at every
step of the transfer function and the worst-case devia­tion is reported in the Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX12553 transition occurs at 0.5 LSB above mid­scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. The slope of the actual
transfer function is measured between two data points:
positive full scale and negative full scale. Ideally, the
positive full-scale MAX12553 transition occurs at 1.5
LSBs below positive full scale, and the negative full­scale transition occurs at 0.5 LSB above negative full
scale. The gain error is the difference of the measured
transition points minus the difference of the ideal transi­tion points.

Small-Signal Noise Floor (SSNF)

Small-signal noise floor is the integrated noise and dis­tortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calcu­lation. For this converter, a small signal is defined as a
single tone with an amplitude less than -35dBFS. This
parameter captures the thermal and quantization noise
characteristics of the converter and can be used to
help calculate the overall noise figure of a receive
channel. Go to www.maxim-ic.com for application
notes on thermal + quantization noise floor.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N bits):

SNR

[max]

= 6.02 × N + 1.76

In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec­tral components to the Nyquist frequency excluding the

MAX12553

14-Bit, 65Msps, 3.3V ADC

26 ______________________________________________________________________________________

fundamental, the first six harmonics (HD2–HD7), and
the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal
to the RMS noise plus distortion. RMS noise plus distor­tion includes all spectral components to the Nyquist fre­quency excluding the fundamental and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:

Single-Tone Spurious-Free Dynamic Range

(SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS amplitude of the next-largest spurious
component, excluding DC offset.

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first six harmon­ics of the input signal to the fundamental itself. This is
expressed as:

where V1is the fundamental amplitude, and V2through
V7are the amplitudes of the 2nd- through 7th-order
harmonics (HD2–HD7).

Intermodulation Distortion (IMD)

IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:

The fundamental input tone amplitudes (V

1

and V2) are

at -7dBFS. Fourteen intermodulation products (V

IM

_)
are used in the MAX12553 IMD calculation. The inter­modulation products are the amplitudes of the output
spectrum at the following frequencies, where f

IN1

and

f

IN2

are the fundamental input tone frequencies:

• Second-order intermodulation products:

f

IN1

+ f

IN2

, f

IN2

- f

IN1

• Third-order intermodulation products:

2 x f

IN1

- f

IN2

, 2 x f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

• Fourth-order intermodulation products:

3 x f

IN1

- f

IN2

, 3 x f

IN2

- f

IN1

, 3 x f

IN1

+ f

IN2

, 3 x f

IN2

+ f

IN1

• Fifth-order intermodulation products:

3 x f

IN1

- 2 x f

IN2

, 3 x f

IN2

- 2 x f

IN1

, 3 x f

IN1

+ 2 x f

IN2

,

3 x f

IN2

+ 2 x f

IN1

Third-Order Intermodulation (IM3)

IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones f

IN1

and f

IN2

. The
individual input tone levels are at -7dBFS. The third­order intermodulation products are 2 x f

IN1

- f

IN2

, 2 x

f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

.

Two-Tone Spurious-Free Dynamic Range

(SFDR

TT

)

SFDRTTrepresents the ratio, expressed in decibels, of
the RMS amplitude of either input tone to the RMS
amplitude of the next-largest spurious component in the
spectrum, excluding DC offset. This spurious compo­nent can occur anywhere in the spectrum up to Nyquist
and is usually an intermodulation product or a harmonic.

Aperture Delay

The MAX12553 samples data on the falling edge of its
sampling clock. In actuality, there is a small delay
between the falling edge of the sampling clock and the

ENOB



=




SINAD

602

.

− 176

.






THD

20

log

=×



2

2

2

2



VVVVVV

+++++

2

3

4







5

V

1

2

6



2



7









2

VV V V

IM IM IM IM

1

IMD

log

=×

20





2

.......

+++ +

2

VV

+

122

2

13

2



2

14





MAX12553

14-Bit, 65Msps, 3.3V ADC

______________________________________________________________________________________ 27

actual sampling instant. Aperture delay (tAD) is the time
defined between the falling edge of the sampling clock
and the instant when an actual sample is taken (Figure 4).

Aperture Jitter

Figure 4 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.

Output Noise (n

OUT

)

The output noise (n

OUT

) parameter is similar to the ther­mal + quantization noise parameter and is an indication
of the ADC’s overall noise performance.

No fundamental input tone is used to test for n

OUT

; INP,
INN, and COM are connected together and 1024k data
points collected. n

OUT

is computed by taking the RMS

value of the collected data points.

Overdrive Recovery Time

Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12553 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%.

Pin Configuration

TOP VIEW

REFIN39REFOUT38PD37V

G/T

40

REFP 1
REFN 2
COM 3

GND 4

INP 5
INN 6

GND 7

DCE 8
CLKN 9
CLKP 10

11

CLKTYP

12

V

36

MAX12553

EXPOSED PADDLE (GND)

13

14

15

DD

DD

DD

V

V

THIN QFN

6mm x 6mm x 0.8mm

DD

DD

GND35OV

DAV33D032D1

34

16

17

DD

V

GND

OV

31

D230
D329
D428
D527
D626
D725
D824
D923
D1022
D1121

18

20

DD

D1319D12

DOR

MAX12553

14-Bit, 65Msps, 3.3V ADC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

D

D/2

E/2

(NE-1) X e

L

L1

e

A1 A2

E

A

D2

C

L

k

(ND-1) X e

C
L

e e

PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm

b

D2/2

e

21-0141

E2/2

C

E2

L

k

L

C

L

QFN THIN 6x6x0.8.EPS

LL

1

E

2

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm

21-0141

2

E

2