MAXIM MAX12528 Technical data

General Description

The MAX12528 is a dual 80Msps, 12-bit analog-to-digi­tal converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12528 is optimized for low power, small size,
and high dynamic performance in intermediate frequen­cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 726mW while delivering a typical 69.8dB signal-to­noise ratio (SNR) performance at a 175MHz input fre­quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper­ating power, the MAX12528 features a 330µW power­down mode to conserve power during idle periods.

A flexible reference structure allows the MAX12528 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer­ence to be shared between the two ADCs. The refer­ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12528
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.

The MAX12528 supports either a single-ended or differ­ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil­ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).

The MAX12528 features two parallel, 12-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out­puts accepts a 1.7V to 3.6V voltage for flexible interfac­ing with various logic levels. The MAX12528 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.

Applications

IF and Baseband Communication Receivers

Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN

I/Q Receivers

Medical Imaging

Portable Instrumentation

Digital Set-Top Boxes

Low-Power Data Acquisition

Features

♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance

70.7dB/69.8dB SNR at f

IN

= 70MHz/175MHz

78.2dBc/72.9dBc SFDR at fIN= 70MHz/175MHz

♦ 3.3V Low-Power Operation

760mW (Differential Clock Mode)
726mW (Single-Ended Clock Mode)

♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Internal, External, or Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
♦ CMOS Outputs in Two’s Complement or Gray

Code

♦ Out-of-Range and Data-Valid Indicators
♦ Compact, 68-Pin Thin QFN Package (10mm x

10mm x 0.8mm)

♦ Evaluation Kit Available (Order MAX12528EVKIT)

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3643; Rev 0; 4/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

*EP = Exposed paddle.

Selector Guide

PART

SAMPLING RATE

(Msps)

RESOLUTION

(Bits)

MAX12528 80 12

MAX12557 65 14

MAX12527 65 12

PART TEMP RANGE PIN-PACKAGE

MAX12528ETK -40°C to +85°C

68 Thin QFN-EP*

PKG

CODE

T6800-2

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, AIN= -0.5dBFS (differen­tial), DIFFCLK/SECLK = OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 80MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND ................................................................-0.3V to +3.6V

OV

DD

to GND............-0.3V to the lower of (VDD+ 0.3V) and +3.6V

INAP, INAN to GND ...-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

INBP, INBN to GND ...-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

CLKP, CLKN to

GND ........................-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

REFIN, REFOUT

to GND ..................-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

REFAP, REFAN,

COMA to GND ......-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

REFBP, REFBN,

COMB to GND ......-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,

DIV4 to GND .........-0.3V to the lower of (V

DD

+ 0.3V) and +3.6V

D0A–D11A, D0B–D11B, DAV,

DORA, DORB to GND..............................-0.3V to (OV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)
68-Pin Thin QFN 10mm x 10mm x 0.8mm

(derate 70mW/°C above +70°C) ....................................4000mW

Thermal Resistance θjc........................................................0.4°C/W

Operating Temperature Range................................-40°C to +85°C

Junction Temperature ...........................................................+150°C

Storage Temperature Range .................................-65°C to +150°C

Lead Temperature (soldering, 10s)......................................+300°C

DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity INL fIN = 3MHz ±0.6 ±1.6 LSB

Differential Nonlinearity DNL fIN = 3MHz, no missing codes ±0.3 ±0.85 LSB
Offset Error ±0.1 ±0.7 %FSR

Gain Error ±0.5 ±4.3 %FSR

ANALOG INPUT (INAP, INAN, INBP, INBN)

Differential Input Voltage Range V

Common-Mode Input Voltage V

Analog Input Resistance R

Analog Input Capacitance

CONVERSION RATE

Maximum Clock Frequency f

Minimum Clock Frequency 5 MHz

Data Latency Figure 5 8

DYNAMIC CHARACTERISTICS

Small-Signal Noise Floor SSNF Input at -35dBFS 71.0 72.1 dBFS

Signal-to-Noise Ratio SNR

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIFF

C

PAR

C

SAMPLE

CLK

IN

Differential or single-ended inputs ±1.024 V

Each input (Figure 3) 2 kΩ

Fixed capacitance to ground,
each input (Figure 3)

Switched capacitance,
each input (Figure 3)

fIN = 3MHz at -0.5dBFS 69.3 71.2

fIN = 40MHz at -0.5dBFS 70.7

fIN = 70MHz at -0.5dBFS 70.7

f

= 175MHz at -0.5dBFS 67.1 69.8

IN

/ 2 V

DD

2

4.5

80 MHz

pF

Clock

Cycles

dB

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, AIN= -0.5dBFS (differen­tial), DIFFCLK/SECLK = OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 80MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Signal-to-Noise Plus Distortion SINAD

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Second Harmonic HD2

Third Harmonic HD3

Two-Tone Intermodulation
Distortion (Note 2)

3rd-Order Intermodulation
Distortion

Two-Tone Spurious-Free
Dynamic Range

Full-Power Bandwidth FPBW Input at -0.2dBFS, -3dB rolloff 750 MHz

Aperture Delay t

Aperture Jitter t

Output Noise n

fIN = 3MHz at -0.5dBFS 68.9 70.8

fIN = 40MHz at -0.5dBFS 70.2

fIN = 70MHz at -0.5dBFS 69.6

= 175MHz at -0.5dBFS 64.6 67.7

f

IN

fIN = 3MHz at -0.5dBFS 74.7 85.6

fIN = 40MHz at -0.5dBFS 81.8

fIN = 70MHz at -0.5dBFS 78.2

f

= 175MHz at -0.5dBFS 67.2 72.9

IN

fIN = 3MHz at -0.5dBFS -84.2 -73.3

fIN = 40MHz at -0.5dBFS -79.3

fIN = 70MHz at -0.5dBFS -75.8

f

= 175MHz at -0.5dBFS -71.9 -66.4

IN

fIN = 3MHz at -0.5dBFS -87.2

fIN = 40MHz at -0.5dBFS -85.2

fIN = 70MHz at -0.5dBFS -85

= 175MHz at -0.5dBFS -81.5

f

IN

fIN = 3MHz at -0.5dBFS -92.1

fIN = 40MHz at -0.5dBFS -85.5

fIN = 70MHz at -0.5dBFS -78.2

= 175MHz at -0.5dBFS -72.9

f

IN

f

= 68.5MHz at -7dBFS

IN1

f

= 71.5MHz at -7dBFS

TTIMD

IM3

SFDR

AD

AJ

OUT

IN2

f

= 172.5MHz at -7dBFS

IN1

f

= 177.5MHz at -7dBFS

IN2

f

= 68.5MHz at -7dBFS

IN1

f

= 71.5MHz at -7dBFS

IN2

f

= 172.5MHz at -7dBFS

IN1

f

= 177.5MHz at -7dBFS

IN2

f

= 68.5MHz at -7dBFS

IN1

= 71.5MHz at -7dBFS

f

IN2

TT

f

= 172.5MHz at -7dBFS

IN1

= 177.5MHz at -7dBFS

f

IN2

Figure 5 1.2 ns

INAP = INAN = COMA
INBP = INBN = COMB

-77.5

-72.8

-78.6

-74.3

78.6

74.3

<0.15 ps

0.3 LSB

dB

dBc

dBc

dBc

dBc

dBc

dBc

dBc

RMS

RMS

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, AIN= -0.5dBFS (differen­tial), DIFFCLK/SECLK = OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 80MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Overdrive Recovery Time ±10% beyond full scale 1

INTERCHANNEL CHARACTERISTICS

Crosstalk Rejection

Gain Matching ±0.01 ±0.1 dB

Offset Matching ±0.01 %FSR

INTERNAL REFERENCE (REFOUT)

REFOUT Output Voltage V

REFOUT Load Regulation -1mA < I

REFOUT Temperature Coefficient TC

REFOUT Short-Circuit Current

BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
V

REFAP/VREFAN/VCOMA

REFIN Input Voltage V

REFIN Input Resistance R

COM_ Output Voltage

REF_P Output Voltage

REF_N Output Voltage

Differential Reference Voltage

Differential Reference
Temperature Coefficient

UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
externally, V

COMA

= V

REF_P Input Voltage

REF_N Input Voltage

COM_ Input Voltage V

Differential Reference Voltage

REFOUT

REF

f

or f

INA

INB

f

or f

INA

INB

REFOUT

= 70MHz at -0.5dBFS 90

= 175MHz at -0.5dBFS 85

< +1mA 35 mV/mA

Short to VDD—sinking 0.24

Short to GND—sourcing 2.1

and V

COMB

REFBP/VREFBN/VCOMB

REFIN

REFIN

V

COMA

V

COMB

V

REFAP

V

REFBP

V

REFAN

V

REFBN

V

REFA

V

REFB

TC

REF

= VDD / 2)

V

REFAP

V

REFBP

V

REFAN

V

REFBN

COM

V

REFA

V

REFB

are generated internally)

VDD / 2 1.60 1.65 1.70 V

VDD / 2 + (V

VDD / 2 - (V

V

= V

REFA

V

= V

REFB

V

- V

REF_P

V

- V

REF_N

x 3/8) 2.418 V

REFIN

x 3/8) 0.882 V

REFIN

- V

REFAP

REFBP

COM

COM

REFAN

- V

REFBN

REFAP/VREFAN/VCOMA

and V

VDD / 2 1.65 V

V

REF_

= V

REF_P

- V

REF_N

= V

x 3/4 1.536 V

REFIN

1.995 2.048 2.075 V

65 ppm/°C

2.048 V

>50 MΩ

1.440 1.536 1.590 V

30 ppm/°C

REFBP/VREFBN/VCOMB

are applied

+0.768 V

-0.768 V

Clock

cycle

dB

mA

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, AIN= -0.5dBFS (differen­tial), DIFFCLK/SECLK = OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 80MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

REF_P Sink Current

REF_N Source Current

COM_ Sink Current

REF_P, REF_N Capacitance

COM_ Capacitance C

CLOCK INPUTS (CLKP, CLKN)

Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold

Minimum Differential Clock Input
Voltage Swing

Differential Input Common-Mode
Voltage

CLK_ Input Resistance R

CLK_ Input Capacitance C

DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4)

Input High Threshold V

Input Low Threshold V

Input Leakage Current

Digital Input Capacitance C

DIGITAL OUTPUTS (D0A–D11A, D0B–D11B, DORA, DORB, DAV)

Output-Voltage Low V

Output-Voltage High V

Three-State Leakage Current
(Note 3)

I

REFAP

I

REFBP

I

REFAN

I

REFBN

I

COMA

I

COMB

C

REF_P

C

REF_N

COM_

V

V

CLK

CLK

,

IH

IL

IH

IL

V

= 2.418V 1.2 mA

REF_P

V

= 0.882V 0.85 mA

REF_N

V

= 1.65V 0.85 mA

COM_

DIFFCLK/SECLK = GND, CLKN = GND

DIFFCLK/SECLK = GND, CLKN = GND

DIFFCLK/SECLK = OV

DIFFCLK/SECLK = OV

DD

DD

Each input (Figure 4) 5 kΩ

Each input 2 pF

OVDD applied to input ±5

Input connected to ground ±5

DIN

D0A–D11A, D0B–D11B, DORA, DORB:
I

= 200µA

SINK

DAV: I

D0A–D11A, D0B–D11B, DORA, DORB:
I

SOURCE

DAV: I

= 600µA 0.2

SINK

OV

= 200µA

SOURCE

= 600µA

OV

OVDD applied to input ±5

Input connected to ground ±5

OH

I

LEAK

OL

0.8 x
V

DD

0.8 x

OV

DD

0.2

DD

0.2

13 pF

6pF

0.2 V

V

DD

DD

5pF

-

-

0.2 x
V

DD

/ 2 V

0.2 x

OV

DD

0.2

V

V

P-P

V

V

µA

V

V

µA

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, AIN= -0.5dBFS (differen­tial), DIFFCLK/SECLK = OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 80MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

D 0A–D 11A, D O RA,
D 0B–D 11B and D ORB Thr ee- S tate
O utp ut C ap aci tance

DAV Three-State Output
Capacitance

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Output Supply Voltage OV

Analog Supply Current I

Analog Power Dissipation P

Digital Output Supply Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

C

OUT

C

DAV

DD

VDD

VDD

OVDD

DD

( N ote 3) 3 pF

(Note 3) 6 pF

Normal operating mode
f

= 175MHz at -0.5dBFS,

IN

single-ended clock
(DIFFCLK/SECLK = GND)

Normal operating mode

= 175MHz at -0.5dBFS,

f

IN

differential clock
(DIFFCLK/SECLK = OV

Power-down mode (PD = OVDD)
clock idle

Normal operating mode
f

= 175MHz at -0.5dBFS,

IN

single-ended clock
(DIFFCLK/SECLK = GND)

Normal operating mode

= 175MHz at -0.5dBFS,

f

IN

differential clock
(DIFFCLK/SECLK = OV

Power-down mode (PD = OVDD)
clock idle

Normal operating mode

= 175MHz at -0.5dBFS

f

IN

Power-down mode (PD = OVDD)
clock idle

DD

DD

)

)

3.15 3.30 3.60 V

1.70 2.0 V

220

230 250

0.1

726

760 825

0.330

20.7

0.004

DD

V

mA

mW

mA

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈ 10pF at digital outputs, AIN= -0.5dBFS (differen­tial), DIFFCLK/SECLK = OV

DD

, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f

CLK

= 80MHz, TA= -40°C to

+85°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 1)

Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: Two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input

power of both input tones.

Note 3: During power-down, D0A–D11A, D0B–D11B, DORA, DORB, and DAV are high impedance.
Note 4: Guaranteed by design and characterization.

Typical Operating Characteristics

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, AIN= -0.5dBFS,
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, f

CLK

= 80MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30 35 402515 20105

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-120
0

FFT PLOT (16,384-POINT DATA RECORD)

MAX12528 toc01

f

CLK

= 80MHz

f

IN

= 2.99926758MHz

A

IN

= -0.46dBFS
SNR = 70.9dB
SINAD = 70.7dB
THD = -84dBc
SFDR = 85.5dBc
HD2 = -86dBc
HD3 = -101dBc

f

IN

HD2

HD3

FFT PLOT (32,768-POINT DATA RECORD)

MAX12528 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30 35 402515 20105

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-120
0

f

CLK

= 80MHz

f

IN

= 39.5092773MHz

A

IN

= -0.482dBFS
SNR = 71.1dB
SINAD = 70.5dB
THD = -79.1dBc
SFDR = 82.7dBc
HD2 = -87.6dBc
HD3 = -82.7dBc

f

IN

HD2

HD3

FFT PLOT (32,768-POINT DATA RECORD)

MAX12528 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30 35 402515 20105

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-120
0

f

CLK

= 80MHz

f

IN

= 69.8999023MHz

A

IN

= -0.437dBFS
SNR = 71dB
SINAD = 69.2dB
THD = -73.9dBc
SFDR = 74.6dBc
HD2 = -94.6dBc
HD3 = -74.6dBc

HD3

HD2

f

IN

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TIMING CHARACTERISTICS (Figure 5)

Clock Pulse-Width High t

Clock Pulse-Width Low t

Data-Valid Delay t

Data Setup Time Before Rising
Edge of DAV

Data Hold Time After Rising Edge
of DAV

Wake-Up Time from Power-Down t

CH

CL

DAV

t

SETUP

t

HOLD

WAKE

(Note 4) 5.0 ns

(Note 4) 5.5 ns

V

= 2.048V 10 ms

REFIN

6.2 ns

6.2 ns

5.3 ns

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, AIN= -0.5dBFS,
DIFFCLK/SECLK = OV

DD

, PD = GND, G/T = GND, f

CLK

= 80MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

FFT PLOT (32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120

f

IN

0

ANALOG INPUT FREQUENCY (MHz)

f

= 80MHz

CLK

= 174.9780273MHz

f

IN

= -0.468dBFS

A

IN

SNR = 69.5dB
SINAD = 67.9dB
THD = -73.1dBc
SFDR = 75dBc
HD2 = -79.3dBc
HD3 = -75dBc

HD2

30 35 402515 20105

MAX12528 toc04

HD3

AMPLITUDE (dBFS)

0

-20

-40

-60

-80

-100

-120

TWO-TONE IMD PLOT

(16,384-POINT DATA RECORD)

f

CLK

f

IN1

f

IN2

A

2f

+ f

IN2

A
IM3 = -92.3dBc
IMD = -89.1dBc

IN1

f

IN1

0

f

IN2

ANALOG INPUT FREQUENCY (MHz)

= 65.00352MHz
= 68.49889MHz
= 71.49832MHz

= -6.96dBFS

IN1

= -7.02dBFS

IN2

(16,384-POINT DATA RECORD)

0

f

= 65.00352MHz

CLK

= 172.50293MHz

f

IN1

-20

= -6.99dBFS

A

MAX12528 toc05

30252015105

IN1

= 177.40198MHz

f

IN2

= -7.01dBFS

A

IN2

-40

IM3 = -88.9dBc
IMD = -82.2dBc

-60

f

AMPLITUDE (dBFS)

-100

-120

IN2

-80

0

ANALOG INPUT FREQUENCY (MHz)

- f

TWO-TONE IMD PLOT

f

IN2

IN1

f

IN1

f

MAX12528 toc06

+ f

IN1

IN2

30252015105

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

f

= 80MHz

CLK

0.8

= 2.1655273MHz

f

0.6

0.4

0.2

0

INL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0

IN

3072 3584 409625601536 204810245120

DIGITAL OUTPUT CODE

MAX12528 toc07

DNL (LSB)

-THD, SFDR vs. ANALOG INPUT FREQUENCY
= 80MHz, AIN = -0.5dBFS)

(f

CLK

90

85

80

75

70

65

-THD, SFDR (dBc)

60

55

50

0400

SFDR

-THD

fIN (MHz)

MAX12528 toc10

350300200 250100 15050

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

f

= 80MHz

CLK

0.8

= 2.1655273MHz

f

IN

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

(f

75

65

55

45

SNR, SINAD (dB)

35

25

15

CLK

-55 0

3072 3584 409625601536 204810245120

DIGITAL OUTPUT CODE

= 80MHz, fIN = 70MHz)

SNR

AIN (dBFS)

SINAD

-5-10-15-20-25-30-35-40-45-50

MAX12528 toc08

MAX12528 toc11

SNR, SINAD vs. ANALOG INPUT FREQUENCY

= 80MHz, AIN = -0.5dBFS)

(f

CLK

72

70

68

66

64

62

60

58

SNR, SINAD (dB)

56

54

52

50

0 400

fIN (MHz)

SINAD

-THD, SFDR vs. ANALOG INPUT AMPLITUDE
= 80MHz, fIN = 70MHz)

(f

90

80

70

60

50

-THD, SFDR (dB)
40

30

20

CLK

SFDR

-THD

-55 0
AIN (dBFS)

SNR

MAX12528 toc09

350300200 250100 15050

MAX12528 toc12

-5-10-15-20-25-30-35-40-45-50

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, AIN= -0.5dBFS,
DIFFCLK/SECLK = OV

DD

, PD = GND, G/T = GND, f

CLK

= 80MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

75

65

55

45

SNR, SINAD (dB)

35

25

15

-55 0

= 80MHz, fIN = 175MHz)

(f

CLK

SNR

SINAD

AIN (dBFS)

-THD, SFDR vs. CLOCK SPEED
= 70MHz, AIN = -0.5dBFS)

(f

90

85

80

75

70

65

-THD, SFDR (dBc)
60

55

50

IN

SFDR

-THD

10 80

f

(MHz)

CLK

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

= 70MHz)

(f

75

70

65

60

SNR, SINAD (dB)

55

50

3.0 3.6

IN

SNR

SINAD

VDD (V)

MAX12528 toc13

-THD, SFDR (dBc)

-5-10-15-20-25-30-35-40-45-50

MAX12528 toc16

SNR, SINAD (dB)

706050403020

MAX12528 toc19

-THD, SFDR (dBc)

3.53.43.33.23.1

-THD, SFDR vs. ANALOG INPUT AMPLITUDE

90

80

70

60

50

40

30

20

-55 0

= 80MHz, fIN = 175MHz)

(f

CLK

SFDR

-THD

AIN (dBFS)

-5-10-15-20-25-30-35-40-45-50

SNR, SINAD vs. CLOCK SPEED

75

70

65

60

55

50

10 80

f

CLK

SNR

SINAD

706050403020

(MHz)

= 175MHz, AIN = -0.5dBFS)

(f

IN

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
= 70MHz)

(f

90

85

80

75

70

65

60

55

50

3.0 3.6

IN

SFDR

-THD

3.53.43.33.23.1

VDD (V)

MAX12528 toc14

SNR, SINAD (dB)

MAX12528 toc17

-THD, SFDR (dBc)

MAX12528 toc20

SNR, SINAD (dB)

SNR, SINAD vs. CLOCK SPEED

= 70MHz, AIN = -0.5dBFS)

(f

75

70

65

60

55

50

IN

SNR

SINAD

10 80

-THD, SFDR vs. CLOCK SPEED
= 175MHz, AIN = -0.5dBFS)

(f

IN

90

85

80

75

70

65

60

55

50

10 80

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

75

70

65

60

55

50

3.0 3.6

SFDR

-THD

(f

f

(MHz)

CLK

f

(MHz)

CLK

= 175MHz)

IN

SNR

SINAD

VDD (V)

706050403020

706050403020

3.53.43.33.23.1

MAX12528 toc15

MAX12528 toc18

MAX12528 toc21

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, AIN= -0.5dBFS,
DIFFCLK/SECLK = OV

DD

, PD = GND, G/T = GND, f

CLK

= 80MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE

90

85

80

75

70

65

-THD, SFDR (dBc)

60

55

50

3.0 3.6

= 175MHz)

(f

IN

SFDR

-THD

VDD (V)

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

= 175MHz)

(f

75

70

65

60

SNR, SINAD (dB)

55

50

1.5 3.6

IN

SNR

SINAD

OVDD (V)

MAX12528 toc22

SNR, SINAD (dB)

3.53.43.33.23.1

MAX12528 toc25

-THD, SFDR (dBc)

3.33.02.72.42.11.8

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

= 70MHz)

(f

75

70

65

60

55

50

1.5 3.6

IN

SNR

SINAD

3.33.02.72.42.11.8

OVDD (V)

-THD, SFDR vs. DIGITAL POWER SUPPLY
= 175MHz)

(f

80

76

72

68

64

60

1.5 3.6

IN

SFDR

-THD

3.33.02.72.42.11.8

OVDD (V)

MAX12528 toc23

MAX12528 toc26

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE

90

85

80

75

70

65

-THD, SFDR (dBc)
60

55

50

1.5 3.6

P

, I

DISS

1000

900

800

700

600

(mW, mA)

VDD

500

, I

DISS

400

P

300

200

100

(ANALOG) vs. ANALOG SUPPLY VOLTAGE

VDD

3.0 3.6

P

DISS

= 70MHz)

(f

IN

OVDD (V)

= 175MHz)

(f

IN

(ANALOG)

I

VDD

VDD (V)

SFDR

-THD

MAX12528 toc24

3.33.02.72.42.11.8

MAX12528 toc27

3.53.43.33.23.1

P

, I

DISS

100

(mW, mA)

OVDD

, I

DISS

P

(DIGITAL) vs. DIGITAL SUPPLY VOLTAGE

OVDD

90

80

70

60

50

40

30

20

10

0

1.5 3.6

= 175MHz)

(f

IN

P

DISS

I

OVDD (V)

(DIGITAL)

OVDD

SNR, SINAD vs. CLOCK DUTY CYCLE

= 70MHz, AIN = -0.5dBFS)

(f

75

MAX12528 toc28

3.33.01.8 2.1 2.4 2.7

70

65

60

SNR, SINAD (dB)

55

50

IN

SNR

SINAD

SINGLE-ENDED CLOCK DRIVE

25 75

CLOCK DUTY CYCLE (%)

65554535

MAX12528 toc29

-THD, SFDR vs. CLOCK DUTY CYCLE
= 70MHz, AIN = -0.5dBFS)

(f

90

85

80

75

-THD, SFDR (dBc)

70

65

60

IN

SINGLE-ENDED CLOCK DRIVE

25 75

CLOCK DUTY CYCLE (%)

MAX12528 toc30

SFDR

-THD

65554535

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 11

Typical Operating Characteristics (continued)

(VDD= 3.3V, OVDD= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈ 5pF at digital outputs, AIN= -0.5dBFS,
DIFFCLK/SECLK = OV

DD

, PD = GND, G/T = GND, f

CLK

= 80MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)

SNR, SINAD (dB)

-0.5

GAIN ERROR (%FSR)

-1.0

-1.5

-2.0

SNR, SINAD vs. TEMPERATURE

= 175MHz, AIN = -0.5dBFS)

(f

IN

72

70

68

66

64

62

60

-40 85

SNR

SINAD

TEMPERATURE (°C)

GAIN ERROR vs. TEMPERATURE

= 2.048V)

(V

2.0

1.5

1.0

0.5

0

-40 -15 10 35 60 85

REFIN

TEMPERATURE (°C)

MAX12528 toc31

-THD, SFDR (dBc)

603510-15

-THD, SFDR vs. TEMPERATURE
= 175MHz, AIN = -0.5dBFS)

(f

IN

90

85

80

SFDR

75

70

65

60

-40 85

-THD

603510-15

TEMPERATURE (°C)

MAX12528 toc32

OFFSET ERROR vs. TEMPERATURE

0.20

MAX12528 toc33

0.15

0.10

0.05

0

-0.05

OFFSET ERROR (%FSR)

-0.10

-0.15

-0.20

-40 -15 10 35 60 85

TEMPERATURE (°C)

MAX12528 toc34

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

12 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1, 4, 5, 9,

13, 14, 17

2 INAP Channel A Positive Analog Input

3 INAN Channel A Negative Analog Input

6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.

7 REFAP

8 REFAN

10 REFBN

11 REFBP

12 COMB Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.

15 INBN Channel B Negative Analog Input

16 INBP Channel B Positive Analog Input

18

19 CLKN

20 CLKP

21 DIV2 Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.

22 DIV4 Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.

23–26, 61,

62, 63

27, 43, 60 OV

28, 29, 45,

46

GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together.

DIFFCLK/

SECLK

V

DD

DD

N.C. No Connection

Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V
REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the

same side of the PC board.

Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (V
REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the

same side of the PC board.

Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (V
REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the

same side of the PC board.

Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (V
REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the

same side of the PC board.

Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
input drives.
DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
DIFFCLK/SECLK = OV

Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the
clock signal to CLKP and connect CLKN to GND.
Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the single-ended clock signal to CLKP and connect CLKN to GND.

Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥10µF and 0.1µF. Connect all V

Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥10µF and 0.1µF.

: Selects differential clock input drive.

DD

pins to the same potential.

DD

- V

REFAP

- V

REFAP

REFBP

- V

REFBP

), connect a differential

DD

), connect a differential

DD

REFAN

- V

REFBN

REFBN

REFAN

). Bypass

). Bypass

). Bypass

). Bypass

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 13

Pin Description (continued)

PIN NAME FUNCTION

30 D0B Channel B CMOS Digital Output, Bit 0 (LSB)

31 D1B Channel B CMOS Digital Output, Bit 1

32 D2B Channel B CMOS Digital Output, Bit 2

33 D3B Channel B CMOS Digital Output, Bit 3

34 D4B Channel B CMOS Digital Output, Bit 4

35 D5B Channel B CMOS Digital Output, Bit 5

36 D6B Channel B CMOS Digital Output, Bit 6

37 D7B Channel B CMOS Digital Output, Bit 7

38 D8B Channel B CMOS Digital Output, Bit 8

39 D9B Channel B CMOS Digital Output, Bit 9

40 D10B Channel B CMOS Digital Output, Bit 10

41 D11B Channel B CMOS Digital Output, Bit 11 (MSB)

Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog

42 DORB

44 DAV

47 D0A Channel A CMOS Digital Output, Bit 0 (LSB)

48 D1A Channel A CMOS Digital Output, Bit 1

49 D2A Channel A CMOS Digital Output, Bit 2

50 D3A Channel A CMOS Digital Output, Bit 3

51 D4A Channel A CMOS Digital Output, Bit 4

52 D5A Channel A CMOS Digital Output, Bit 5

53 D6A Channel A CMOS Digital Output, Bit 6

54 D7A Channel A CMOS Digital Output, Bit 7

55 D8A Channel A CMOS Digital Output, Bit 8

56 D9A Channel A CMOS Digital Output, Bit 9

57 D10A Channel A CMOS Digital Output, Bit 10

58 D11A Channel A CMOS Digital Output, Bit 11 (MSB)

59 DORA

64 G/T

65 PD

input voltage is out of range.
DORB = 1: Digital outputs exceed full-scale range.
DORB = 0: Digital outputs are within full-scale range.

Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.
The MAX12528 evaluation kit (MAX12528 EV kit) utilizes DAV to latch data into any external back-end
digital logic.

Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog
input voltage is out of range.
DORA = 1: Digital outputs exceed full-scale range.
DORA = 0: Digital outputs are within full-scale range.

Output Format Select Digital Input.
G/T = GND: Two’s-complement output format selected.
G/T = OV

Power-Down Digital Input.
PD = GND: ADCs are fully operational.
PD = OV

: Gray-code output format selected.

DD

: ADCs are powered down.

DD

MAX12528

Detailed Description

The MAX12528 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high­speed conversion while minimizing power consump­tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.

Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out­put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12528 functional diagram.

Dual, 80Msps, 12-Bit, IF/Baseband ADC

14 ______________________________________________________________________________________

Pin Description (continued)

Figure 1. Pipeline Architecture—Stage Blocks

PIN NAME FUNCTION

66 SHREF

67 REFOUT

68 REFIN

—EP

Shared Reference Digital Input.
SHREF = V
SHREF = GND: Shared reference disabled.
When sharing the reference, externally connect REFAP and REFBP together to ensure that V
equals V
ensure that V
Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.
For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from
REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor.
For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥0.1µF
capacitor.
Single-Ended Reference Analog Input. For internal reference and buffered external reference operation,
apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor.
Within its specified operating voltage, REFIN has a >50MΩ input impedance, and the differential
reference voltage (V
operation, connect REFIN to GND. In this mode REF_P, REF_N, and COM_ are high-impedance inputs
that accept the external reference voltages.

Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified
dynamic performance.

: Shared reference enabled.

DD

. Similarly, when sharing the reference, externally connect REFAN to REFBN together to

REFBP

MAX12528

REFAN

= V

REF_P

REFBN

- V

.

) is generated from REFIN. For unbuffered external reference

REF_N

FLASH

ADC

+

Σ

DAC

x2

−

REFAP

IN_P

IN_N

STAGE 1 STAGE 9

STAGE 2

DIGITAL ERROR CORRECTION

D0_ THROUGH D11_

STAGE 10

END OF PIPELINE

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 15

Figure 2. Functional Diagram

INAP

INAN

REFAP
COMA
REFAN

REFIN

REFOUT

SHREF

REFBP
COMB
REFBN

INBP

INBN

12-BIT

PIPELINE

ADC

CHANNEL A
REFERENCE

SYSTEM

CHANNEL B
REFERENCE

SYSTEM

12-BIT

PIPELINE

ADC

DIGITAL

ERROR

CORRECTION

MAX12528

INTERNAL

REFERENCE

GENERATOR

DIGITAL

ERROR

CORRECTION

CLOCK

DATA

FORMAT

DATA

FORMAT

OUTPUT
DRIVERS

OUTPUT
DRIVERS

D0A TO D11A

DORA

G/T

DAV

OV

DD

D0B TO D11B

DORB

DIFFCLK/SECLK

CLKP

CLKN

DIV2
DIV4

CLOCK

DIVIDER

DUTY-CYCLE

EQUALIZER

CLOCK

CLOCK

POWER

CONTROL

AND

BIAS CIRCUITS

V

DD

PD

GND

MAX12528

Analog Inputs and Input Track-and-Hold

(T/H) Amplifier

Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a VDD/ 2 common-mode input voltage.

The MAX12528 sampling clock controls the switched­capacitor input T/H architecture (Figure 3) allowing the
analog input signals to be stored as charge on the
sampling capacitors. These switches are closed (track
mode) when the sampling clock is high and open (hold
mode) when the sampling clock is low (Figure 4). The
analog input signal source must be able to provide the
dynamic currents necessary to charge and discharge
the sampling capacitors. To avoid signal degradation,
these capacitors must be charged to one-half LSB
accuracy within one-half of a clock cycle. The analog
input of the MAX12528 supports differential or single­ended input drive. For optimum performance with dif­ferential inputs, balance the input impedance of IN_P
and IN_N and set the common-mode voltage to mid­supply (VDD/ 2). The MAX12528 provides the optimum
common-mode voltage of VDD/ 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 9, 10, and 11.

Reference Output

An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the

MAX12528. The power-down logic input (PD) enables
and disables the reference circuit. REFOUT has approxi­mately 17kΩ to GND when the MAX12528 is powered
down. The reference circuit requires 10ms to power up
and settle to its final value when power is applied to the
MAX12528 or when PD transitions from high to low.

The internal bandgap reference produces a buffered
reference voltage of 2.048V ±1% at the REFOUT pin
with a ±50ppm/°C temperature coefficient. Connect an
external ≥0.1µF bypass capacitor from REFOUT to
GND for stability. REFOUT sources up to 1mA and
sinks up to 0.1mA for external circuits with a 35mV/mA
load regulation. Short-circuit protection limits I

REFOUT

to a 2.1mA source current when shorted to GND and a

0.24mA sink current when shorted to VDD. Similar to
REFOUT, REFIN should be bypassed with a 4.7µF
capacitor to GND.

Reference Configurations

The MAX12528 full-scale analog input range is ±2/3 x
V

REF

with a VDD/ 2 ±0.5V common-mode input range.

V

REF

is the voltage difference between REFAP (REFBP)
and REFAN (REFBN). The MAX12528 provides three
modes of reference operation. The voltage at REFIN
(V

REFIN

) selects the reference operation mode (Table 1).

Connect REFOUT to REFIN either with a direct short or
through a resistive divider to enter internal reference
mode. COM_, REF_P, and REF_N are low-impedance
outputs with V

COM_

= VDD/ 2, V

REFP

= VDD/ 2 + 3/8 x

V

REFIN

, and V

REF_N

= VDD/ 2 - 3/8 x V

REFIN

. Bypass
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.

Dual, 80Msps, 12-Bit, IF/Baseband ADC

16 ______________________________________________________________________________________

Table 1. Reference Modes

Figure 3. Internal T/H Circuit

V

BOND WIRE

INDUCTANCE

1.5nH

IN_P

BOND WIRE

INDUCTANCE

1.5nH

IN_N

SAMPLING

CLOCK

*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:

DD

MAX12528

x C

1

SAMPLE

*C

4.5pF

*C

4.5pF

SAMPLE

SAMPLE

C

PAR

2pF

V

DD

C

PAR

2pF

RIN =

f

CLK

V

REFIN

Internal Reference Mode.

35% V

REFOUT

to 100%

V

REFOUT

0.7V to 2.3V

<0.5V

REFIN is driven by REFOUT either through a
direct short or a resistive divider.
V

= VDD / 2

COM_

= VDD / 2 + 3/8 x V

V

REF_P

V

= VDD / 2 - 3/8 x V

REF_N

Buffered External Reference Mode.
An external 0.7V to 2.3V reference voltage is
applied to REFIN.
V

= VDD / 2

COM_

= VDD / 2 + 3/8 x V

V

REF_P

V

= VDD / 2 - 3/8 x V

REF_N

U nb uffer ed E xter nal Refer ence M od e.
RE F_P , RE F_N , and C O M _ ar e d r i ven b y
exter nal r efer ence sour ces. The ful l - scal e
anal og i np ut r ang e i s ± ( V

REFERENCE MODE

REFIN

REFIN

REFIN

REFIN

- V

R E F _P

R E F _N

) x 2/3.

Bypass REFIN and REFOUT to GND with a 0.1µF capac­itor. The REFIN input impedance is very large (>50MΩ).
When driving REFIN through a resistive divider, use
resistances ≥10kΩ to avoid loading REFOUT.

Buffered external reference mode is virtually identical to
the internal reference mode except that the reference
source is derived from an external reference and not the
MAX12528’s internal bandgap reference. In buffered
external reference mode, apply a stable reference volt­age source between 0.7V to 2.3V at REFIN. Pins COM_,
REF_P, and REF_N are low-impedance outputs with
V

COM_

= VDD/ 2, V

REF_P

= VDD/ 2 + 3/8 x V

REFIN

, and

V

REF_N

= VDD/ 2 - 3/8 x V

REFIN

. Bypass REF_P, REF_N,
and COM_ each with a 0.1µF capacitor to GND. Bypass
REF_P to REF_N with a 10µF capacitor.

Connect REFIN to GND to enter unbuffered external ref­erence mode. Connecting REFIN to GND deactivates
the on-chip reference buffers for COM_, REF_P, and
REF_N. With their buffers deactivated, COM_, REF_P,
and REF_N become high-impedance inputs and must
be driven with separate, external reference sources.
Drive V

COM_

to VDD/ 2 ±5%, and drive REF_P and

REF_N so V

COM_

= (V

REF_P_

+ V

REF_N_

) / 2. The analog

input range is ±(V

REF_P_

- V

REF_N

) x 2/3. Bypass
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.

For all reference modes, bypass REFOUT with a 0.1µF
and REFIN with a 4.7µF capacitor to GND.

The MAX12528 also features a shared reference mode,
in which the user can achieve better channel-to-chan­nel matching. When sharing the reference (SHREF =
VDD), externally connect REFAP and REFBP together to
ensure that V

REFAP

= V

REFBP

. Similarly, when sharing
the reference, externally connect REFAN to REFBN
together to ensure that V

REFAN

= V

REFBN

.

Connect SHREF to GND to disable the shared refer­ence mode of the MAX12528. In this independent refer­ence mode, a better channel-to-channel isolation is
achieved.

For detailed circuit suggestions and how to drive the
ADC in buffered/unbuffered external reference mode,
see the Applications Information section.

Clock Duty-Cycle Equalizer

The MAX12528 has an internal clock duty-cycle equaliz­er, which makes the converter insensitive to the duty
cycle of the signal applied to CLKP and CLKN. The con­verters allow clock duty-cycle variations from 25% to 75%
without negatively impacting the dynamic performance.

The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are

duty-cycle independent. Due to this DLL, the
MAX12528 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.

Clock Input and Clock Control Lines

The MAX12528 accepts both differential and single­ended clock inputs with a wide 25% to 75% input clock
duty cycle. For single-ended clock input operation,
connect DIFFCLK/SECLK and CLKN to GND. Apply an
external single-ended clock signal to CLKP. To reduce
clock jitter, the external single-ended clock must have
sharp falling edges. For differential clock input opera­tion, connect DIFFCLK/SECLK to OVDD. Apply an
external differential clock signal to CLKP and CLKN.
Consider the clock input as an analog input and route it
away from any other analog inputs and digital signal
lines. CLKP and CLKN enter high impedance when the
MAX12528 is powered down (Figure 4).

Low clock jitter is required for the specified SNR perfor­mance of the MAX12528. The analog inputs are sam­pled on the falling (rising) edge of CLKP (CLKN),
requiring this edge to have the lowest possible jitter.
Jitter limits the maximum SNR performance of any ADC
according to the following relationship:

where fINrepresents the analog input frequency and t

J

is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For instance,
assuming that clock jitter is the only noise source, to
obtain the specified 69.8dB of SNR with an input fre­quency of 175MHz the system must have less than

0.29ps of clock jitter. However, in reality there are other
noise sources such as thermal noise and quantization
noise that contribute to the system noise requiring the
clock jitter to be less than 0.14ps to obtain the speci­fied 69.8dB of SNR at 175MHz.

Clock-Divider Control Inputs (DIV2, DIV4)

The MAX12528 features three different modes of sam­pling/clock operation (see Table 2). Pulling both control
lines low, the clock-divider function is disabled and the
converters sample at full clock speed. Pulling DIV4 low
and DIV2 high enables the divide-by-two feature, which
sets the sampling speed to one-half the selected clock
frequency. In divide-by-four mode, the converter sam­pling speed is set to one-fourth the clock speed of the
MAX12528. Divide-by-four mode is achieved by applying
a high level to DIV4 and a low level to DIV2. The option to
select either one-half or one-fourth of the clock speed for

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 17

SNR

20

log

=×

⎛
⎜

2 π

⎝

1

ft

×× ×

IN J

⎞
⎟

⎠

MAX12528

sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.

System Timing Requirements

Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sam­pled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.

The DAV indicator is synchronized with the digital out­put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-

cuitry can be latched with the rising edge of the con­version clock (CLKP - CLKN).

Data-Valid Output

DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12528 output data changes on the
falling edge of DAV, and DAV rises once the output
data is valid. The falling edge of DAV is synchronized
to have a 5.4ns delay from the falling edge of the input
clock. Output data at D0A/B–D11A/B and DORA/B are
valid from 7ns before the rising edge of DAV to 7ns
after the rising edge of DAV.

DAV enters high impedance when the MAX12528 is
powered down (PD = OVDD). DAV enters its high­impedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.

DAV is capable of sinking and sourcing 600µA and has
three times the driving capabilities of D0A/B–D11A/B
and DORA/B. DAV is typically used to latch the
MAX12528 output data into an external digital back-end
circuit. Keep the capacitive load on DAV as low as possi­ble (<15pF) to avoid large digital currents feeding back
into the analog portion of the MAX12528, thereby
degrading its dynamic performance. Buffering DAV

Dual, 80Msps, 12-Bit, IF/Baseband ADC

18 ______________________________________________________________________________________

Figure 4. Simplified Clock Input Circuit

Table 2. Clock-Divider Control Inputs

Figure 5. System Timing Diagram

V

DD

S

CLKP

CLKN

GND

S

1L

1H

10kΩ

10kΩ

S

2H

10kΩ

SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN MAKING

S

2L

CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S
SINGLE-ENDED CLOCK MODE.

10kΩ

MAX12528

DUTY-CYCLE

EQUALIZER

ARE OPEN IN

2_

(V

(V

REF_P

REF_N

- V

REF_N

- V

REF_P

DAV

D0_–D11_

DOR

DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)

) x 2/3

N - 3

N - 2

) x 2/3

CLKN

CLKP

t

DAV

N

N - 1

t

AD

N + 1

N + 3

N +2

t

CL

t

SETUP

8.0 CLOCK-CYCLE DATA LATENCY

N + 4

t

N + 5

CH

DIV4 DIV2 FUNCTION

00

01

10

Clock Divider Disabled
f

SAMPLE

Divide-by-Two Clock Divider
f

SAMPLE

Divide-by-Four Clock Divider
f

SAMPLE

1 1 Not Allowed

N + 6

t

HOLD

N + 7

N + 9

N + 8

N N + 1 N + 2 N + 3 N + 5 N + 6 N + 7N - 1N - 2N - 3 N + 9N + 8

N + 4

t

SETUP

= f

CLK

= f

/ 2

CLK

= f

/ 4

CLK

t

HOLD

externally isolates it from heavy capacitive loads. Refer
to the MAX12557 EV kit schematic for recommendations
of how to drive the DAV signal through an external buffer.

Data Out-of-Range Indicator

The DORA and DORB digital outputs indicate when the
analog input voltage is out of range. When DOR_ is high,
the analog input is out of range. When DOR_ is low, the
analog input is within range. The valid differential input
range is from (V

REF_P

- V

REF_N

) x 2/3 to (V

REF_N

-

V

REF_P

) x 2/3. Signals outside of this valid differential

range cause DOR_ to assert high as shown in Table 1.

DOR is synchronized with DAV and transitions along
with the output data D11–D0. There is an 8 clock-cycle
latency in the DOR function as is with the output data
(Figure 5). DOR_ is high impedance when the
MAX12528 is in power-down (PD = high). DOR_ enters
a high-impedance state within 10ns after the rising edge
of PD and becomes active 10ns after PD’s falling edge.

Digital Output Data and Output Format Selection

The MAX12528 provides two 12-bit, parallel, tri-state
output buses. D0A/B–D11A/B and DORA/B update on

the falling edge of DAV and are valid on the rising edge
of DAV.

The MAX12528 output data format is either Gray code
or two’s complement depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is set to two’s com­plement. See Figure 8 for a binary-to-Gray and Gray-to­binary code conversion example.

The following equations, Table 3, Figure 6, and Figure 7
define the relationship between the digital output and
the analog input.

Gray Code (G/T = 1):

V

IN_P

- V

IN_N

= 2/3 x (V

REF_P

- V

REF_N

) x 2 x

(CODE10- 2048) / 4096

Two’s Complement (G/T = 0):

V

IN_P

- V

IN_N

= 2/3 x (V

REF_P

- V

REF_N

) x 2 x

CODE10/ 4096

where CODE10is the decimal equivalent of the digital
output code as shown in Table 3.

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 19

Table 3. Output Codes vs. Input Voltage

BINARY
D11A–D0A
D11B–D0B

1000 0000 0000 1 0x800 [phone] 1111 1 0x7FF +2047

1000 0000 0000 0 0x800 [phone] 1111 0 0x7FF +2047 +1.0235V

1000 0000 0001 0 0x801 [phone] 1110 0 0x7FE +2046 +1.0230V

GRAY-CODE OUTPUT CODE

(G/T = 1)

H EXA D ECIM A L

EQUIVALENT

DOR

OF
D11A–D0A
D11B–D0B

DECIMAL

EQUIVALENT

OF
D11A–D0A
D11B–D0B

(CODE

10

)

TWO’S COMPLEMENT OUTPUT CODE

(G/T = 0)

HEXADECIMAL

BINARY
D11A–D0A
D11B–D0B

DOR

EQUIVALENT

OF
D11A–D0A
D11B–D0B

DECIMAL

EQUIVALENT

OF
D11A–D0A
D11B–D0B

(CODE10)

- V

V

IN_P

V

= 2.418V

REF_P

V

= 0.882V

REF_N

>+1.0235V

(DATA OUT OF

RANGE)

IN_N

1100 0000 0011 0 0xC03 [phone] 0010 0 0x002 +2 +0.0010V

1100 0000 0001 0 0xC01 [phone] 0001 0 0x001 +1 +0.0005V

1100 0000 0000 0 0xC00 [phone] 0000 0 0x000 0 +0.0000V

0100 0000 0000 0 0x400 [phone] 1111 0 0xFFF -1 -0.0005V

0100 0000 0001 0 0x401 [phone] 1110 0 0xFFE -2 -0.0010V

0000 0000 0001 0 0x001 [phone]x801 -2047 -1.0235V

0000 0000 0000 0 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V

<-1.0240V

0000 0000 0000 1 0x000 0 1000 0000 0000 1 0x800 -2048

(DATA OUT OF

RANGE)

MAX12528

The digital outputs D0A/B–D11A/B are high impedance
when the MAX12528 is in power-down (PD = 1) mode.
D0A/B–D11A/B enter this state 10ns after the rising
edge of PD and become active again 10ns after PD
transitions low.

Keep the capacitive load on the MAX12528 digital out­puts D0A/B–D11A/B as low as possible (<15pF) to
avoid large digital currents feeding back into the ana­log portion of the MAX12528 and degrading its dynam­ic performance. Adding external digital buffers on the
digital outputs helps isolate the MAX12528 from heavy
capacitive loads. To improve the dynamic performance
of the MAX12528, add 220Ω resistors in series with the
digital outputs close to the MAX12528. Refer to the
MAX12557 EV kit schematic for guidelines of how to
drive the digital outputs through 220Ω series resistors
and external digital output buffers.

Power-Down Input

The MAX12528 has two power modes that are con­trolled with a power-down digital input (PD). With PD
low, the MAX12528 is in its normal operating mode.
With PD high, the MAX12528 is in power-down mode.

The power-down mode allows the MAX12528 to effi­ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12528 parallel output bus goes high-impedance in
power-down mode, allowing other devices on the bus
to be accessed.

In power-down mode all internal circuits are off, the
analog supply current reduces to less than 100µA, and
the digital supply current reduces to less than 1µA. The
following list shows the state of the analog inputs and
digital outputs in power-down mode:

1) INAP/B and INAN/B analog inputs are disconnect­ed from the internal input amplifier (Figure 3).

2) REFOUT has approximately 17kΩ to GND.

3) REFAP/B, COMA/B, and REFAN/B enter a high­impedance state with respect to VDDand GND, but
there is an internal 4kΩ resistor between REFAP/B
and COMA/B, as well as an internal 4kΩ resistor
between REFAN/B and COMA/B.

4) D0A–D11A, D0B–D11B, DORA, and DORB enter a
high-impedance state.

5) DAV enters a high-impedance state.

6) CLKP and CLKN clock inputs enter a high-imped­ance state (Figure 4).

The wake-up time from power-down mode is dominated
by the time required to charge the capacitors at REF_P,
REF_N, and COM. In internal reference mode and
buffered external reference mode the wake-up time is
typically 10ms. When operating in the unbuffered exter­nal reference mode the wake-up time is dependent on
the external reference drivers.

Dual, 80Msps, 12-Bit, IF/Baseband ADC

20 ______________________________________________________________________________________

Figure 6. Two’s-Complement Transfer Function (G/T= 0)

Figure 7. Gray-Code Transfer Function (G/T= 1)

1 LSB = 4/3 x (V

2/3 x (V

0x7FF
0x7FE

0x7FD

0x001
0x000
0xFFF

0x803

TWO'S-COMPLEMENT OUTPUT CODE (LSB)

0x802
0x801
0x800

- V

REFP

REFN

-2045 +2047+2045-1 0 +1-2047

DIFFERENTIAL INPUT VOLTAGE (LSB)

- V

REFP

REFN

) 2/3 x (V

) / 4096

REFP

- V

REFN

1 LSB = 4/3 x (V

)

0x800
0x801
0x803

0xC01
0xC00
0xC00

GRAY OUTPUT CODE (LSB)

0x002
0x003
0x001
0x000

2/3 x (V

- V

REFP

REFN

-2045 +2047+2045-1 0 +1-2047

DIFFERENTIAL INPUT VOLTAGE (LSB)

- V

REFP

REFN

) 2/3 x (V

) / 4096

REFP

- V

REFN

)

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 21

Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion

BINARY-TO-GRAY CODE CONVERSION

1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.

D11 D7 D3 D0

0111 0100 1100 BINARY

2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:

GRAYX = BINARYX +BINARY

+

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:

GRAY

= BINARY10BINARY

10

+

GRAY10 = 1 0

GRAY

= 1

10

D11 D7 D3 D0

+

0 111 0100 1100 BINARY

1

3) REPEAT STEP 2 UNTIL COMPLETE:

GRAY

= BINARY9BINARY

9

+

GRAY9 = 1 1

= 0

GRAY

9

X + 1

+

11

+

10

BIT POSITION

GRAY CODE0

BIT POSITION

GRAY CODE0

GRAY-TO-BINARY CODE CONVERSION

1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.

D11 D7 D3 D0

0 BINARY

2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:

BINARYX = BINARY

+

WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:

= BINARY11GRAY

BINARY

10

BINARY10 = 0 1

BINARY

= 1

10

D11 D7 D3 D0

0 100 1110 1010

+

0

1

3) REPEAT STEP 2 UNTIL COMPLETE:

BINARY

= BINARY10GRAY

9

BINARY9 = 1 0

= 1

BINARY

9

+

GRAY

X+1

+

+

X

+

10

+

9

BIT POSITION

GRAY CODE0100 11 011010

BIT POSITION

GRAY CODE

BINARY

D11 D7 D3 D0

+

01 11 0100 1100 BINARY

10

4) THE FINAL GRAY-CODE CONVERSION IS:

D11 D7 D3 D0

0111 0100 1100 BINARY

1001101 1010

FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY
CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT
FORMAT OF THE MAX12528 IS TWO'S-COMPLEMENT BINARY,
HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE
MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT.

BIT POSITION

GRAY CODE0

BIT POSITION

GRAY CODE0

EXCLUSIVE OR TRUTH TABLE

AB Y=AB

00
01
10
11

D11 D7 D3 D0

01 00 1110 1010

+

11

0

4) THE FINAL BINARY CONVERSION IS:

D11 D7 D3 D0

0100 1110 1010

0111 0100 1100

+

0
1
1
0

BIT POSITION

GRAY CODE

BINARY

BIT POSITION

GRAY CODE

BINARY

MAX12528

Applications Information

Using Transformer Coupling

In general, the MAX12528 provides better SFDR and
THD with fully differential input signals than single­ended input drive, especially for input frequencies
above 125MHz. In differential input mode, even-order
harmonics are lower as both inputs are balanced, and
each of the ADC inputs only requires half the signal
swing compared to single-ended input mode.

An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12528
for optimum performance. Connecting the center tap of
the transformer to COM provides a V

DD

/ 2 DC level
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the

overall distortion. The configuration of Figure 9 is good
for frequencies up to Nyquist (f

CLK

/ 2).

The circuit of Figure 10 converts a single-ended input
signal to fully differential just as Figure 9. However,
Figure 10 utilizes an additional transformer to improve
the common-mode rejection allowing high-frequency
signals beyond the Nyquist frequency. A set of 75Ω
and 113Ω termination resistors provide an equivalent
50Ω termination to the signal source. The second set of
termination resistors connects to COM_ providing the
correct input common-mode voltage. Two 0Ω resistors
in series with the analog inputs allow high IF input fre­quencies. These 0Ω resistors can be replaced with low­value resistors to limit the input bandwidth.

Single-Ended AC-Coupled Input Signal

Figure 11 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.

Dual, 80Msps, 12-Bit, IF/Baseband ADC

22 ______________________________________________________________________________________

Figure 9. Transformer-Coupled Input Drive for Input Frequencies
Up to Nyquist

Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist

Figure 11. Single-Ended, AC-Coupled Input Drive

24.9Ω

5.6pF

0.1µF

1

V

IN

N.C.

MINICIRCUITS

6

T1

5

2

24.9Ω

0.1µF

5.6pF

3

4

TT1-6

OR

T1-1T

IN_P

MAX12528

COM_

IN_N

V

IN

MAX4108

100Ω

100Ω

0.1µF

0Ω

24.9Ω

24.9Ω

IN_P

5.6pF

MAX12528

COM_

0.1µF

IN_N

5.6pF

0Ω*

0.1µF

1

V

IN

N.C.

6

T1

5

2

3

4

MINICIRCUITS

ADT1-1WT

N.C.

75Ω
1%

75Ω
1%

*0Ω RESISTORS CAN BE REPLACED WITH
LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.

N.C.

MINICIRCUITS

1

T2

5

3

ADT1-1WT

6

2

N.C.

4

113Ω

0.5%

113Ω

0.5%

5.6pF

0.1µF

0Ω*

5.6pF

IN_P

MAX12528

COM_

IN_N

Buffered External Reference Drives

Multiple ADCs

The buffered external reference mode allows for more
control over the MAX12528 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is >50MΩ.

Figure 12 shows the MAX6029 precision 2.048V bandgap
reference used as a common reference for multiple con­verters. The 2.048V output of the MAX6029 passes
through a single-pole 10Hz LP filter to the MAX4230.

The MAX4250 buffers the 2.048V reference and pro­vides additional 10Hz LP filtering before its output is
applied to the REFIN input of the MAX12528.

Unbuffered External Reference Drives

Multiple ADCs

The unbuffered external reference mode allows for pre­cise control over the MAX12528 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal reference,

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 23

Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference

3.3V

0.1µF

1

16.2kΩ

5

MAX6029

(EUK21)

2

NOTE: ONE FRONT-END REFERENCE CIRCUIT IS
CAPABLE OF SOURCING UP TO 15mA AND
SINKING UP TO 30mA OF OUTPUT CURRENT.

1µF

0.1µF

V

DD

GND

V

REF_P

REF_N

COM_

0.1µF

DD

REF_P

2.048V

0.1µF

3

4

MAX4230

5

1

2

47Ω

1.47kΩ

300µF
6V

0.1µF

REFIN

MAX12528

REFOUT

REFIN

MAX12528

10µF

10µF

2.2µF

0.1µF

0.1µF

0.1µF

0.1µF

3.3V

2.2µF

0.1µF

0.1µF

REFOUT

0.1µF

GND

REF_N

0.1µF

COM_

0.1µF

MAX12528

allowing REF_P, REF_N, and COM_ to be driven directly
by a set of external reference sources.

Figure 13 uses a MAX6029 precision 3.000V bandgap
reference as a common reference for multiple convert­ers. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz LP filter. Three
MAX4230 amplifiers buffer taps along this resistor
chain providing 2.413V, 1.647V, and 0.880V to the
MAX12528 REF_P, REF_N, and COM_ reference
inputs. The feedback around the MAX4230 op amps
provides additional 10Hz LP filtering. Reference volt­ages 2.413V and 0.880V set the full-scale analog input

range for the converter to ±1.022V (±[V

REF_P

- V

REF_N

]

x 2/3).

Note that one single power supply for all active circuit
components removes any concern regarding power­supply sequencing when powering up or down.

Grounding, Bypassing, and

Board Layout

The MAX12528 requires high-speed board layout
design techniques. Refer to the MAX12528 EV kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer­ably on the same side as the ADC, using surface-

Dual, 80Msps, 12-Bit, IF/Baseband ADC

24 ______________________________________________________________________________________

Figure 13. External Unbuffered Reference Driving Multiple ADCs

3.3V

0.1µF

1

MAX6029

(EUK30)

2

5

0.47µF

3V

20kΩ
1%

20kΩ
1%

52.3kΩ
1%

52.3kΩ
1%

20kΩ
1%

20kΩ
1%

20kΩ
1%

0.1µF

10µF

0.1µF

1

47Ω

10µF

10µF

10µF

4

6V

1.47kΩ

47Ω

4

6V

1.47kΩ

47Ω

4

6V

1.47kΩ

MAX4230

3

1

MAX4230

3

1

MAX4230

3

2.413V

0.1µF

330µF
6V

1.647V

330µF
6V

0.880V

330µF
6V

0.1µF

0.1µF

0.1µF

0.1µF

10µF

0.1µF

REF_P

REF_N

COM_

3.3V

REF_P

REF_N

COM_

V

DD

MAX12528

GND

V

DD

MAX12528

GND

0.1µF

REFOUT

REFIN

0.1µF

REFOUT

REFIN

2.2µF

0.1µF

2.2µF

0.1µF

mount devices for minimum inductance. Bypass VDDto
GND with a 220µF ceramic capacitor in parallel with at
least one 10µF, one 4.7µF, and one 0.1µF ceramic
capacitor. Bypass OVDDto GND with a 220µF ceramic
capacitor in parallel with at least one 10µF, one 4.7µF,
and one 0.1µF ceramic capacitor. High-frequency
bypassing/decoupling capacitors should be located as
close as possible to the converter supply pins.

Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All grounds
and the exposed backside paddle of the MAX12528
package (package code: T6800-2) must be connected
to the same ground plane. The MAX12528 relies on the
exposed backside paddle connection for a low-induc­tance ground connection. Isolate the ground plane
from any noisy digital system ground planes such as a
DSP or output buffer ground.

Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.

Ensure that the differential, analog input network layout
is symmetric and that all parasitic components are bal­anced equally. Refer to the MAX12528 EV kit data
sheet for an example of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX12528, this
straight line is between the endpoints of the transfer
function, once offset and gain errors have been nulli­fied. INL deviations are measured at every step of the
transfer function and the worst-case deviation is report­ed in the Electrical Characteristics table.

Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX12528, DNL
deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally, the midscale
MAX12528 transition occurs at 0.5 LSB above mid­scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope of
the ideal transfer function. The slope of the actual trans­fer function is measured between two data points: posi­tive full scale and negative full scale. Ideally, the positive
full-scale MAX12528 transition occurs at 1.5 LSBs below
positive full scale, and the negative full-scale transition
occurs at 0.5 LSB above negative full scale. The gain
error is the difference of the measured transition points
minus the difference of the ideal transition points.

Small-Signal Noise Floor (SSNF)

SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter,
a small signal is defined as a single tone with an ampli­tude of -35dBFS. This parameter captures the thermal
and quantization noise characteristics of the data con­verter and can be used to help calculate the overall
noise figure of a digital receiver signal path.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N bits):

SNR

[max]

= 6.02 × N + 1.76

In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec­tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2 through
HD7), and the DC offset.

SNR = 20 x log (SIGNAL

RMS

/ NOISE

RMS

)

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig­nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 25

MAX12528

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first six harmon­ics of the input signal to the fundamental itself. This is
expressed as:

where V1is the fundamental amplitude, and V2through
V7are the amplitudes of the 2nd- through 7th-order
harmonics (HD2 through HD7).

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next largest spurious
component, excluding DC offset.

Intermodulation Distortion (IMD)

IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones f

IN1

and f

IN2

. The
individual input tone levels are at -7dBFS. The inter­modulation products are as follows:

2nd-Order Intermodulation products (IM2):

f

IN1

= f

IN2

, f

IN2

- f

IN1

3rd-Order Intermodulation products (IM3):

2 x f

IN1

- f

IN2

, 2 x f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

,

2 x f

IN2

+ f

IN1

4th-Order Intermodulation products (IM4):

3 x f

IN1

- f

IN2

, 3 x f

IN2

- f

IN1

, 3 x f

IN1

+ f

IN2

,

3 x f

IN2

+ f

IN1

, 2 x f

IN1

- 2 x f

IN2

, 2 x f

IN1

+ 2 x f

IN2

,

2 x f

IN2

- 2 x f

IN1

5th-Order Intermodulation products (IM5):

3 x f

IN1

- 2 x f

IN2

, 3 x f

IN2

- 2 x f

IN1

, 3 x f

IN1

+ 2 x f

IN2

,

3 x f

IN2

+ 2 x f

IN1

, 4 x f

IN1

- f

IN2

, 4 x f

IN2

- f

IN1

,

4 x f

IN1

+ f

IN2

, 4 x f

IN2

+ f

IN1

Note that the two-tone intermodulation distortion is mea­sured with respect to a single-carrier amplitude and not
the peak-to-average input power of both input tones.

3rd-Order Intermodulation (IM3)

IM3 is the total power of the 3rd-order intermodulation
product to the Nyquist frequency relative to the total
input power of the two input tones f

IN1

and f

IN2

. The
individual input tone levels are at -7dBFS. The 3rd­order intermodulation products are 2 x f

IN1

- f

IN2

, 2 x

f

IN2

- f

IN1

, 2 x f

IN1

+ f

IN2

, 2 x f

IN2

+ f

IN1

.

Aperture Jitter

Figure 14 shows the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 14).

Full-Power Bandwidth

A large -0.2dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full­power input bandwidth frequency.

Output Noise (n

OUT

)

The output noise (n

OUT

) parameter is similar to thermal
plus quantization noise and is an indication of the con­verter’s overall noise performance.

No fundamental input tone is used to test for n

OUT

.
IN_P, IN_N, and COM_ are connected together and
1024k data points are collected. n

OUT

is computed by
taking the RMS value of the collected data points after
the mean is removed.

Overdrive Recovery Time

Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12528 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%. The MAX12528 requires one
clock cycle to recover from an overdrive condition.

Crosstalk

Coupling onto one channel being driven by a
(-0.5dBFS) signal when the adjacent interfering channel
is driven by a full-scale signal. Measurement includes
all spurs resulting from both direct coupling and mixing
components.

Dual, 80Msps, 12-Bit, IF/Baseband ADC

26 ______________________________________________________________________________________

Figure 14. T/H Aperture Timing

THD

log

=×

20

⎛

2

2

2

2

VVVVVV

+++++

2

3

4

⎜
⎜
⎝

5

V

1

2

6

2

7

CLKN

CLKP

⎞
⎟

⎟
⎠

ANALOG

INPUT

SAMPLED

DATA

T/H

TRACKHOLD HOLD

t

AD

t

AJ

Gain Matching

Gain matching is a figure of merit that indicates how
well the gains between the two channels are matched
to each other. The same input signal is applied to both
channels and the maximum deviation in gain is report­ed (typically in dB) as gain matching.

Offset Matching

Like gain matching, offset matching is a figure of merit
that indicates how well the offsets between the two chan­nels are matched to each other. The same input signal is
applied to both channels and the maximum deviation in
offset is reported (typically in %FSR) as offset matching.

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

______________________________________________________________________________________ 27

Pin Configuration

TOP VIEW

D5A

D6A

D7A

D8A

D9A

D10A

D11A

DORA

OV

V

V

V

G/T

SHREF

REFOUT

REFIN 68

N.C.

DAV

OVDDDORB

D11B

D10B

D9B

D8B

D7B

GND

GND

INBN

D6B

INBP

3536

1716

D5B

GND

34 D4B

D3B

33

32

D2B

31 D1B

D0B

30

N.C.

29

28

N.C.

27

OV

DD

V

26

DD

25

V

DD

V

24

DD

V

23

DD

22

DIV4

21

DIV2

CLKP

20

19

CLKN

18

DIFFCLK/SECLK

D4A

51

52

53

54

55

56

57

58

59

60

DD

61

DD

62

DD

63

DD

64

65

PD

66

67

GND

INAP

N.C.

47

484950

EXPOSED PADDLE (GND)

654321098711211 151413

GND

GND

INAN

COMA

MAX12528

REFAP

REFAN

GND

4142434445 3738394046

REFBN

REFBP

COMB

D0A

D3A

D2A

D1A

THIN QFN

MAX12528

Dual, 80Msps, 12-Bit, IF/Baseband ADC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

68L QFN THIN.EPS

PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm

21-0142

1

C

2

PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm

21-0142

2

C

2