Maxim MAX1245BEPP, MAX1245BEAP, MAX1245BCPP, MAX1245AEPP, MAX1245AEAP Datasheet

...

19-1066; Rev 0; 6/96

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

________________General Description

The MAX1245 12-bit data-acquisition system combines an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and ultra-low power consumption. It operates from a single +2.375V to +3.3V supply, and its analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation.

The 4-wire serial interface directly connects to SPI™, QSPI™, and Microwire™ devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1245 works with an external reference, and uses either the internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions.

This device provides a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface powers up the MAX1245, and the quick turn-on time allows it to be shut down between conversions. This technique can cut supply current to under 10µA at reduced sampling rates.

The MAX1245 is available in a 20-pin DIP package and an SSOP that occupies 30% less area than an 8-pin DIP. For supply voltages from +2.7V to +5.25V, use the pincompatible MAX147.

________________________Applications

Portable Data Logging Medical Instruments Battery-Powered Instruments Data Acquisition

___________T ypical Operating Circuit

+2.5V

+2.048V

ANALOG

INPUTS

+2.048V

0V to

0.1µF

CH0

CH7

VREF

MAX1245

DGND AGND

COM

SCLK

DIN

DOUT

SSTRB

SHDN

0.1µF

CPU

I/O SCK (SK)*

MOSI (SO) MISO (SI)

____________________________Features

♦ Single +2.375V to +3.3V Operation ♦ 8-Channel Single-Ended or 4-Channel

Differential Analog Inputs

♦ Low Power: 0.8mA (100ksps)

10µA (1ksps) 1µA (power-down mode)

♦ Internal Track/Hold, 100kHz Sampling Rate ♦ SPI/QSPI/Microwire/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs ♦ 20-Pin DIP/SSOP Packages

________________Ordering Information

†

PART

MAX1245ACPP MAX1245BCPP MAX1245ACAP 0°C to +70°C MAX1245BCAP 0°C to +70°C 20 SSOP MAX1245BC/D 0°C to +70°C Dice*

Ordering Information continued at end of data sheet.

†

Contact factory for availability of alternate surface-mount

TEMP. RANGE PIN-PACKAGE

0°C to +70°C 0°C to +70°C

20 Plastic DIP 20 Plastic DIP 20 SSOP

packages.

Contact factory for availability.

INL

(LSB)

±1/2 ±1 ±1/2 ±1 ±1

___________________Pin Configuration

TOP VIEW

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM



1 2 3 4 5 6 7 8 9

MAX1245

DIP/SSOP

SCLK

DIN

SSTRB DOUT



DGND

14 13

AGND V

VREFSHDN

MAX1245

SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp.

________________________________________________________________

Maxim Integrated Products

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

ABSOLUTE MAXIMUM RATINGS

VDDto AGND, DGND.............................................. -0.3V to +6V

AGND to DGND.................................................... -0.3V to +0.3V

CH0–CH7, COM to AGND, DGND............ -0.3V to (V

VREF to AGND........................................... -0.3V to (V

Digital Inputs to DGND............................................ -0.3V to +6V

Digital Outputs to DGND........................... -0.3V to (V

Digital Output Sink Current.................................................25mA

Continuous Power Dissipation (T

MAX1245

Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

= +70°C)

DD DD

+ 0.3V) + 0.3V)

+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VDD= +2.375V to +3.3V, COM = 0V, f VREF = 2.048V applied to VREF pin, T

DC ACCURACY (Note 1)

Differential Nonlinearity Offset Error

Channel-to-Channel Offset Matching

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0Vp-p to 2.048Vp-p, 100ksps, 1.5MHz external clock, bipolar input mode)

CONVERSION RATE

Conversion Time (Note 5)

Track/Hold Acquisition Time External clock = 1.5MHz

Internal Clock Frequency

External Clock Frequency

= 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),

CLK

= T

to T

INLRelative Accuracy (Note 2)

CONV

ACQ

MIN

, unless otherwise noted.)

MAX

MAX1245A MAX1245B No missing codes over temperature

Up to the 5th harmonic

50kHz, 2V

-3dB rolloff

Internal clock, SHDN = FLOAT Internal clock, SHDN = V External clock = 1.5MHz, 12 clocks/conversion

SHDN = FLOAT SHDN = V

Data transfer only

p-p

(Note 4)

SSOP (derate 8.00mW/°C above +70°C) ................... 640mW

CERDIP (derate 11.11mW/°C above +70°C).............. 889mW

Operating Temperature Ranges

MAX1245_C_P................................................... 0°C to +70°C

MAX1245_E_P ................................................ -40°C to +85°C

Storage Temperature Range............................ -60°C to +150°C

Lead Temperature (soldering, 10sec)............................ +300°C

CONDITIONS

±0.5 ±1.0

5.5 7.5

35 65

1.5

0.225

0.1 1.5 0 1.5

UNITSMIN TYP MAXSYMBOLPARAMETER

ppm/°C±0.25Gain Temperature Coefficient

Bits12Resolution LSB LSB±1DNL

LSB±0.5 ±4 LSBGain Error (Note 3) ±0.5 ±4

LSB±0.2

dB68SINADSignal-to-Noise + Distortion Ratio dB-76THDTotal Harmonic Distortion dB76SFDRSpurious-Free Dynamic Range

dB-85Channel-to-Channel Crosstalk MHz2.25Small-Signal Bandwidth MHz1.0Full-Power Bandwidth

µs

µs2.0t ns40Aperture Delay

ps<50Aperture Jitter MHz

MHz

2 _______________________________________________________________________________________

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.375V to +3.3V, COM = 0V, f VREF = 2.048V applied to VREF pin, T

ANALOG/COM INPUTS

Input Voltage Range, SingleEnded and Differential (Note 6)

Multiplexer Leakage Current

EXTERNAL REFERENCE

VREF Input Voltage Range (Note 8)

DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current

SHDN Input Mid Voltage SHDN Voltage, Floating

SHDN Maximum Allowed Leakage,

Mid Input

DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low

Output Voltage High Three-State Leakage Current Three-State Output Capacitance

POWER REQUIREMENTS

Positive Supply Voltage Positive Supply Current

= 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),

CLK

= T

to T

INH

INL

HYST

INH

INL IN

FLT

OUT

MIN

, unless otherwise noted.)

MAX

CONDITIONS

Unipolar, COM = 0V Bipolar, COM = VREF/2 On/off leakage current, VIN= 0V or V (Note 7)

VREF = 2.048V

VIN= 0V or V (Note 7)

SHDN = 0V or V

SHDN = open SHDN = open

SINK

SOURCE

CS = V CS = VDD(Note 7)

Operating mode, full-scale input

VDD= 2.375V to 3.3V, full-scale input, external reference = 2.048V

= 5mA = 16mA

=0.5mA

0 to VREF

±VREF/2

0.5

1.2 10Power-down

50mV

0.4

1.0

VDD/2 VDD/2

- 0.3 + 0.3

MAX1245

UNITSMIN TYP MAXSYMBOLPARAMETER

µA±0.01 ±1

pF16Input Capacitance

µA82 120VREF Input Current kΩ18 25VREF Input Resistance µA0.01 10Shutdown VREF Input Current

V2.0V V0.8V V0.2V

µA±0.01 ±1I

pF15C

VVDD- 0.4V V0.4V

µA±4.0I

V VVDD/2V

nA±80

V VVDD - 0.375V

µA±0.01 ±10I

pF15C

V2.375 3.3V

mA0.8 1.3

µA mV±0.3PSRSupply Rejection (Note 9)

_______________________________________________________________________________________ 3

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

TIMING CHARACTERISTICS

(VDD= +2.375V to +3.3V, COM = 0V, TA= T

PARAMETER

Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid

MAX1245

CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold

SCLK Pulse Width Low SCLK Fall to SSTRB ns

CS Fall to SSTRB Output Enable CS Rise to SSTRB Output Disable

SSTRB Rise to SCLK Rise

Note 1: Tested at V Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

= +2.375V; COM = 0V; unipolar single-ended input mode.

been calibrated.

Note 3: External reference (VREF = +2.048V), offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to V Note 7: Guaranteed by design. Not subject to production testing. Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 9: Measured as

VFS(2.375V) - VFS(3.3V)|.

to T

MIN

, unless otherwise noted.)

MAX

CONDITIONS

ACQ

DS DH

Figure 1 ns20 260

Figure 1

Figure 2

CSS

CSH

CH CL

Figure 1

SSTRB

External clock mode only, Figure 1

SDV

External clock mode only, Figure 2

STR

Internal clock mode only (Note 7)

SCK

300t

260t

UNITSMIN TYP MAXSYMBOL

µs2.0t ns200t ns0t

ns240t ns400t ns200t ns0 ns300SCLK Pulse Width High ns

ns240t ns400t ns

__________________________________________Typical Operating Characteristics

(VDD= 2.5V, VREF = 2.048V, f

SUPPLY CURRENT

1.25

1.00

(mA)

0.75

0.50

vs. SUPPLY VOLTAGE

RL = ∞ CODE = 101010100000

= 50pF

LOAD



2.625

2.375

= 20pF

LOAD



2.875 (V)

4 _______________________________________________________________________________________

= 1.5MHz, C

CLK

3.125

3.375

LOAD

0.90

MAX1245-01

0.85

0.80

(mA)

0.75

0.70

0.65

-55 -30 70

= 20pF, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT 

vs. TEMPERATURE

RL = ∞ CODE = 101010100000

20 145120-5 45 95

TEMPERATURE (°C)

MAX1245-02

0.50

0.45

0.40

0.35

0.30

0.25

INL (LSB)

0.20

0.15

0.10

0.05

0.00

2.375

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

2.875

(V)

3.3753.1252.625

MAX1245-03

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

____________________________Typical Operating Characteristics (continued)

(VDD= 2.5V, VREF = 2.048V, f

INTEGRAL NONLINEARITY

0.50

0.45

0.40

0.35

0.30

0.25

INL (LSB)

0.20

0.15

0.10

0.05 0

-55 -30 45

vs. TEMPERATURE

VDD = 2.375V

20-5 70 95 145120

TEMPERATURE (˚C)

CHANNEL-TO-CHANNEL OFFSET MATCHING 

2.375

vs. SUPPLY VOLTAGE

2.875

(V)

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

OFFSET MATCHING (LSB)

0.10

0.05

GAIN ERROR 

0.50

0.45

0.40

0.35

0.30

0.25

0.20

GAIN ERROR (LSB)

0.15

0.10

0.05 0

vs. TEMPERATURE

-55

-5 45 120

-30 20 TEMPERATURE (˚C)

CLK

3.1252.625

= 1.5MHz, C



MAX1245-04

MAX1245-07

3.375

MAX1245-10

145

= 20pF, TA = +25°C, unless otherwise noted.)

LOAD



OFFSET vs. SUPPLY VOLTAGE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

OFFSET (LSB)

0.15

0.10

0.05 0

2.375

CHANNEL-TO-CHANNEL OFFSET MATCHING 

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

OFFSET MATCHING (LSB)

0.10

0.05 0

-55

-30 45

CHANNEL-TO-CHANNEL GAIN MATCHING 

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

GAIN MATCHING (LSB)

0.10

0.05 0

2.375

2.875

(V)

vs. TEMPERATURE

-5 TEMPERATURE (˚C)

vs. SUPPLY VOLTAGE

2.875

2.625 V

(V)

3.1252.625



MAX1245-05

3.375

MAX1245-08

145120

MAX1245-11

3.3753.125

OFFSET vs. TEMPERATURE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

OFFSET (LSB)

0.15

0.10

0.05 0

-55 -30

20-5 70 14512095

TEMPERATURE (˚C)

GAIN ERROR 



2.375 2.875 3.3753.1252.625

vs. SUPPLY VOLTAGE

(V)

0.50

0.45

0.40

0.35

0.30

0.25

0.20

GAIN ERROR (LSB)

0.15

0.10

0.05

CHANNEL-TO-CHANNEL GAIN MATCHING 

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

GAIN MATCHING (LSB)

0.10

0.05 0

-55

vs. TEMPERATURE

-30

-5 45 TEMPERATURE (˚C)



MAX1245

MAX1245-06

MAX1245-09

MAX1245-12

1451209570

_______________________________________________________________________________________

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

____________________________Typical Operating Characteristics (continued)

(VDD= 2.5V, VREF = 2.048V, f

= 1.5MHz, C

CLK

= 20pF, TA = +25°C, unless otherwise noted.)

LOAD

1000

MAX1245

0.25

0.20

0.15

0.10

0.05 0

INL (BITS)

-0.05



-0.10

-0.15

-0.20

-0.25

100

(µA)

0.1

 

AVERAGE SUPPLY CURRENT 



vs. CONVERSION RATE

VREF = 2.5V

DD =

CODE = 101010100000

= ∞



8 CHANNELS

1 CHANNEL

0.1

CONVERSIONS PER CHANNEL PER SECOND (Hz)

101 1k 10k100 100k

MAX1245-13

INTEGRAL NONLINEARITY

   

2048

DIGITAL CODE



4096

12.0

11.5

11.0

10.5

EFFECTIVE NUMBER OF BITS

10.0 1 10 100

-20

-40

-60

AMPLITUDE (dB)

-80

-100

-120 0

 

EFFECTIVE NUMBER OF BITS

vs. INPUT FREQUENCY

MAX1245-14

INPUT FREQUENCY (kHz)

FFT PLOT

= 10ksps

TONE

= 100ksps

SAMPLE



   

10 20 30 40 50

FREQUENCY (kHz)



6 _______________________________________________________________________________________

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

______________________________________________________________Pin Description

1–8 CH0–CH7 Sampling Analog Inputs

9 COM

11 VREF External Reference Voltage Input for analog-to-digital conversion

12, 20 V

13 AGND Analog Ground 14 DGND Digital Ground 15 DOUT

16 SSTRB

17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.

19 SCLK

NAME FUNCTION

Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB.

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1245 down to 10µA (max) supply current;

SHDN

otherwise, the MAX1245 is fully operational. Letting SHDN float sets the internal clock frequency to 1.5MHz. Pulling SHDN high sets the internal clock frequency to 225kHz. See

Positive Supply Voltage

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D con-

version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode).

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance.

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60%.)

Hardware Power-Down

section.

MAX1245

DOUT

a) High-Z to V

DGND

and VOL to V

DOUT



LOAD

50pF

b) High-Z to VOL and VOH to V

LOAD

50pF

DGND

DOUT



DGND

a) VOH to High-Z b) VOL to High-Z

50pF

LOAD



Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time

_______________________________________________________________________________________ 7

DOUT



LOAD

50pF DGND

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

_______________Detailed Description

The MAX1245 analog-to-digital converter (ADC) uses a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). No external hold capacitors are required. Figure 3 is a block diagram of the MAX1245.

MAX1245

The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0–CH7, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels with Tables 2 and 3.

In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected analog input) to AGND.

During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor C sition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on C sample of the signal at IN+.

Pseudo-Differential Input

. The acqui-

HOLD

as a

The conversion interval begins with the input multiplexer switching C

from the positive input, IN+, to the

HOLD

negative input, IN- (In single-ended mode, IN- is simply COM). This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x [(V (VIN-)] from C

to the binary-weighted capacitive

HOLD

) -

DAC, which in turn forms a digital representation of the analog input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and C

charges to the input signal.

HOLD

The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, t

, is the maximum time the device takes to acquire

ACQ

the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by:

= 9 x (RS+ RIN) x 16pF

ACQ

SCLK

INPUT

DIN

SHDN

CH0 CH1 CH2

CH3 CH4 CH5 CH6 CH7

COM VREF



1 2 3

4 5 6

7 8 9

SHIFT

ANALOG

INPUT

MUX

MAX1245

Figure 3. Block Diagram

CONTROL

LOGIC

T/H

INT

CLOCK

12-BIT

SAR ADC

REF

OUTPUT

SHIFT

OUT

12, 20 14 13

DOUT SSTRB

DGND

AGND

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM

SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF  CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

Figure 4. Equivalent Input Circuit

12-BIT CAPACITIVE DAC

VREF

INPUT

MUX

–

SWITCH

HOLD

16pF

TRACK

SWITCH

T/H

ZERO

IN

12k 

HOLD

AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES  FROM THE SELECTED IN+  CHANNEL TO THE SELECTED  IN- CHANNEL.

8 _______________________________________________________________________________________

COMPARATOR

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

where RIN= 12kΩ, RS= the source impedance of the input signal, and t

is never less than 2.0µs. Note

ACQ

that source impedances below 1kΩ do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog input to VDDand AGND, allow the channel input pins to swing from AGND - 0.3V to VDD+ 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDDby more than 50mV or be lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over two milliamperes, as excessive current will degrade the conversion accuracy of the on channel.

To quickly evaluate the MAX1245’s analog perfor-

Quick Look

mance, use the circuit of Figure 5. The MAX1245 requires a control byte to be written to DIN before each conversion. Tying DIN to VDDfeeds in control bytes of $FF (HEX), which trigger single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 alters the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK.

How to Start a Conversion

A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1245’s internal shift register. After CS falls, the first arriving logic “1” bit defines the MSB of the control byte. Until this first “start” bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 1 shows the control-byte format.

The MAX1245 is compatible with Microwire, SPI, and QSPI devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the

Typical Operating Circuit,

the simplest soft-

ware interface requires only three 8-bit transfers to

MAX1245

0V TO

2.048V

ANALOG

0.01µF

INPUT

2.048V C1

0.1µF

Figure 5. Quick-Look Circuit

_______________________________________________________________________________________ 9

CH7

VREF

MAX1245

DGND

AGND

COM

SCLK

DIN

DOUT

SSTRB

SHDN

OSCILLOSCOPE

+2.5V

N.C.

+2.5V

0.1µF

1.5MHz

OSCILLATOR

CH1 CH2

* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)

CH3 CH4

SCLK

SSTRB DOUT*

+2.375V, Low-Power, 8-Channel,

DIF

Serial 12-Bit ADC

Table 1. Control-Byte Format

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

BIT NAME DESCRIPTION

7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.

MAX1245

6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3). 5 SEL1 4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-

1 PD1 Selects clock and power-down modes. 0(LSB) PD0 PD1 PD0 Mode

analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2.

ended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3).

0 0 Power-down (IQ= 1.2µA) 0 1 Unassigned 1 0 Internal clock mode 1 1 External clock mode

Table 2. Channel Selection in Single-Ended Mode (SGL/

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

00 0 + – 10 0 + – 00 1 + – 10 1 + – 01 0 + – 11 0 + – 01 1 +– 11 1 + –

Table 3. Channel Selection in Differential Mode (SGL/

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

00 0 + – 00 1 + – 01 0 + – 01 1 +– 10 0 – + 10 1 – + 11 0 – + 11 1 –+

10 ______________________________________________________________________________________

= 1)

= 0)

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). See Figure 17 for MAX1245 QSPI connections.

Simple Software Interface

Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 1.5MHz.

1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull CS low.

3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 HEX) and, simultaneously, receive byte RB2.

5) Transmit a byte of all zeros ($00 HEX) and, simultaneously, receive byte RB3.

6) Pull CS high.

Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 will contain the result of the conversion padded with one leading zero and three trailing zeros. The total conversion time is a function of the serial clock frequency and the amount of idle time between 8-bit transfers. Make sure that the total conversion time does not exceed 120µs, to avoid excessive T/H droop.

In unipolar input mode, the output is straight binary

Digital Output

(Figure 14). For bipolar inputs, the output is two’s-complement (Figure 15). Data is clocked out at the falling edge of SCLK in MSB-first format.

Clock Modes

The MAX1245 may use either an external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1245. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7–10 show the timing characteristics common to both modes.

External Clock

In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion. SSTRB pulses high for one clock period after the control byte’s last bit. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic low. Figure 8 shows the SSTRB timing in external clock mode.

The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serial clock frequency is less than 100kHz, or if serial-clock interruptions could cause the conversion interval to exceed 120µs.

MAX1245

SCLK

DIN

SSTRB

DOUT

A/D STATE

Figure 6. 24-Clock External-Clock-Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f

14 8 12 16 20 24

SEL2 SEL1 SEL0

START

RB1

IDLE

______________________________________________________________________________________ 11

UNI/

SGL/

BIP

DIF

ACQUISITION

(SCLK = 1.5MHz)

ACQ

PD1 PD0



2.0µs 

B11 MSB

RB2

B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

CONVERSION

RB3

LSB

B0

FILLED WITH  ZEROS

IDLE

CLK

≤

1.5MHz)

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

CSH

SCLK

MAX1245

DIN

DOUT

CSS

Figure 7. Detailed Serial-Interface Timing

SSTRB

SCLK

• • •

SDV

• • •

SSTRB

• • •

SSTRB

• • •

• • • • •

CSH

STR

PD0 CLOCKED IN

Figure 8. External-Clock-Mode SSTRB Detailed Timing

In internal clock mode, the MAX1245 generates its own

Internal Clock

conversion clock internally. This frees the µP from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor’s convenience, at any clock rate from zero to

1.5MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB will be low for a maximum of 7.5µs (SHDN = FLOAT), during which time SCLK should remain low for best noise performance.

An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 9). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1245 and three-states DOUT, but it does not adversely affect an internal clock-mode conversion already in progress. When internal clock mode is

12 ______________________________________________________________________________________

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

MAX1245

SCLK

DIN

SSTRB

DOUT

A/D STATE

14 8

2 3 5 6 7 9 10 11 19 21 22 23

SEL2 SEL1 SEL0

START

IDLE

Figure 9. Internal Clock Mode Timing

CS • • •

CSH

SSTRB • • •

SCLK • • •

PD0 CLOCK IN

DOUT • • •

UNI/

SGL/

BIP

DIF

ACQUISITION

(SCLK = 1.5MHz)

PD1 PD0

2.0µs



SSTRB

CONV

CONVERSION

7.5µs MAX

(SHDN = FLOAT)

CONV

B11

B10 B9 B2 B1

MSB

IDLE

SCK

FILLED WITH 

B0

ZEROS

LSB

CSS

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 10. Internal Clock Mode SSTRB Detailed Timing

selected, SSTRB does not go into a high-impedance state when CS goes high.

Figure 10 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX1245 at clock rates exceeding 1.5MHz, provided that the minimum acquisition time, t

ACQ

, is kept

above 2.0µs.

Data Framing

The falling edge of CS does not start a conversion on the MAX1245. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of

______________________________________________________________________________________ 13

SCLK, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as:

The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after V

is applied.

The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto the DOUT pin.

is toggled before the current conversion is com-

If CS plete, then the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started.

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

The fastest the MAX1245 can run is 15 clocks per conversion with CS held low between conversions. Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros.

Most microcontrollers require that conversions occur in multiples of eight SCLK clocks; 16 clocks per conversion will typically be the fastest that a microcontroller can

MAX1245

drive the MAX1245. Figure 11b shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode.

__________ Applications Information

When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1245 in internal clock mode, ready to convert with SSTRB = high. After the power supplies have stabilized, the internal reset time is 10µs, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on

SCLK

DIN

DOUT

SSTRB

S CONTROL BYTE 0

Power-On Reset

8181

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

DIN will be interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros.

Power-Down

The MAX1245’s automatic power-down mode can save considerable power when operating at speeds below the maximum sampling rate. Figure 13 shows the average supply current as a function of the sampling rate. You can save power by placing the converter in a lowcurrent shutdown state between conversions.

Select power-down via bits 1 and 0 of the DIN control byte with SHDN high (Tables 1 and 4). Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte (Table 5).

Power-down mode turns off all chip functions that draw quiescent current, reducing IDDtypically to 1.2µA.

Figures 12a and 12b illustrate the various power-down sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 4, PD1 and PD0

CONTROL BYTE 1S

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

CONTROL BYTE 2S

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

SCLK

DIN

DOUT

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

14 ______________________________________________________________________________________

S CONTROL BYTE 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8

CONVERSION RESULT 0

CONTROL BYTE 1S

CONVERSION RESULT 1

• • •

+2.375V, Low-Power, 8-Channel,

SHDN

Serial 12-Bit ADC

MAX1245

CLOCK

MODE

SHDN

DIN

DOUT

MODE

SETS EXTERNAL CLOCK MODE

XXXX

11 S 00



12 DATA BITS

POWERED UP

EXTERNAL

XXXXX XXXXX

Figure 12a. Timing Diagram Power-Down Modes, External Clock

CLOCK

MODE

DIN

DOUT

SSTRB

MODE

XXXX

SETS INTERNAL CLOCK MODE

10 S 00

DATA VALID

CONVERSION

POWERED UP

EXTERNAL

SETS SOFTWARE POWER-DOWN

12 DATA BITS

INTERNAL

XXXXX 



SETS EXTERNAL

CLOCK MODE

S11

SOFTWARE

POWER-DOWN

SETS POWER-DOWN

CONVERSION

POWERED UP

DATA VALID

POWER-DOWN

VALID DATA

SOFTWARE

INVALID

DATA

HARDWARE

POWER-

DOWN

POWERED UP

Figure 12b. Timing Diagram Power-Down Modes, Internal Clock

Table 4. Software Power-Down and Clock Mode

PD1 PD0 DEVICE MODE

1 1 External Clock 1 0 Internal Clock 0 1 Unassigned 0 0 Power-Down

______________________________________________________________________________________ 15

Table 5. Hard-Wired Power-Down and Internal Clock Frequency

STATE MODE FREQUENCY

1 Enabled 225kHz

Floating Enabled 1.5MHz

0 Power-Down N/A

DEVICE INTERNAL CLOCK

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

Table 6. Full Scale and Zero Scale

UNIPOLAR MODE BIPOLAR MODE

Full Scale Zero Scale

VREF + COM COM

MAX1245

also specify the clock mode. When software shutdown is asserted, the ADC continues to operate in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results can be clocked out after the MAX1245 has entered a software power-down.

The first logical 1 on DIN is interpreted as a start bit, and powers up the MAX1245. Following the start bit, the data input word or control byte also determines clock mode and power-down states. For example, if the DIN word contains PD1 = 1, the chip remains powered up. If PD0 = PD1 = 0, a power-down resumes after one conversion.

Hardware Power-Down

Pulling SHDN low places the converter in hardware power-down. Unlike the software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the clock frequency in internal clock mode. Letting SHDNfloat sets the internal clock frequency to 1.5MHz. When returning to normal operation with SHDN floating, there is a t delay of approximately 2MΩ x CL, where CLis the capacitive loading on the SHDN pin. Pulling SHDN high sets the internal clock frequency to 225kHz. This feature eases the settling-time requirement for the reference voltage.

External Reference

An external reference is required for the MAX1245. The reference voltage range is 1V to VDD.

At VREF, the input impedance is a minimum of 18kΩ for DC currents. During a conversion, the reference must be able to deliver up to 250µA DC load current and have an output impedance of 10Ω or less. If the reference has higher output impedance or is noisy, bypass it close to the VREF pin with a 0.1µF capacitor.

Transfer Function

Table 6 shows the full-scale voltage ranges for unipolar and bipolar modes using a 2.048V reference.

The external reference must have a temperature coefficient of 4ppm/°C or less to achieve accuracy to within 1LSB over the commercial temperature range of 0°C to +70°C.

Positive Zero Negative

Full Scale Scale Full Scale

VREF/2 + COM + COM

(µA)

Figure 13. Average Supply Current vs. Conversion Rate

Figure 14 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 15 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 500µV (2.048V /

4096) for unipolar operation and 1LSB = 500µV [(2.048V / 2 - -2.048V / 2) / 4096] for bipolar operation.

For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package.

Figure 16 shows the recommended system ground connections. A single-point analog ground (“star” ground point) should be established at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. The ground return to the power supply for the star

COM

AVERAGE SUPPLY CURRENT 

1000

100

0.1

vs. CONVERSION RATE

VREF = 2.5V

DD =

CODE = 101010100000

= ∞

8 CHANNELS

0.1

CONVERSIONS PER CHANNEL PER SECOND (Hz)

1 CHANNEL

101 1k 10k100 100k

-VREF/2



MAX1245-13



Layout, Grounding, and Bypassing

16 ______________________________________________________________________________________

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

OUTPUT CODE

FULL-SCALE

11 . . . 111 11 . . . 110 11 . . . 101

00 . . . 011 00 . . . 010 00 . . . 001

00 . . . 000

(COM)

123

TRANSITION

INPUT VOLTAGE (LSBs)

FS = VREF + COM ZS = COM

1LSB =

FS - 3/2LSB

VREF



4096

Figure 14. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM

ground should be low impedance and as short as possible for noise-free operation.

High-frequency noise in the VDDpower supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1µF and 4.7µF capacitors close to pin 20 of the MAX1245. Minimize capacitor lead lengths for best supply-noise rejection. If the +2.5V power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter (Figure 16).

OUTPUT CODE

VREF



+ COM

ZS = COM

-FS = + COM

1LSB =

- FS

-VREF



2 VREF



4096

( VREF/2)

INPUT VOLTAGE (LSBs)

COM

≤

+FS - 1LSB

011 . . . 111 011 . . . 110

000 . . . 010 000 . . . 001 000 . . . 000

111 . . . 111 111 . . . 110 111 . . . 101

100 . . . 001 100 . . . 000

Figure 15. Bipolar Transfer Function, Full Scale (FS) = VREF / 2 + COM, Zero Scale (ZS) = COM

SUPPLIES

+2.5V

GND

MAX1245

R* = 10Ω

* OPTIONAL

AGNDV

MAX1245

DGND+2.5VDGNDCOM

DIGITAL

CIRCUITRY

Figure 16. Power-Supply Grounding Connection

______________________________________________________________________________________ 17

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+3V

+2.5V

0.1µF

MAX1245

ANALOG 

INPUTS



CH0

CH1 CH2

3 4

CH3

MAX1245

CH4

CH5

CH6

CH7

COM

SHDN

SCLK

DIN

SSTRB

DOUT DGND AGND

VREF

17 16 15



14 13

Figure 17. MAX1245 QSPI Connections

High-Speed Digital Interfacing with QSPI

The MAX1245 can interface with QSPI using the circuit in Figure 17 (f

= 1.5MHz, CPOL = 0, CPHA = 0). This

SCLK

QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own micro-sequencer.

Because the maximum external clock frequency is

1.5MHz, the MAX1245 is QSPI compatible up to 1.5MHz.

4.7µF (POWER SUPPLIES)

SCK PCS0

MOSI

MISO



0.1µF +2.048V

MC683XX

(GND)

CLOCK CONNECTIONS NOT SHOWN

18 ______________________________________________________________________________________

+2.375V, Low-Power, 8-Channel,

Serial 12-Bit ADC

Figure 18 shows an application circuit to interface the

TMS320LC3x-to-MAX1245 Interface

MAX1245 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 19.

Use the following steps to initiate a conversion in the MAX1245 and to read the results:

1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are tied together with the MAX1245’s SCLK input.

2) The MAX1245’s CS pin is driven low by the TMS320’s XF_ I/O port, to enable data to be clocked into the MAX1245’s DIN.

3) An 8-bit word (1XXXXX11) should be written to the MAX1245 to initiate a conversion and place the device into external clock mode. Refer to Table 1 to select the proper XXXXX bit values for your specific application.

4) The MAX1245’s SSTRB output is monitored via the TMS320’s FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1245.

5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four trailing bits, which should be ignored.

6) Pull CS high to disable the MAX1245 until the next conversion is initiated.

XF

CLKX

TMS320LC3x

CLKR

DX

DR

FSR

Figure 18. MAX1245-to-TMS320 Serial Interface

CS

SCLK



DIN

DOUT

SSTRB

MAX1245

SCLK

DIN

SSTRB

DOUT

Figure 19. TMS320 Serial-Interface Timing Diagram

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

______________________________________________________________________________________ 19

MSB B10 B1 LSB

HIGH IMPEDANCE

+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

__Ordering Information (continued)

†

PIN-PACKAGETEMP. RANGEPART

INL

(LSB)

___________________Chip Information

TRANSISTOR COUNT: 2554

±1/220 Plastic DIP-40°C to +85°CMAX1245AEPP ±120 Plastic DIP-40°C to +85°CMAX1245BEPP ±1/220 SSOP-40°C to +85°CMAX1245AEAP

MAX1245

†

Contact factory for availability of alternate surface-mount

±120 SSOP-40°C to +85°CMAX1245BEAP

packages.

________________________________________________________Package Information

INCHES

DIM



MIN

A

0.068

A1

0.002

B

0.010

C

0.004

D E e H L

SEE VARIATIONS



0.205 

0.301

0.025

0˚

MAX

0.078

0.008

0.015

0.008

0.209

0.311

0.037 8˚



MILLIMETERS

MIN

1.73

0.05

0.25

0.09 

5.20

0.65 BSC0.0256 BSC



7.65

0.63

0˚

MAX

1.99

0.21

0.38

0.20 

5.38 

7.90

0.95

8˚

PINS

14 16 20 24 28

INCHES

MIN



0.239

0.278

0.317

0.397

DIM

SSOP

SHRINK

SMALL-OUTLINE

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

PACKAGE



D D D D D

MAX

0.249

0.289

0.328

0.407

MILLIMETERS

MAX

MIN

6.33

6.07

6.33

6.07

7.33

7.07

8.33

8.07

10.33

10.07

21-0056A

Maxim MAX1245BEPP, MAX1245BEAP, MAX1245BCPP, MAX1245AEPP, MAX1245AEAP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual